JPH0582758A - Rom回路用プログラムセル構造 - Google Patents
Rom回路用プログラムセル構造Info
- Publication number
- JPH0582758A JPH0582758A JP8596791A JP8596791A JPH0582758A JP H0582758 A JPH0582758 A JP H0582758A JP 8596791 A JP8596791 A JP 8596791A JP 8596791 A JP8596791 A JP 8596791A JP H0582758 A JPH0582758 A JP H0582758A
- Authority
- JP
- Japan
- Prior art keywords
- region
- cell structure
- cell
- rom circuit
- program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
Landscapes
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT19903A/90 | 1990-03-30 | ||
| IT19903A IT1239989B (it) | 1990-03-30 | 1990-03-30 | Struttura di cella programmata,a bassa capacita' e ad elevata tensione di rottura, per circuiti di memoria a sola lettura |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0582758A true JPH0582758A (ja) | 1993-04-02 |
Family
ID=11162207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8596791A Pending JPH0582758A (ja) | 1990-03-30 | 1991-03-27 | Rom回路用プログラムセル構造 |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0450389B1 (OSRAM) |
| JP (1) | JPH0582758A (OSRAM) |
| DE (1) | DE69112882T2 (OSRAM) |
| IT (1) | IT1239989B (OSRAM) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5291435A (en) * | 1993-01-07 | 1994-03-01 | Yu Shih Chiang | Read-only memory cell |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4268950A (en) * | 1978-06-05 | 1981-05-26 | Texas Instruments Incorporated | Post-metal ion implant programmable MOS read only memory |
| US4359817A (en) * | 1981-05-28 | 1982-11-23 | General Motors Corporation | Method for making late programmable read-only memory devices |
| JPS5830154A (ja) * | 1981-08-17 | 1983-02-22 | Toshiba Corp | 固定記憶半導体装置およびその製造方法 |
-
1990
- 1990-03-30 IT IT19903A patent/IT1239989B/it active IP Right Grant
-
1991
- 1991-03-19 EP EP91104217A patent/EP0450389B1/en not_active Expired - Lifetime
- 1991-03-19 DE DE69112882T patent/DE69112882T2/de not_active Expired - Fee Related
- 1991-03-27 JP JP8596791A patent/JPH0582758A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| DE69112882T2 (de) | 1996-02-15 |
| DE69112882D1 (de) | 1995-10-19 |
| EP0450389A3 (OSRAM) | 1994-02-23 |
| EP0450389B1 (en) | 1995-09-13 |
| IT1239989B (it) | 1993-11-27 |
| IT9019903A1 (it) | 1991-09-30 |
| EP0450389A2 (en) | 1991-10-09 |
| IT9019903A0 (it) | 1990-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100466902B1 (ko) | 비휘발성메모리셀및그메모리셀을액세스하는방법 | |
| US7157773B2 (en) | Nonvolatile semiconductor memory device | |
| US5424567A (en) | Protected programmable transistor with reduced parasitic capacitances and method of fabrication | |
| US5942780A (en) | Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate | |
| US5837554A (en) | Integrated circuit with EPROM cells | |
| US5792670A (en) | Method of manufacturing double polysilicon EEPROM cell and access transistor | |
| US6127696A (en) | High voltage MOS transistor for flash EEPROM applications having a uni-sided lightly doped drain | |
| US5479367A (en) | N-channel single polysilicon level EPROM cell | |
| US5888867A (en) | Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration | |
| JPH11214529A (ja) | Mosデバイスの集積化方法及び半導体チイップ | |
| EP0820103A1 (en) | Single polysilicon level flash EEPROM cell and manufacturing process therefor | |
| US6600188B1 (en) | EEPROM with a neutralized doping at tunnel window edge | |
| US5732012A (en) | Rom cell with reduced drain capacitance | |
| US5486487A (en) | Method for adjusting the threshold of a read-only memory to achieve low capacitance and high breakdown voltage | |
| US20080023763A1 (en) | Threshold-voltage trimming of insulated-gate power devices | |
| JPH0582758A (ja) | Rom回路用プログラムセル構造 | |
| US6573561B1 (en) | Vertical MOSFET with asymmetrically graded channel doping | |
| US5196361A (en) | Method of making source junction breakdown for devices with source-side erasing | |
| US5486486A (en) | Process for the manufacture of an integrated voltage limiter and stabilizer in flash EEPROM memory devices | |
| JPH06237000A (ja) | 不揮発性メモリセルおよびその製造方法 | |
| JPH06342919A (ja) | 不揮発性メモリ装置 | |
| KR100233558B1 (ko) | 반도체 소자의 제조방법 | |
| US5838616A (en) | Gate edge aligned EEPROM transistor | |
| US6455375B1 (en) | Eeprom tunnel window for program injection via P+ contacted inversion | |
| US6852594B1 (en) | Two-step source side implant for improving source resistance and short channel effect in deep sub-0.18μm flash memory technology |