JPH0582679A - Plastic sealed type semiconductor device - Google Patents
Plastic sealed type semiconductor deviceInfo
- Publication number
- JPH0582679A JPH0582679A JP24208091A JP24208091A JPH0582679A JP H0582679 A JPH0582679 A JP H0582679A JP 24208091 A JP24208091 A JP 24208091A JP 24208091 A JP24208091 A JP 24208091A JP H0582679 A JPH0582679 A JP H0582679A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- film
- semiconductor device
- semiconductor chip
- stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は樹脂封止型半導体装置、
特に樹脂封止型半導体装置における半導体チップ表面の
保護構造に関する。BACKGROUND OF THE INVENTION The present invention relates to a resin-sealed semiconductor device,
In particular, it relates to a protective structure for the surface of a semiconductor chip in a resin-sealed semiconductor device.
【０００２】近年の半導体装置の高集積化に伴い、素子
が微細化され、半導体チップ上に形成される回路パター
ンの物理的強度が減少している。そのため、樹脂封止型
半導体装置においては、樹脂封止に際してのストレスか
ら上記回路パターンを保護してその歩留りや信頼性を高
めるために、樹脂封止される半導体チップ上を予め樹脂
膜で覆う構造が提案されているが、その効果が十分でな
く改善が望まれている。With the recent high integration of semiconductor devices, elements have been miniaturized, and the physical strength of circuit patterns formed on semiconductor chips has decreased. Therefore, in the resin-encapsulated semiconductor device, in order to protect the circuit pattern from the stress at the time of resin encapsulation and improve the yield and reliability thereof, a structure in which the resin-encapsulated semiconductor chip is covered with a resin film in advance However, the effect is not sufficient and improvement is desired.
【０００３】[0003]
【従来の技術】従来の樹脂封止型半導体装置における半
導体チップ表面の封止ストレスからの保護は、図４に示
す模式断面図のように、例えばアルミニウム(Al)配線52
が形成され、その上が例えば燐珪酸ガラス（ＰＳＧ）膜
と窒化シリコン（Si3N4)膜とからなるパッシベーション
膜53で覆われた前記半導体チップ51の表面に、ポリイミ
ド等の緻密な単層の樹脂膜54を形成した後に樹脂封止を
行うことによってなされていた。しかし緻密な樹脂膜は
可塑性に乏しいために、モールド樹脂56等により封止
（パッケージング）がなされる際、モールド樹脂等の中
にその熱抵抗を下げるために添加されているシリカ等の
高硬度を有するフィラーの粒子55の圧接によって上記保
護用樹脂膜54の表面に大きなストレス（Ｓ）が加わる
と、そのストレスが殆ど減衰せずに半導体チップ51の表
面に加わって半導体チップ表面の前記Al配線52等で形成
されている回路パターンを破壊したり、また保護用樹脂
膜54中にストレスが残りこの残留ストレスにより経時的
に回路パターンを劣化させるという問題が生じていた。2. Description of the Related Art In a conventional resin-sealed semiconductor device, the surface of a semiconductor chip is protected from sealing stress by, for example, aluminum (Al) wiring 52 as shown in a schematic sectional view of FIG.
On the surface of the semiconductor chip 51 covered with a passivation film 53 made of, for example, a phosphosilicate glass (PSG) film and a silicon nitride (Si 3 N 4 ) film. This is done by forming the resin film 54 and then sealing the resin. However, since a dense resin film has poor plasticity, when it is sealed (packaged) with the mold resin 56, etc., it has a high hardness such as silica that is added to the mold resin to reduce its thermal resistance. When a large stress (S) is applied to the surface of the protective resin film 54 due to the pressure contact of the filler particles 55 having the stress, the stress is applied to the surface of the semiconductor chip 51 with almost no attenuation and the Al wiring on the surface of the semiconductor chip. There has been a problem that the circuit pattern formed by 52 or the like is destroyed, or stress remains in the protective resin film 54, and the residual stress deteriorates the circuit pattern over time.
【０００４】[0004]
【発明が解決しようとする課題】そこで本発明は、モー
ルド樹脂等による封止（パッケージング）に際して、封
止用樹脂に含まれる硬度の高いフィラー粒子によって半
導体チップ表面に及ぼされるストレスを大幅に減衰させ
て、樹脂封止型半導体装置の歩留り及び信頼性を向上す
ることを目的とする。Therefore, the present invention significantly reduces the stress exerted on the surface of the semiconductor chip by the filler particles having high hardness contained in the encapsulating resin when encapsulating (packaging) with the mold resin or the like. Thus, the object is to improve the yield and reliability of the resin-encapsulated semiconductor device.
【０００５】[0005]
【課題を解決するための手段】上記課題の解決は、回路
パターンが形成されパッシベーション膜で覆われた半導
体チップの少なくともワイヤボンディング部を除く領域
上を、緻密な第１の樹脂膜と気泡を含む第２の樹脂膜と
により順次覆った後、樹脂封止がなされてなる本発明に
よる樹脂封止型半導体装置によって達成される。Means for Solving the Problems To solve the above problems, a dense first resin film and bubbles are included in at least a region of a semiconductor chip on which a circuit pattern is formed and covered with a passivation film except a wire bonding portion. This is achieved by the resin-encapsulated semiconductor device according to the present invention in which the resin-encapsulated semiconductor device is sequentially covered with the second resin film and then resin-encapsulated.
【０００６】[0006]
【作用】図１は、本発明の原理説明用模式断面図であ
る。同図において、１は半導体チップ、２は回路パター
ンを模したAl配線、３は無機絶縁膜からなるパッシベー
ション膜、４は緻密な第１の樹脂膜、５は気泡を含む第
２の樹脂膜、６はモールド樹脂、７はモールド樹脂に含
まれる硬度の高いフィラー粒子を示す。1 is a schematic sectional view for explaining the principle of the present invention. In the figure, 1 is a semiconductor chip, 2 is Al wiring imitating a circuit pattern, 3 is a passivation film made of an inorganic insulating film, 4 is a dense first resin film, 5 is a second resin film containing bubbles, 6 is a mold resin, and 7 is a filler particle with high hardness contained in the mold resin.
【０００７】本発明に係る樹脂封止型半導体装置におい
ては、図１に示すように、樹脂封止される半導体チップ
１のAl配線２等による回路パターンが形成されている表
面が、該表面に直に付着する緻密な第１の樹脂膜４とそ
の上に付着する気泡を含む第２の樹脂膜５とからなる２
層構造の表面保護用樹脂膜で覆われる。In the resin-encapsulated semiconductor device according to the present invention, as shown in FIG. 1, the surface of the semiconductor chip 1 to be resin-encapsulated on which a circuit pattern is formed by the Al wirings 2 2 composed of a dense first resin film 4 directly attached and a second resin film 5 containing bubbles attached thereon 2
It is covered with a surface-protective resin film having a layered structure.
【０００８】これによって、例えば樹脂モールドによっ
て樹脂封止（パッケージング）がなされるに際に、モー
ルド樹脂中に熱抵抗を減少させるために混入されている
高硬度のフィラー粒子７が、チップ上に強く圧接されて
も、この圧接のストレス（Ｓ）は気泡を含み可塑性を有
する第２の樹脂膜６によって大部分吸収されて、緻密な
樹脂膜７を介しその下部のAl配線２等よりなる回路パタ
ーンに及ぼされるストレス（Ｓ′）は非常に軽微にな
る。従って樹脂封止過程における回路パターンの破損が
防止され歩留りが向上する。また、樹脂封止に際し上記
表面保護用の樹脂膜中にめり込んだフィラー粒子７によ
るストレスは、上記気泡を含み可塑性を有する樹脂膜５
中の気泡によって吸収されて上記樹脂膜５及び６内に残
留するストレスは大幅に減少する。従って、上記樹脂膜
５及び６内の残留ストレスに起因する経時的な回路パタ
ーンの劣化も防止されて、信頼性が向上する。As a result, for example, when the resin sealing (packaging) is performed by resin molding, the high hardness filler particles 7 mixed in the molding resin for reducing the thermal resistance are provided on the chip. Even if it is strongly pressed, the stress (S) of this pressing is mostly absorbed by the second resin film 6 containing air bubbles and having plasticity, and the circuit composed of the Al wiring 2 and the like thereunder via the dense resin film 7. The stress (S ') exerted on the pattern becomes very small. Therefore, the circuit pattern is prevented from being damaged during the resin sealing process, and the yield is improved. In addition, the stress caused by the filler particles 7 embedded in the resin film for surface protection during resin encapsulation is caused by the resin film 5 having plasticity including the bubbles.
The stress absorbed by the bubbles inside and remaining in the resin films 5 and 6 is greatly reduced. Therefore, the deterioration of the circuit pattern over time due to the residual stress in the resin films 5 and 6 is prevented, and the reliability is improved.
【０００９】[0009]
【実施例】以下本発明を、図示実施例により具体的に説
明する。図２は本発明に係る樹脂封止型半導体装置の一
実施例の模式断面図で、図３は同半導体装置の一実施例
に係る製造工程断面図である。EXAMPLES The present invention will be described in detail below with reference to illustrated examples. 2 is a schematic cross-sectional view of an embodiment of the resin-sealed semiconductor device according to the present invention, and FIG. 3 is a manufacturing process cross-sectional view of the embodiment of the semiconductor device.
【００１０】全図を通じ同一対象物は同一符合で示す。
本発明に係る樹脂封止型半導体装置の一実施例を示す図
１において、11は半導体チップ、12S はAl配線等よりな
る回路パターン、12P はボンディングパッド、13はＰＳ
Ｇ膜及びSi3N4 膜からなる無機質パッシベーション膜、
14は緻密な第１のポリイミド膜、15は気泡を含む第２の
ポリイミド膜、16はモールド樹脂、17はフィラーとして
含有するシリカ粒子、18はリードフレームのチップステ
ージ、19はリードフレームの外部リード、20は導電性接
着材、21は金（Au)等よりなるボンディングワイヤ、22
は樹脂パッケージを示す。Throughout the drawings, the same object is designated by the same reference numeral.
In FIG. 1 showing an embodiment of a resin-sealed semiconductor device according to the present invention, 11 is a semiconductor chip, 12S is a circuit pattern made of Al wiring, 12P is a bonding pad, and 13 is PS.
An inorganic passivation film consisting of a G film and a Si 3 N 4 film,
14 is a dense first polyimide film, 15 is a second polyimide film containing bubbles, 16 is a molding resin, 17 is silica particles contained as a filler, 18 is a lead frame chip stage, and 19 is an external lead of the lead frame. , 20 is a conductive adhesive, 21 is a bonding wire made of gold (Au) or the like, 22
Indicates a resin package.
【００１１】この実施例の樹脂封止型半導体装置は、図
２のように、回路パターン12S が形成され、ボンディン
グパッド12P 部を除く領域上が無機質パッシベーション
膜13で覆わた半導体チップ11上に、前記ボンディングパ
ッド12P 上を除いて、前記無機質パッシベーション膜13
上に直に付着する厚さ２〜３μｍ程度の緻密な第１のポ
リイミド膜14とその上に付着する厚さ２〜３μｍ程度の
気泡を含む第２のポリイミド膜15とからなる２層の樹脂
膜で覆われてなる半導体チップが用いられている。そし
て通常通り、上記半導体チップが、リードフレームのチ
ップステージ18上に例えば導電性接着材によって固着さ
れ、そのボンディングパッド12Pがリードフレームの外
部リード19とボンディングワイヤ21により接続され、例
えば粒径２μｍ程度のシリカ粒子17をフィラーとして含
んだエポキシ等のモールド樹脂16によって樹脂モールド
（パッケージング）された構造を有する。In the resin-sealed semiconductor device of this embodiment, as shown in FIG. 2, a circuit pattern 12S is formed, and a region other than a bonding pad 12P portion is covered with an inorganic passivation film 13 on a semiconductor chip 11, The inorganic passivation film 13 except on the bonding pad 12P.
Two-layer resin consisting of a dense first polyimide film 14 having a thickness of about 2 to 3 .mu.m directly attached on top and a second polyimide film 15 having bubbles of a thickness of about 2 to 3 .mu.m attached thereon. A semiconductor chip covered with a film is used. Then, as usual, the semiconductor chip is fixed on the chip stage 18 of the lead frame by, for example, a conductive adhesive, and its bonding pad 12P is connected to the external lead 19 of the lead frame by the bonding wire 21, and the grain size is, for example, about 2 μm. It has a structure in which it is resin-molded (packaged) with a mold resin 16 such as epoxy containing the silica particles 17 as a filler.
【００１２】この構造においては、樹脂モールドに際
し、モールド樹脂16中にフィラーとして含まれる高硬度
を有するシリカ粒子17によって半導体チップ11に向かっ
て及ぼされるストレスは、半導体チップ11の最上部に形
成された気泡を含む第２のポリイミド膜15中の気泡によ
って吸収されるので、半導体チップ11に形成されている
回路パターン12S に直に大きなストレスを及ぼすことが
なくなり、樹脂モールド工程における特性劣化による歩
留り低下は防止される。また樹脂モールドに際し気泡を
含む第２のポリイミド膜15にめり込んだ上記シリカ粒子
17によって及ぼされるストレスも、このポリイミド膜15
中に含まれる気泡によって吸収されるので、ポリイミド
膜15及び14中に上記シリカ粒子17によるストレスが残留
することもなくなり、この残留ストレスによる、経時的
な回路パターン12S の性能劣化による信頼性の低下も防
止される。In this structure, during resin molding, the stress exerted on the semiconductor chip 11 by the silica particles 17 having a high hardness contained as a filler in the mold resin 16 is formed on the uppermost part of the semiconductor chip 11. Since it is absorbed by the bubbles in the second polyimide film 15 containing bubbles, the circuit pattern 12S formed on the semiconductor chip 11 is not directly subjected to a large stress, and the yield is not reduced due to the deterioration of the characteristics in the resin molding process. To be prevented. Further, the silica particles embedded in the second polyimide film 15 containing bubbles during resin molding.
The stress exerted by 17 also causes this polyimide film 15
Since it is absorbed by the bubbles contained therein, the stress due to the silica particles 17 does not remain in the polyimide films 15 and 14, and the residual stress reduces the reliability due to the performance deterioration of the circuit pattern 12S over time. Is also prevented.
【００１３】上記実施例に用いた緻密な第１のポリイミ
ド膜14と気泡を含む第２のポリイミド膜15とよりなる２
層構造の表面保護用樹脂膜を有する半導体チップは、例
えば下記に示す方法により形成される。2 consisting of the dense first polyimide film 14 used in the above embodiment and the second polyimide film 15 containing bubbles.
A semiconductor chip having a surface-protective resin film having a layered structure is formed, for example, by the method described below.
【００１４】図３(a) 参照 即ち、半導体素子の形成が終わり、Al配線等による回路
パターン12S及びボンディングパッド12P の形成が完了
し、通常通りダイシングライン23の部分を除く上面が前
記ＰＳＧ膜及びSi3N4 膜からなる無機質パッシベーショ
ン膜13で覆われてなる半導体基板111の全面上に、例え
ばN-メチルピロリドン等の溶媒に溶解してなるポリイミ
ド液をスピンコート法により所要の厚さに塗布し、この
塗布膜に例えば 120℃,1.5分、 150℃,1.5分のステップ
乾燥処理を施して、厚さ２μｍ程度の緻密なポリイミド
膜14を形成する。なお、ダイシングライン23上のパッシ
ベーション膜13の除去は、後に行われるワイヤボンディ
ング用開孔の形成の際に同時に行うこともある。Referring to FIG. 3 (a), that is, the formation of the semiconductor element is completed, the formation of the circuit pattern 12S and the bonding pad 12P by Al wiring or the like is completed, and the upper surface excluding the portion of the dicing line 23 is the PSG film and the On the entire surface of the semiconductor substrate 111 covered with the inorganic passivation film 13 made of a Si 3 N 4 film, a polyimide solution prepared by dissolving in a solvent such as N-methylpyrrolidone is applied to a required thickness by a spin coating method. Then, this coating film is subjected to step drying treatment at 120 ° C. for 1.5 minutes and 150 ° C. for 1.5 minutes to form a dense polyimide film 14 having a thickness of about 2 μm. The removal of the passivation film 13 on the dicing line 23 may be performed at the same time when the wire bonding opening is formed later.
【００１５】図３(b) 参照 次いで上記基板上に再び同様の条件でポリイミド液を塗
布し、例えば 150℃、３分の急速乾燥を行い、上記緻密
な第１のポリイミド膜14上に厚さ２μｍ程度の気泡を含
んだ第２のポリイミド膜15を形成する。Next, referring to FIG. 3 (b), a polyimide solution is applied again on the above-mentioned substrate under the same conditions, and rapid drying is carried out, for example, at 150 ° C. for 3 minutes, and a thickness is formed on the dense first polyimide film 14 mentioned above. A second polyimide film 15 containing bubbles of about 2 μm is formed.
【００１６】図３(c) 参照 次いで上記気泡を含む第２のポリイミド膜15を有する半
導体基板上111 上に例えば２μｍ程度の厚さに例えばノ
ボラック系のポジレジスト膜24を塗布し、次いでボンデ
ィングパッド12P 及びダイシングライン23の上部に露光
を行い、次いで例えばエチルセルソルブアセテートによ
り現像を行う。ここで、上記レジスト膜23の露光部に開
孔125A、125B、125C、125D等が形成され、且つその下部
の第１、第２のポリイミド膜14、15にも開孔125A、125
B、125C、125D等が形成される。Referring to FIG. 3 (c), a novolac-based positive resist film 24 is applied to a thickness of, for example, about 2 μm on the semiconductor substrate 111 having the second polyimide film 15 containing bubbles, and then the bonding pad is formed. The 12P and the upper part of the dicing line 23 are exposed, and then developed with, for example, ethyl cellosolve acetate. Here, openings 125A, 125B, 125C, 125D, etc. are formed in the exposed portion of the resist film 23, and the openings 125A, 125 are also formed in the first and second polyimide films 14, 15 thereunder.
B, 125C, 125D, etc. are formed.
【００１７】図３(d) 参照 次いで、上記ポジレジスト膜24をマスクにし弗素系のガ
スによるリアクティブイオンエッチング処理を行い、無
機質パッシベーション膜13にダイシングライン23及びボ
ンディングパッド12P を表出する開孔を形成し、次いで
レジスト膜24を除去し、洗浄を行った後、この基板を 3
50〜400 ℃に加熱して第１のポリイミド膜14と第２のポ
リイミド膜15のキュアーを行う。Next, referring to FIG. 3 (d), using the positive resist film 24 as a mask, a reactive ion etching process using a fluorine-based gas is carried out to expose the dicing line 23 and the bonding pad 12P in the inorganic passivation film 13. Is formed, the resist film 24 is removed, and cleaning is performed.
The first polyimide film 14 and the second polyimide film 15 are cured by heating at 50 to 400 ° C.
【００１８】ここで、半導体基板111 上に積層されてい
るパッシベーション膜13、緻密な第１のポリイミド膜14
及び気泡を有する第２のポリイミド膜15に、ダイシング
ライン23を表出する開孔25A 、25D 等及びボンディング
パッド12P を表出する開孔25B 、25C 等を有する半導体
基板111 が形成される。Here, the passivation film 13 and the dense first polyimide film 14 laminated on the semiconductor substrate 111.
The semiconductor substrate 111 having the openings 25A, 25D for exposing the dicing line 23 and the openings 25B, 25C for exposing the bonding pad 12P are formed on the second polyimide film 15 having the bubbles.
【００１９】図３(e) 参照 次いで、上記半導体基板基板111 をダイシングライン23
でダイシングし、回路パターン12S が形成され、ボンデ
ィングパッド12P 部を除く領域上が無機質パッシベーシ
ョン膜13で覆われ、且つ前記ボンディングパッド12P 上
を除いて、前記無機質パッシベーション膜13上が厚さ２
〜３μｍ程度の緻密な第１のポリイミド膜14と厚さ２〜
３μｍ程度の気泡を含む第２のポリイミド膜15とにより
順次覆われた前記実施例に係る半導体チップが完成す
る。Next, referring to FIG. 3 (e), the semiconductor substrate substrate 111 is diced by the dicing line 23.
Then, the circuit pattern 12S is formed, the region except the bonding pad 12P portion is covered with the inorganic passivation film 13, and the inorganic passivation film 13 has a thickness 2 except the bonding pad 12P.
~ 1 μm dense first polyimide film 14 and thickness 2 ~
The semiconductor chip according to the above-mentioned embodiment completed by being sequentially covered with the second polyimide film 15 containing bubbles of about 3 μm is completed.
【００２０】なお本発明において、半導体チップ上を覆
う緻密な第１の樹脂膜及び気泡を有する第２の樹脂膜
は、上記ポリイミドに限らず、弗素樹脂、エポキシ樹脂
等により形成してもよい。In the present invention, the dense first resin film covering the semiconductor chip and the second resin film having bubbles are not limited to the above polyimide, but may be formed of fluorine resin, epoxy resin or the like.
【００２１】また本発明の構造はモールド封止に限ら
ず、キャステイング封止、ポッティング封止にも適用さ
れる。Further, the structure of the present invention is not limited to mold sealing, but is applied to casting sealing and potting sealing.
【００２２】[0022]
【発明の効果】以上実施例に示したように、本発明に係
る構造においては、モールド等の樹脂封止に際し、封止
用樹脂中に含まれる高硬度のフィラー粒子によって半導
体チップに向かって及ぼされる強いストレスは、半導体
チップの最上部に形成された気泡を含む第２のポリイミ
ド膜中の気泡によって吸収されるので、半導体チップに
形成されている回路パターンに直に大きなストレスを及
ぼすことがなくなり、樹脂封止工程における特性劣化に
よる歩留り低下は防止される。また樹脂封止に際し気泡
を含む第２のポリイミド膜にめり込んだ上記フィラー粒
子によって及ぼされるストレスも、このポリイミド膜中
に含まれる気泡によって吸収されるので、ポリイミド膜
中にストレスが残留することもなくなり、この残留スト
レスによる、経時的な回路パターン12S の性能劣化によ
る信頼性の低下も防止される。As shown in the above embodiments, in the structure according to the present invention, when the resin such as the mold is encapsulated, the high hardness filler particles contained in the encapsulating resin extend toward the semiconductor chip. The strong stress generated is absorbed by the bubbles in the second polyimide film including the bubbles formed on the uppermost part of the semiconductor chip, so that the circuit pattern formed on the semiconductor chip is not directly stressed. The yield reduction due to the characteristic deterioration in the resin sealing step is prevented. Further, the stress exerted by the filler particles embedded in the second polyimide film containing bubbles during resin sealing is also absorbed by the bubbles contained in the polyimide film, so that the stress does not remain in the polyimide film. It is also possible to prevent deterioration of reliability due to performance deterioration of the circuit pattern 12S with time due to this residual stress.
【図面の簡単な説明】[Brief description of drawings]
【図１】 本発明の原理説明用模式断面図FIG. 1 is a schematic sectional view for explaining the principle of the present invention.
【図２】 本発明の一実施例の模式断面図FIG. 2 is a schematic sectional view of an embodiment of the present invention.
【図３】 本発明の一実施例に係る製造工程断面図FIG. 3 is a sectional view of a manufacturing process according to an embodiment of the present invention.
【図４】 従来構造の模式断面図FIG. 4 is a schematic sectional view of a conventional structure.
１ 半導体チップ ２ 回路パターンを模したAl配線 ３ 無機絶縁膜からなるパッシベーション膜 ４ 緻密な第１の樹脂膜 ５ 気泡を含む第２の樹脂膜 ６ モールド樹脂 ７ 硬度の高いフィラー粒子 1 semiconductor chip 2 Al wiring simulating a circuit pattern 3 passivation film made of an inorganic insulating film 4 dense first resin film 5 second resin film containing air bubbles 6 mold resin 7 filler particles with high hardness
Claims (2)
ン膜で覆われた半導体チップの少なくともワイヤボンデ
ィング部を除く領域上を、緻密な第１の樹脂膜と気泡を
含む第２の樹脂膜とにより順次覆った後、樹脂封止がな
されてなることを特徴とする樹脂封止型半導体装置。1. A semiconductor chip in which a circuit pattern is formed and covered with a passivation film is covered with a dense first resin film and a second resin film containing bubbles in order at least on a region except for a wire bonding portion. A resin-encapsulated semiconductor device, which is then resin-encapsulated.
る第２の樹脂膜がポリイミド樹脂よりなることを特徴と
する請求項１記載の樹脂封止型半導体装置。2. The resin-encapsulated semiconductor device according to claim 1, wherein the dense first resin film and the second resin film having bubbles are made of a polyimide resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24208091A JPH0582679A (en) | 1991-09-20 | 1991-09-20 | Plastic sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24208091A JPH0582679A (en) | 1991-09-20 | 1991-09-20 | Plastic sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0582679A true JPH0582679A (en) | 1993-04-02 |
Family
ID=17083991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24208091A Withdrawn JPH0582679A (en) | 1991-09-20 | 1991-09-20 | Plastic sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0582679A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006332576A (en) * | 2005-04-25 | 2006-12-07 | Matsushita Electric Works Ltd | Semiconductor device and manufacturing method thereof |
| CN114420867A (en) * | 2022-01-11 | 2022-04-29 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
-
1991
- 1991-09-20 JP JP24208091A patent/JPH0582679A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006332576A (en) * | 2005-04-25 | 2006-12-07 | Matsushita Electric Works Ltd | Semiconductor device and manufacturing method thereof |
| CN114420867A (en) * | 2022-01-11 | 2022-04-29 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
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