JPH0582542A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the penetration of ions of a channel in the case where the introduction of an impurity into a source and a drain is performed by implantation, and to reduce the introduction of the impurity into a gate electrode by a method wherein before the introduction of the impurity into the source and the drain is performed, the upper surface only of the gate electrode is covered with an insulating film. CONSTITUTION:A gate electrode 2 is provided on the upper surface of a semiconductor substrate 4 and after the upper surface only of the electrode 2 is covered with an insulating film 1, an impurity is introduced in a source 5 and a drain 6, which are located in the substrate 4, through the whole surface of the substrate 4. For example, an SiO2 film 3 of a film thickness of 10 to 40nm or thereabouts is formed on a P-type substrate 4 of a surface concentration of 1X10<16>cm<-3> or thereabouts and a conductive layer 2 consisting of a polysilicon layer is formed thereon in a film thickness of 0.2 to 0.5mum. Then, a primary insulating film 1 consisting of an SiO2 film is formed. After the film 1 is patterned by etching along with the layer 2, phosphorus is ion- implanted on the conditions of E=70keV 1E13cm<-2> and phosphorus primary diffused layers 5 and 6 having a polarity opposite to that of the substrate 4 are formed in the substrate 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOSLDD type transistor, which prevents ion penetration through a channel of a semiconductor substrate when introducing impurities into a source / drain. Pertain to.

[0002]

2. Description of the Related Art Conventionally, in this type of semiconductor device manufacturing method,
When the impurity implantation of the source / drain is performed by ion implantation, the gate electrode is thin, or the gate electrode is formed of polysilicon, and if the acceleration voltage of ion implantation is high, it will penetrate through the gate electrode, There is a risk that impurities may be introduced into the channel region. or,
When polysilicon is used for the gate electrode, N-type or P-type is doped at a high concentration, but when the impurity introduction into the source / drain is an impurity having conductivity opposite to that of the gate electrode, the gate electrode Since the impurities of the reverse conductive electrode are introduced up to this point, there is a drawback that the resistance of the gate electrode becomes high. For example, since a gate electrode made of polysilicon usually has columnar crystal grains, it happens that the ions implanted at the crystal grain boundaries reach the channel region instead of staying in the gate electrode. The impurity concentration of the channel is locally reduced, which has a drawback of lowering Vth.

[0003]

SUMMARY OF THE INVENTION In order to eliminate the above-mentioned drawbacks of the conventional example, the present invention provides a method of manufacturing a semiconductor device of this type in which ion penetration into a channel when impurities are introduced into the source / drain by implantation. While preventing
The purpose is to reduce the introduction of impurities into the gate electrode when introducing impurities into the source / drain.

[0004]

In order to achieve the above object, the present invention is such that in the semiconductor device as described above, the gate electrode is covered with an insulating film when impurities are introduced into the source / drain. More specifically, in the method of manufacturing a semiconductor device, a step of forming an insulating layer of SiO _{2 on} a surface of a semiconductor substrate, forming a conductive layer of polysilicon, and further forming an insulating layer 2; A step of simultaneously etching the film and the insulating layer 2 of SiO ₂ using a photolithography technique;
Gate electrode, and using the gate electrode as a mask, forming a phosphorus diffusion layer having a polarity opposite to that of the substrate, forming a vertical layer made of an insulating material adjacent to a side surface of the gate electrode, A step of forming an insulating layer 3 on the surface of the electrode, and a step of forming an arsenic diffusion layer 2 having a polarity opposite to that of the substrate so as to have an impurity concentration higher than that of the diffusion layer by using the gate electrode and a vertical layer as a mask. And a step of forming a contact on the diffusion layer 2.

According to the method of manufacturing a semiconductor device of the present invention,
Since the implanted ions pass through the amorphous layer at least once, they are scattered and the possibility of passing through the grain boundaries is greatly reduced. Also, when introducing P-type source / drain impurities into N-type polysilicon by ion implantation, for example, if BF ₂ 70 keV 5 × 10 ¹⁵ cm ⁻² is implanted, the range of BF ₂ 70 keV is about 60 nm. Therefore, if a 60 nm oxide film is formed on the gate electrode,
0% could be cut.

[0006]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. In the drawing, 4 is a semiconductor substrate, 3 is a gate oxide film, 2 is a conductive layer forming a gate electrode, 1 is an insulating film of primary SiO ₂ covering the upper surface of the conductive layer, 5 and 6 are primary layers of phosphorus. Diffusion layer, 7, 8 and 9 are CVD
The films 10, 11 and 12 are SiO ₂ secondary insulating films covering the upper surface of the conductive layer 2, and 13 and 14 are arsenic secondary diffusion layers.

1 to 7 sequentially show manufacturing steps of a semiconductor device according to the present invention.

First, as a first step, an insulating film 3 as a gate oxide film is formed on a semiconductor substrate 4, and a conductive layer 2 forming a gate electrode is formed on the insulating film 3, and further, An insulating film 1 of SiO ₂ is formed on the conductive layer 2. In this embodiment, the surface concentration of the semiconductor substrate is 1
A P-type substrate doped with about 10 ¹⁶ cm ⁻³ is used, and the insulating film 3 is a SiO ₂ film with a thickness of about 10 to 40 nm. The conductive layer 2 is made of high-concentration N-type doped polysilicon, but it may be a so-called polycide having two layers of polysilicon and silicide (Wsi, MoSi, etc.). The thickness of the conductive layer is selected in the range of 0.2 to 0.5 μm. Although the primary insulating film 1 is formed from SiO ₂ of CVD, which may be a polysilicon SiO ₂ film formed by thermal oxidation.

Next, in a second step, as shown in FIG. 2, the primary insulating film 1 and the conductive layer 2 are removed by dry etching after pattern etching by photolithography. A step is formed in the insulating film 3 due to overetching during etching.

As a third step thereafter, as shown in FIG.
On the semiconductor substrate 4, a phosphorus primary diffusion layer 5 having a polarity opposite to that of the substrate 5,
6 is formed. In this embodiment, phosphorus is used as E = 70 keV, 1
Ion implantation is performed at E13 cm ^-2 . At the time of this ion implantation, implantation into the channel is completely blocked by the primary insulating film 1 and the conductive layer 2. By subsequent annealing, these primary diffusion layers 5 and 6 come to diffuse to the vicinity of the edge of the conductive layer 2.

Further, as a fourth step, as shown in FIG. 4, an insulating film 7 of a CVD film is formed so as to cover the entire primary diffusion layers 5, 6, the conductive layer 2, and the semiconductor substrate 4. In the present embodiment, the CVD method is used to obtain Si with a thickness of about 0.4 μm.
An O ₂ film is formed. This film may be a conductive film such as polysilicon.

Thereafter, as a fifth step, as shown in FIG. 5, the vertical layer 8 of the insulating film 7 left only on the side surface of the conductive layer 2,
9 is formed. This vertical layer is formed adjacent to the conductive layer 2 and partially covering the primary diffusion layers 5 and 6.
This is obtained by a method of etching the entire surface (etchback method) by anisotropic dry etching of SiO ₂ . At this time, the SiO ₂ film 7 existing on the side surface of the conductive layer 1
Thickness of the thicker than other portions, if the film by a thickness partial etching of the SiO ₂ film, so only the SiO ₂ film of the side portion is left.

Subsequently, as a sixth step, as shown in FIG. 6, SiO ₂ films 10, 11 and 12 are formed so as to cover the surface of the conductive layer 2 and the exposed surfaces of the primary diffusion layers 5 and 6. .. This SiO ₂ film is easily obtained by the thermal oxidation method,
This is performed for the purpose of preventing the channeling during the subsequent ion implantation and recovering the damage on the surface of the Si substrate during the etch back in the previous step. The film thickness of SiO ₂ as the secondary insulating film is about 20 nm on the surface of the Si substrate.

Finally, as a seventh step, as shown in FIG. 7, secondary diffusion layers 13 and 14 are formed by ion implantation using the vertical layers 8 and 9, the conductive layer 2 and the insulating film 10 as a mask. In this embodiment, the films 11 and 12 are penetrated,
Arsenic was ion-implanted at 70 keV and 5E15 cm ^{−2 so} that the resistance value of the diffusion layer could be sufficiently lowered without penetrating the conductive layer 2. After that, an impurity is activated through an annealing process of N _{2 at} 900 ° C. for about 30 minutes. In this way, a MOSLDD transistor is manufactured.

When the transistor manufactured by the method of the present invention as described above is compared with the conventional transistor, the result is that the leakage current of the transistor provided with the primary and secondary insulating layers of the present invention is smaller than that of the conventional transistor. Is coming out.

As shown in the above embodiments, in the method of manufacturing a semiconductor according to the present invention, after covering only the upper surface of the gate electrode projecting on the upper surface of the semiconductor substrate with the primary insulating film, the entire surface of the semiconductor substrate is covered. A primary impurity is diffused and introduced into the substrate, then a CVD film is formed on the side surface of the gate electrode, and only the upper surface of the gate electrode is covered with a secondary insulating film. The secondary transistor is formed by introducing and diffusing secondary impurities into the substrate, and the manufactured transistor prevents the penetration of ions into the channel of the source / drain implanter due to the presence of the primary and secondary insulating films. It is possible to prevent the decrease of the Vth of the transistor and to improve the yield as well as to prevent the injection of the source / drain implanter into the gate electrode. For it is possible to, it is possible to keep the resistance of the gate electrode lower, but also has an advantage that can correspond to high speed and can be reduced to increase the Poly-Si resistor.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step of a manufacturing method according to the present invention.

FIG. 2 is a sectional view showing a second step following FIG.

FIG. 3 is a sectional view showing a third step following FIG.

FIG. 4 is a cross-sectional view showing a fourth step following FIG.

5 is a sectional view showing a fifth step following FIG. 4. FIG.

6 is a sectional view showing a sixth step following FIG. 5. FIG.

7 is a sectional view showing a seventh step following FIG. 6. FIG.

[Explanation of symbols]

 1 Primary Insulation Film 2 Conductive Layer 3 Insulation Film 4 Semiconductor Substrate 5,6 Primary Diffusion Layer 7,8,9 CVD Film 10, 11, 12 Secondary Insulation Film 13,14 Secondary Diffusion Layer

Claims (2)

[Claims] 1. A gate electrode is provided on the upper surface of a semiconductor substrate,
A method for manufacturing a semiconductor device, characterized in that only an upper surface of the gate electrode is covered with an insulating film, and then impurities of source / drain are introduced into the substrate from the entire surface of the semiconductor substrate. 2. A primary insulating film is formed only on the upper surface of a gate electrode provided on the upper surface of a semiconductor substrate, and then primary impurities are diffused and introduced into the substrate from the entire surface of the semiconductor substrate. After forming a vertical layer on the side surface of the electrode and covering only the upper surface of the gate electrode with a secondary insulating film,
A method of manufacturing a semiconductor device, wherein secondary impurities are introduced and diffused into the substrate from the entire surface of the semiconductor substrate.