JPH0581205A - Electronic device - Google Patents

Abstract

PURPOSE:To provide an electronic device capable of rewriting program data without unloading a program ROM from an electronic device body in an electronic notebook provided with an F-ROM as a program storing part. CONSTITUTION:When a memory card 40 is set to the electronic device and a data erasing/writing program is transferred from an external device through a communication terminal 51b, a CPU 51 temporarily writes the program in a RAM 52. Then the CPU 51 reads out the program temporarily written in the RAM 52 and erases program data stored in a ROM 54 in accordance with the procedure of the read program. After completing program erasing processing, the CPU 51 reads out program data stored in a ROM 41 and successively writes the read program data in their corresponding addresses in the ROM 54 to rewrite the program data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device such as an electronic notebook, and more specifically, to an electrically erasable program ROM mounted on an electronic device main body without removing the program ROM. The present invention relates to an electronic device capable of rewriting program data.

[0002]

2. Description of the Related Art This type of electronic notebook has a ROM as a program storage unit. As a ROM,
A mask ROM in which data (program data) cannot be rewritten, an ultraviolet erasable PROM in which data can be rewritten but requires rewriting, and the like are used. By the way, recently, a flash EEPROM is often used as a ROM of this type. Flash E
Since the EPROM can be rewritten more easily than the conventional ROMs, it is useful for electronic devices that require periodic version upgrades and electronic devices that require internal program updates and replacements. Is.

Here, the flash EEPROM is F
flash-ElectricalErasable
Programmable Read Only Mem
It is an abbreviation for "oly" (hereinafter abbreviated as F-PROM), and is an electrically erasable program ROM.
The F-PROM is a semiconductor memory having the following features.

The entire memory contents can be erased by refreshing it in a few tens of seconds. Therefore, the erasing time is fast, and a large capacity element can be mass-produced.

An erasing window unlike the conventional ultraviolet erasing type PROM is not necessary, and the erasing time is extremely fast. Incidentally, the UV erasable PROM takes 10 to 20 minutes.

Erasing and writing of memory contents is done by general C
It can be easily executed by using PU to create a program to access in a predetermined procedure.

At the time of erasing / writing, a 12V DC voltage is applied to V
It is performed by supplying it to the pp pin. In addition, 5V is supplied during normal reading.

The data erasure of the F-PROM can be executed by the CPU of the electronic notebook even if it is incorporated in the electronic notebook by preparing a specific DC voltage and an erasing / writing program. Therefore, originally, rewriting is possible without removing the F-PROM from the electronic notebook.

[0009]

However, in an electronic notebook which uses only one F-PROM as a storage element, the erase / write program has a place to store only in the F-PROM. Where F-PRO
The data erasing of M has only the function of erasing all the data of the F-PROM at once. Therefore, if the erasing program is executed, the erasing program itself is also erased, and it becomes impossible to execute subsequent programming.
That is, in the electronic notebook that uses only one F-PROM, the data cannot be rewritten without removing the F-PROM from the electronic notebook.

Therefore, in an electronic notebook that uses only one F-PROM as a ROM, when rewriting the data content of the F-PROM, the F-PROM has been removed from the electronic notebook and erased by a dedicated writing device. After the rewriting, the troublesome work of reattaching the electronic notebook is required.

The present invention solves the problem of the prior art as described above, and an object thereof is to remove an electrically erasable program ROM (F-PROM) from an electronic device main body (notebook main body). The present invention provides an electronic device in which program data can be easily rewritten without the need.

[0012]

An electronic device according to the present invention includes a program storage unit in which a program for erasing / writing data is stored in an electronic device main body having an electrically erasable program ROM mounted therein. An electronic device in which an external storage device equipped with a storage unit in which program data is written is connected, the program stored in the program ROM is erased, and the program stored in the storage unit is rewritable. , An erasing program starting means for activating an erasing program stored in the program storage section when the external storage device is connected, and a program data erasing means for erasing the program written in the program ROM according to the erasing program , A writing program for activating a program for writing the program stored in the program storage section Ram activation means and, the program data in accordance with said data write program is erased RO
M is provided with a data writing unit for writing the program data stored in the storage unit, whereby the above object is achieved.

[0013]

According to the above system configuration, the program ROM,
Alternatively, when the data erasing / writing program is transferred to the storage means mounted in the electronic device main body through the communication terminal provided in the electronic device main body and the external storage device is set in the electronic device main body, the control means First erases the program data stored in the program ROM according to the data erasing / writing program. Then, the program and data stored in the storage unit mounted on the external storage device are read out, and then the read program data are sequentially written into the corresponding addresses of the program ROM. As a result, the program data can be rewritten without removing the program ROM from the electronic apparatus main body.

[0014]

EXAMPLES The present invention will be described below with reference to examples.

An electronic notebook 1 which is an example of the electronic device of the present invention.
As shown in FIG. 1, it has a notebook body 10 and a cover 20 that can be opened and closed with respect to the notebook body 10, and both are electrically connected. The notebook body 10 is provided with a display unit 11, a card operation key 13, and the like. On the other hand, the cover 20 is provided with a key input section 51a including a ten-key pad 23 and the like. In addition, an insertion hole (card slot) 14 is formed in the lower end surface of the notebook body 10 so that a memory card 40 as an external storage device can be inserted and taken out. When the memory card 40 is inserted into the insertion hole 14, the connector 30 provided at the leading edge of the memory card 40 is connected to the female connector formed inside the insertion hole 14, whereby the memory card 40 and the electronic notebook 1 are electrically connected. Connected to.

FIG. 2 shows a circuit configuration of the electronic notebook 1 and the memory card 40 connected thereto. The CPU 51 equipped in the notebook main body 10 serves as a control center of this system and performs various controls described below. For example, when data is input by the operator via the key input unit 51a, the CPU 51 once writes this input data in the RAM 52 according to the control program stored in the ROM 54. The data once written in the RAM 52 is the CPU 51
After that, it is read out and displayed on the display unit 11 which is, for example, a liquid crystal display device having a dot matrix configuration. This display operation is performed via the display circuit 12.

The ROM 54 is composed of the above-mentioned F-PROM and stores program codes for various controls.
The program code can be rewritten as described later. This rewriting is performed when updating the version.

The power supply control unit 53 controls the supply of the 12V DC voltage necessary for rewriting the control program code stored in the ROM 54 by the control signal from the CPU 51, that is, for erasing / writing the program code to the ROM 54. To do. This DC voltage of 12 V is generated internally or is externally supplied through a jack 53a with a power supply adapter or the like.

The circuit configuration of the memory card 40 is as follows. Signal lines such as an address bus and a data bus that allow the CPU 51 to access the ROM 41 in the memory card 40 are connected to the connector 30. The ROM 41 stores program data for program rewriting.

Rewriting of the program code stored in the ROM 54 is performed by the CPU 51 according to an erasing / writing program installed in the ROM 41 of the memory card 40.
Below, the CPU 5 in rewriting the program code
The control procedure of No. 1 will be described with reference to the flowcharts shown in FIGS.

When the main flow shown in FIG. 3 starts, the CPU 51 firstly executes the memory card 4 in step L1.
It is determined whether 0 is set in the electronic notebook 1. When confirming that the setting has been made, the CPU 51 proceeds to step L.
2 erases data from an external device via the communication terminal 51b.
It is determined whether the program data of the writing program has been transferred. When it is confirmed that the program data has been transferred, the program data is written in the RAM 52.

Then, in step L3, the reading of the data erasing / writing program which is written in the RAM 52 is started, and the control content is switched to the control content in accordance with the data erasing / writing program.

Next, the CPU 51 issues a control signal to the power supply control section 53 by program control in step L4,
Vpp of ROM54 which was initially applied with a DC voltage of 5V
A DC voltage of 12V is applied to the terminals. In addition, electronic notebook 1
Is not equipped with a DC voltage supply circuit of 12V, it is supplied from an external power source. Next, in step L5, the CPU 51 executes an erasing process subroutine for erasing the program code in the ROM 54 according to the erasing program.
The contents of this subroutine are shown in FIG.

The details will be described below. CPU51
After confirming that the DC voltage of 12 V is applied to the Vpp terminal of the ROM 54, first, in step M1, data of all bytes stored in the memory area of the ROM 54 is sequentially read, and 00 is written in all the read bytes ( M
2). That is, in the processing in steps M1 to M2, all addresses are sequentially read, and if there is an address other than 00,
This is a routine in which 00 is written there and finally all bytes are set to 00. Next, the CPU 51 executes n in step M3.
Is set to 0. Here, n is the step M4 M13
And M13, the number of tries of the erasing process is not performed, and if the data erasing is not performed, the number of tries n is incremented to n + 1 in step M4, and the erasing process is retried. The number of tries n is set to, for example, n = 1000 as shown in step M13. If the erasing process cannot be performed, the routine shown in steps M4 to M10 and M14 is repeated 1000 times.

The contents will be described below. CPU51
First, in step M5, the erase command is input to the ROM 54 twice. Then, after the waiting time of 9.5 ns shown in step M6, all the data in the ROM 54 is erased at once, so if it is confirmed that the waiting time has passed, the address is set to the head address in step M7. A process for confirming that all data has been erased at once is started.

That is, first, in step M8, the ROM 54
Input the erase verify command (erase confirmation command) and address information to. Then, the waiting time 6.
After a lapse of 5 μs (M9), a response signal indicating whether or not the data at the corresponding address has been erased is transmitted from the ROM 54. Based on this response signal, it is determined at step M10 whether verification is OK (erase OK).

When it is confirmed that the number of tries has not been erased, it is then determined in step M13 whether or not the number of tries n has reached 1000 times. If not, the process proceeds to step M4, where the number of tries n is n + 1. Is incremented, and the same processing as above is performed again.

On the other hand, at step M13, the number of tries n is 1
If the number has reached 000, proceed to step M14,
Executes fail processing and returns to the main flow. When the fail process is performed, the write process subroutine shown in step L6 is not performed, and RO is performed in step L7.
The DC voltage applied to the Vpp terminal of M54 changes from 12V to 5
Descend to V. Next, in step L8, it is determined that the process has not ended normally, and a fail display is displayed on the display unit 11 (L1
0), notify the operator to that effect. When it is confirmed in step L11 that the memory card 40 has been removed, this process ends.

On the other hand, if it is determined in step M10 that the verification is OK, then in step M11 it is determined whether or not the address for erasure confirmation has reached the final address. After returning, the write processing subroutine described below is executed.

On the other hand, if it is determined that the address is not the final address, the erase confirmation of the next address is performed (M
12), The process after step M8 is performed again.

Next, the subroutine of the writing process will be described. When this subroutine starts, the CPU
First, at step N1, 51 is R at the head address of ROM 54.
In order to write the data stored in the head address of the OM42, the address information and the setup command are stored in the ROM5.
4 and ROM 42 respectively.

Next, the CPU 51 proceeds to step N2, where n '
Set to 0. Here, n'is the step N4 to N1.
It means the number of trials of the writing process indicated by 0 and N13. This number of tries n'is set to, for example, n '= 25 as shown in step N13, and if the write processing cannot be performed, steps N4 to N10 and N13 are performed.
The routine indicated by is repeated 25 times. The contents will be described below.

First, the CPU 51 executes the ROM in step N3.
One byte of write data is read from the master data address 42. Next, in step N5, a write command and address information are input to the ROM 54, and subsequently the read 1-byte data is input to the ROM 54 in step N6. Then, the waiting time 1 shown in step N7
When 0 μs has elapsed, this data is written, so if it is confirmed that the data has been written, the next step N
In step 8, a write verify command (write confirmation command) is input to the ROM 54. Then, a response signal indicating whether or not the corresponding address has been written is sent from the ROM 54 after the waiting time 6 μs shown in step N9 elapses. Therefore, it is determined in step N10 whether the verification is OK (write OK) by the response signal. To judge.

When the CPU 51 confirms that the writing has not been performed in step N10, it determines in step N13 whether or not the number of trials n'has reached 25 times. If the number of tries n'has not reached 25, the process proceeds to step N4, where the number of tries n'is incremented to n '+ 1, and the same processing is repeated for the routines of steps N4 to N10.

On the other hand, at step N13, the number of tries n is 2
When it is confirmed that the number of times has reached 5, the process proceeds to step N14, the fail process is executed, and the process returns to the main flow of FIG. When the fail processing is performed, step L7
DC voltage applied to Vpp terminal of ROM 54 is 12V
To 5V. Next, in step L8, it is determined that the process has not ended normally, and a fail display is displayed on the display unit 11 (L
10), Notify the operator to that effect. When it is confirmed in step L11 that the memory card 40 has been removed, this process ends.

On the other hand, if it is determined in step N10 that the write verify is OK, then step N1
At 1, it is determined whether the address of the ROM 54 has reached the final address.

When it is confirmed that the address for confirmation of writing is not the final address, the write address and the setup command are moved to the next address in step N12 in order to write the data to the next address, and the process proceeds to step N2. Then, the process from step N2 onward is repeated.

On the other hand, if the final address is confirmed in step N11, the process returns to the main flow of FIG. When it is confirmed that the process has been completed, the message is displayed on the display unit 11 in step L9. When the confirmation process of step L11 is completed, the series of processes described above is completed.

In the above embodiment, the R is written in accordance with the data erasing program transferred via the communication terminal 51b.
Although the rewriting of the OM 54 has been performed, this data erasing / writing program may be stored in the empty area of the ROM 54 and transferred to the RAM 52 to perform the rewriting process similar to the above.

[0040]

According to the electronic device of the present invention as described above, the program data in the program ROM is automatically erased in accordance with the data erasing / writing program transferred from the program ROM or the external storage device to the storage means. The new program data stored in the storage unit mounted on the external storage device is automatically written in the program ROM. Therefore, according to the electronic device of the present invention, the data can be easily rewritten without removing the program ROM from the main body of the electronic device. Therefore, there is an advantage that processing such as version upgrade can be performed quickly and reliably.

[Brief description of drawings]

FIG. 1 is a perspective view showing an electronic notebook according to the present invention.

FIG. 2 is a block diagram showing a circuit configuration of the electronic notebook of the present invention.

FIG. 3 is a flowchart showing a main flow of a data rewriting procedure of the electronic notebook of the present invention.

FIG. 4 is a flowchart showing a subroutine of an erasing program.

FIG. 5 is a flowchart showing a subroutine of a writing program.

[Explanation of symbols]

 1 electronic notebook 10 notebook main body 11 display section 30 connector 40 memory card 41, 42 ROM 51 CPU 53 power supply control section 54 program ROM (F-PROM)

Claims (1)

[Claims] 1. A program RO electrically erasable
An external storage device including a storage unit in which program data is written is connected to the electronic device main body in which M is installed,
An electronic device in which a program stored in the storage unit is rewritable by erasing a program written in the program ROM, and a data erasing / writing program stored in the program ROM or transferred from an external storage device. Storage means for temporarily storing the received data erasing / writing program, the data erasing / writing program stored in the storing means, and program data stored in the program ROM according to the data erasing / writing program. An electronic device comprising: a control unit that erases the program stored in the storage unit and writes the program in the program ROM.