JPH0581168A - Direct memory access circuit - Google Patents

Abstract

PURPOSE:To make it possible to perform a data transfer at a high speed by a single transfer system. CONSTITUTION:In a direct memory access circuit performing a direct memory access via a bus 103 connecting plural processing means 101 and a memory 102, a clock generation means 111 generating a clock signal having a cycle corresponding to the minimum time necessary for the access for the memory 102, a mediation means 112 synchronizing the clock signal, validating either one of the access demand from plural processing means 101, notifying to the pertinent processing means 101 and endowing the access demand with the usage right of the bus 103 for one cycle of the clock signal, a synchronizing signal generation means 113 synchronizing the clock signal, generating a synchronizing signal corresponding to each procedure of the access for the memory 102 and transmitting it to the memory 102 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access circuit (hereinafter abbreviated as a DMA circuit) for controlling data transfer between an input / output device such as an image scanner and a memory.
Regarding

With the recent increase in the capacity and cost of semiconductor memories, it has become possible to provide a large capacity buffer memory between an input / output device and an interface circuit. In response to this, SCSI (Small Computer System)
It is desired to connect a host computer with an input / output device that requires high-speed synchronous transfer, such as an image scanner, using a standard interface (such as a stem interface). DMA capable of high-speed processing between DMA transfers
Circuits are needed.

[0003]

2. Description of the Related Art Generally, there are three methods of DMA transfer, a single transfer method, a demand transfer method, and a burst transfer method.

In the single transfer system, the bus is released every time data of a bus width (for example, 1 byte) is transferred, so that a plurality of input / output devices can perform data transfer alternately. On the other hand, the transfer rate is relatively slow because arbitration processing of the bus usage right is required for each 1-byte transfer.

On the other hand, in the demand transfer method, once the bus use right is once acquired, the bus use right is held and a plurality of bytes are contiguous unless there is a DMA request having a higher priority than itself. The data transfer can be performed at a high speed because the data is transferred by the transfer. However, a high priority channel may occupy the bus.

Similarly, in the burst transfer method, the right to use the bus is held until the transfer of the required number of bytes is completed, so that the data transfer can be performed at the highest speed among the three methods. However, like the demand transfer, one channel occupies the bus.

Therefore, in applications where one channel is not allowed to occupy the bus, there is no choice but to adopt the single transfer system DMA transfer and sacrifice the transfer speed.

For example, in an image scanner, if a huge amount of image data read by an image reading unit is stored in a buffer memory and then read out again and sent out through an interface circuit, the reading process and the sending process are required. Due to the time, the reading speed of the document is substantially reduced. Therefore, in parallel with the process of writing the read image data in the buffer memory, it is necessary to perform the process of reading the image data from the buffer memory and transferring it via the interface circuit.

That is, in the image scanner, it is not allowed to occupy the bus for writing to or reading from the buffer memory, so that a single transfer system DMA transfer is performed between the image reading unit and the interface circuit and the buffer memory. Need to do. However, conventional single transfer DMA
In the transfer, it was not possible to follow the reading speed of the image scanner because the transfer speed was slow.

[0010]

By the way, a single transfer system D realized by a conventional general-purpose DMA circuit is used.
The procedure for the MA transfer is determined so that the processor can operate effectively on the premise that the access to the memory by the input / output device is processed by interposing the processing between the processors as the bus masters. That is, as shown in FIG. 5, by shifting the timing of each procedure by one cycle of the clock signal CLK (see FIG. 5 (a)) of the processor, the time required for memory access and the clock signal CLK
The difference with the cycle of was adjusted.

Further, since it is usually assumed that the processor becomes a bus master and holds the right to use the bus, according to the DMA request DRQ from the input / output device (see FIG. 5B). It includes a procedure for exchanging the hold request HLDRQ and the hold response HLDAK (see FIGS. 5C and 5D) between the DMA circuit and the bus master to release the bus use right. In this way, after the bus usage right is released, the address enable AEN (see Fig. 5 (e))
By this, the addresses A _{0 to} A ₁₅ (see FIG. 5 (f)) by the DMA circuit are validated, and the DMA confirmation DMACK (see FIG. 5 (g)) is notified to the input / output device side. Access is started.

Therefore, as shown in FIGS. 5 (h) and 5 (i), the actual memory access time is 2 to 3 clocks in response to the read signal READ and the write signal WRITE. Despite this, due to the time required for arbitration processing of the bus usage right, there is a difference in timing between the reception of the DMA request and the start of access to the memory, and it takes 10 clocks to transfer 1 byte of data. Was needed.

On the other hand, in the image scanner, it is not necessary for either one of the image reading unit and the interface circuit to be the bus master. Therefore, the arbitration process for the bus use right like the conventional single transfer system is a redundant process. Is.

The present invention is a single transfer type D
An object of the present invention is to provide a DMA circuit that can process MA transfer at high speed.

[0015]

FIG. 1 is a block diagram showing the principle of the present invention. According to the present invention, in a direct memory access circuit for performing direct memory access transfer via a bus 103 connecting a plurality of processing means 101 and a memory 102, a cycle corresponding to a minimum time required to access the memory 102 is set. A clock generation unit 111 that generates a clock signal that the unit has and one of the access requests from the plurality of processing units 101 is made valid in synchronization with the clock signal, and the corresponding processing unit 101 is notified of the access request. An arbitration means 112 for giving the right to use the bus 103 for one cycle of the clock signal, and a synchronization signal which is synchronized with the clock signal and which generates a synchronization signal corresponding to each procedure of access to the memory 102 and sends it to the memory 102. And a signal generating means 113.

[0016]

According to the present invention, the arbitration means 112 arbitrates the access request in synchronization with the clock signal obtained by the clock generation means 111, and the arbitration means is validated according to the synchronization signal generated by the synchronization signal generation means 113. Each procedure for accessing the memory 102 by the access request is executed.

Here, one cycle of the clock signal described above corresponds to the minimum time required to access the memory 102. Therefore, if the access processing is started in synchronization with the start of one cycle of this clock signal, the DMA corresponding to the above-mentioned access request is completed at the end of this cycle.
The transfer process can be completed. Also, the arbitration means 11
2 gives the right to use the bus 103 to the valid access request only for one cycle of the clock signal, so that the DMA transfer process corresponding to the access request is completed,
The right to use the bus 103 is certainly released. Therefore, 1
The arbitration process of the right of use of the bus 103 is omitted for each DMA transfer, the deviation between the reception of the access request and the start of the access is removed, and the DMA is performed once for each cycle of the clock signal.
The transfer can be executed to speed up the DMA transfer process.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 shows the configuration of an embodiment of an image scanner to which the DMA circuit of the present invention is applied.

In FIG. 2, the image scanner has a structure in which an image reading unit 210, an interface circuit 220, a buffer memory 231, and a DMA circuit 240 are connected to each other via a bus 103 having a bus width of 1 byte. .. The buffer memory 231 corresponds to the memory 102 shown in FIG. 1, and may be formed using a dynamic RAM, for example.

The image reading section 210 includes a CCD sensor (CC
D) 211 reads the original, and the analog-digital converter (A / D) 212 converts the analog output of the CCD sensor 211 corresponding to each pixel on the original into 1-byte digital data. Further, the image reading unit 210 sends out a DMA request DREQ1 to the DMA circuit 240 every time the analog-digital converter 212 obtains a conversion result of 1 byte, and the DMA request DREQ1 is sent.
1-byte data is output to the bus 103 in response to a response from the circuit 240.

Further, the interface circuit 220 is configured to operate in accordance with the standard of the standard interface in order to send the image data obtained by the image reading section 210 to the external bus 201. This interface circuit 22
0 is a DMA request to the DMA circuit 240 when sending the data stored in the buffer memory 231 to the outside.
DREQ2 is transmitted, the data output to the bus 103 is read according to the response from the DMA circuit 240, and is output to the external bus 201.

Further, in FIG. 2, the refresh controller 232 periodically sends a DMA request DREQ3 to the DMA circuit 240 to request reading of data from each address of the buffer memory 231, and the buffer memory 231 is read. The memory holding operation of the dynamic RAM forming the H. 231 is controlled.

That is, the image reading section 210, the interface circuit 220, and the refresh control section 232 described above each function as the processing means 101 shown in FIG.

The detailed structure and operation of the DMA circuit 240 will be described below. FIG. 3 shows a detailed configuration diagram of an embodiment of the DMA circuit of the present invention. Where dynamic RA
Since the time required to access M is about 190 ns including the precharge time, it is possible to access the buffer memory 231 once every 200 ns.

For example, as shown in FIG.
1 and the frequency dividing circuit 242, the clock generating means 111.
, The oscillator circuit 241 generates a reference clock signal CLK0 having a frequency of 20 MHz, and the frequency divider circuit 242 divides the reference clock signal CLK0 by 4 to generate a frequency of 5 MHz (cycle 200 ns).
The access clock signal CLKA may be generated.

In this way, the access clock signal CLKA having a period of the minimum time required to access the memory 102 is generated, and the access clock signal CLKA is generated.
Should be sent to the arbitration means 112.

The arbitration means 112 includes three D-type flip-flops (hereinafter simply referred to as flip-flops) 2.
43a, 243b, 243c and the priority determination circuit 24
4, a latch circuit 245, and three NAND gates 246
a, 246b, 246c and an OR gate 247.

Three flip-flops 243a and 243
The clock terminals of b and 243c have the above-mentioned D
The MA requests DREQ1, DREQ2, DREQ3 are inputted respectively, and the logic "1" is outputted in response to the rising edges of these DMA requests DREQ1, DREQ2, DREQ3. In addition, these flip-flops 243a, 2
The outputs of 43b and 243c are input to the priority determination circuit 244, respectively, and are configured to notify the priority determination circuit 244 of DMA requests from the image reading unit 210, the interface circuit 220, and the refresh control unit 251. There is.

The priority determination circuit 244 has a preset priority of three DMA requests DREQ1, DREQ2, DREQ3, and detects the DMA request with the highest priority among the notified DMA requests. Has become. Also,
The priority determination circuit 244 uses the DMA requests DREQ1, DREQ2, D
It is configured to send a determination result indicating whether each is valid to REQ3 to the latch circuit 245.

The flip-flop 243 described above is also used.
The outputs of a, 243b, and 243c are input to the latch circuit 245 via the OR gate 247, and the latch circuit 245 determines the result of determination by the priority determination circuit 244 in response to the rising edge of the access clock signal CLKA described above. And a logical sum of these DMA requests DREQ1, DREQ2, DREQ3.

That is, the arbitration means 112 requests the DMA in response to the rising edge of the access clock signal CLKA.
Arbitration of DREQ1, DREQ2, and DREQ3 is performed, and the arbitration result is held in the latch circuit 245 only for one cycle of the access clock signal CLKA.

Further, the above-mentioned DMA requests DREQ1, DREQ2,
The arbitration result for DREQ3 is input to one of the input terminals of the corresponding NAND gates 246a, 246b, 246c, and the corresponding DMA requests DREQ1, DREQ2, DREQ2, DREQ2,
As a DMA response to DREQ3, the image reading unit 210,
Interface circuit 220, refresh controller 251
It is configured to be returned to each.

Thus, only while the latch circuit 245 holds the arbitration result, the DMA response is returned to the sender of the valid DMA request, indicating that the DMA request is valid. This means that the bus 1
This is equivalent to giving the use right of 03.

Further, these DMA responses correspond to the corresponding flip-flops 243a, 243b, 243c.
The DMA request is input to the clear terminal and the DMA request accepted by the DMA circuit 240 is cleared.

Further, in FIG. 3, the arbitration result held in the above-mentioned latch circuit 245 is input to the gate circuit 251, and the gate circuit 251 responds to the arbitration result by requesting the DMA requests DREQ1, DREQ2, Address counters 252a, 252b, 252 respectively corresponding to DREQ3
The configuration is such that one of the outputs c is selected and output to the bus 103.

These address counters 252a, 25
An initial value of the address is set in advance in each of 2b and 252c, and the gate circuit 251 is configured to select the output of the address counter 252 corresponding to the DMA request validated by the input arbitration result. ..

Further, the DM held in the latch circuit 245
The logical sum of A request DREQ1, DREQ2, DREQ3 is at least 1
A DMA detection signal indicating whether or not there is one DMA request is input to the synchronization signal generation means 113, and the synchronization signal generation means 113 operates according to the DMA detection signal.

In FIG. 3, the synchronization signal generating means 113
Are three D-type flip-flops (hereinafter simply referred to as flip-flops) 261a and 261 connected in series.
b, 261c, the DMA detection signal is input through the NAND gate 262, and these flip-flops 261a,
261b and 261c and NAND gates 263 and 264 are used to generate an address strobe signal AS, a row address strobe signal RAS, and a column address strobe signal CAS. These flip-flops 26
The above-described reference clock signal CLK0 is input to the clock terminals of 1a, 261b, and 261c, and it is configured to operate in synchronization with this reference clock signal CLK0.

The output and the inverted output of the first-stage flip-flop 261a are sent as an address strobe AS and a negative logic address strobe ASI, respectively. Further, the address strobe AS and the output of the second-stage flip-flop 261b are inverted and input to the NAND gate 263, and the output of the NAND gate 263 is as follows.
It is configured to obtain the negative logic row address strobe RAS. In addition, three flip-flops 261a and 261
The inverted output of each of b and 261c is the NAND gate 26.
4 and the negative logic column address strobe CAS is obtained as the output of the NAND gate 264.

The above-mentioned row address strobe RAS is input to another D-type flip-flop 265, and this D-type flip-flop 265 operates in synchronization with the reference clock signal CLK0 input via the inverter 266. As a result, the switching signal R / C indicating the switching timing between the row address and the column address is generated. In addition, the column address strobe CAS is inverted and then, via the buffer 267, the NAND gate 26 described above.
2 is inverted and input, and after the column address becomes valid, one address period of the reference clock signal CLK0 elapses, and then all address strobe signals are made invalid.

That is, the synchronization signal generating means 113 is D
While the MA detection signal is logic "1", an address strobe AS, a row address strobe RAS, and a column address strobe CAS are generated as a synchronization signal corresponding to the access procedure at each rising of the reference clock signal CLK0. It is composed.

FIG. 4 is a timing chart showing the operation of the DMA circuit of the present invention. 4 (a) and 4 (b) respectively show the reference clock signal CLK0 and the access clock signal CLKA generated by the clock generation means 111 described above, and FIG.
(d) and (e) show DMA requests DREQ1, DREQ2, and DREQ3.

For example, at the time point indicated by arrow A in FIG. 4, since only the DMA request DREQ1 is output, DM is synchronized with the rising edge of the access clock signal CLKA.
The A request DREQ1 is held in the latch circuit 245. In response to this, the gate circuit 251a of the address control unit 250 is opened, and the address calculated by the address counter 252a is output to the bus 103.

At this time, since the latch circuit 245 also holds the output of the OR gate 247, the DMA detection signal becomes a logic "1" as shown in FIG. 4 (f), and the synchronization signal is generated accordingly. The means 113 starts the operation of generating the synchronization signal.

First, an address strobe ASI (see FIG. 4 (g)) is generated with a delay of one cycle of the reference clock signal CLK0 from the rising edge of the DMA detection signal, and an image is generated according to the DMA response synchronized with this address strobe ASI. 1 obtained by the analog-digital converter 212 of the reading unit 210
The byte data is output to the bus 103.

Then, by the synchronization signal generating means 113,
Row address strobe RAS, Column address strobe CAS
Is generated (see FIGS. 4 (h) and 4 (i)), and in synchronization with the row address strobe RAS and the column address strobe CAS, the address output to the bus 103 is divided into a row address and a column address and buffered. The data set in the memory 231 and output to the bus 103 is written.

Since one cycle of the access clock signal CLKA corresponds to four cycles of the reference clock signal CLK0, one cycle of the above-described synchronizing signal generating operation is one cycle of the access clock signal CLKA. That is, the processing is completed in the access time to the dynamic RAM. Also, DMA
The rising edge of the detection signal is synchronized with the rising edge of the access clock signal CLKA, and since the access clock signal CLKA and the reference clock signal CLK0 are synchronized,
By executing each access procedure according to the above-mentioned synchronization signal, the access to the buffer memory 231 including precharge can be completed within one cycle from the rise of the access clock signal CLKA.

Further, since the latch circuit 245 holds the new arbitration result in synchronization with the next rising edge of the access clock signal CLKA, the corresponding D depending on the previous arbitration result.
The right to use the bus 103 given to the MA request is necessarily released at the end of that cycle of the access clock signal CLKA, and is passed to the DMA request indicated by the new arbitration result.

As a result, the arbitration processing of the bus 103 can be omitted, so that the next access clock signal CLKA
It becomes possible to start another DMA transfer process by receiving another DMA request in synchronization with the rising edge of the DM.
It is possible to remove the timing lag between the reception of the A request and the start of access to the memory 102.

For example, as shown in FIG. 4, at the next rise of the access clock signal CLKA, the DMA request DREQ2
Also, the DMA request DREQ3 is detected, and, for example, the DMA request DREQ3 is detected according to the priority set in the priority determination circuit 244.
The latch circuit 245 determines that the request DREQ2 is a valid DMA request.
Held in. In response to this, the DMA transfer process corresponding to the DMA request DREQ2 is started, and corresponding data is read from the buffer memory 231 according to the address from the address counter 252b corresponding to the DMA request DREQ2, and is transferred via the bus 103. Are transferred to the interface circuit 220. Similarly, in the next cycle of the access clock signal CLKA, the DMA corresponding to the DMA request DREQ3
Transfer processing is performed.

As described above, the cycle of the access clock signal CLKA is determined based on the access time to the dynamic RAM, the DMA request is arbitrated at each rising edge of the access clock signal CLKA, and the buffer memory 231 is arbitrated.
By starting the access processing to the DMA request, the DMA requests DREQ1, DR are made for each cycle of the access clock signal CLKA.
It is possible to perform the DMA transfer of each channel corresponding to EQ2 and DREQ3.

As a result, in the image scanner shown in FIG. 2, the DMA circuit 240 includes the image reading unit 210,
Interface circuit 220, refresh controller 232
Since the DMA request from the can be processed every 200 ns, the DM of the single transfer system by the conventional DMA circuit is used.
It is possible to increase the speed by about 5 times as compared with the A transfer, and can sufficiently cope with the reading speed of the image scanner.

Further, since the above-mentioned DMA circuit 240 arbitrates the DMA request in synchronization with the rising edge of the access clock signal CLKA, the image reading section 210, the interface circuit 220, and the refresh control section 232 need to access the access clock signal. CLKA or reference clock signal CLK0
DMA requests DREQ1, DREQ2, DREQ3 can be sent asynchronously with. Also, at the same time as the above arbitration result,
If the data of each channel is latched, the time required for access processing will not be extended.

As described above, the time required for the DMA transfer processing by the DMA circuit of the present invention is limited by the time required for accessing the memory element used as the memory 102. Therefore, instead of the dynamic RAM, a static RAM that enables faster access
If the buffer memory 231 is formed by using
Higher-speed DMA transfer can be realized by the A circuit 240.

In addition, the DMA circuit of the present invention can perform one D
Since the time required for MA transfer processing is always constant, it is possible to accurately evaluate the transfer speed. In addition, RISC (Reduce Instruction Set Computer) processors and DSP (Didital Signal Proccessor) instructions Can also be applied to a processor that executes in one clock.

[0056]

As described above, according to the present invention, the cycle of the clock signal which is the synchronizing signal is set according to the time required for accessing the memory, and the cycle of the clock signal is set for each cycle.
By completing the DMA transfer processing corresponding to one DMA request and freeing the bus, the memory access start and the D
It is possible to reduce the timing shift from the reception of the MA request and the redundant time required for the arbitration processing of the bus use right, and to process the single transfer DMA transfer at high speed.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of an image scanner to which the DMA circuit of the present invention is applied.

FIG. 3 is a detailed configuration diagram of a DMA circuit of the present invention.

FIG. 4 is a timing diagram showing the operation of the DMA circuit of the present invention.

FIG. 5 is a timing chart showing the operation of a conventional single transfer system.

[Explanation of symbols]

 101 processing means 102 memory 103 bus 111 clock generation means 112 arbitration means 113 synchronization signal generation means 201 external bus 210 image reading section 211 CCD sensor (CCD) 212 analog-digital converter (A / D) 220 interface circuit 231 buffer memory 232 Refresh control unit 240 DMA circuit 241 Oscillation circuit 242 Dividing circuit 243, 261, 265 D-type flip-flop 244 Priority determination circuit 245 Latch circuit 246, 262, 263, 264 NAND gate 247 OR gate 251 Gate circuit 252 Address counter 266 Inverter 267 buffer

Claims (1)

[Claims] 1. A plurality of processing means (101) and a memory (1)
02) in a direct memory access circuit for direct memory access transfer via a bus (103) connected to the clock signal (02) to generate a clock signal having a cycle corresponding to the minimum time required to access the memory (102). Clock generating means (111) for controlling the plurality of processing means (1) in synchronization with the clock signal.
01) Validate any of the access requests from
Notifying the corresponding processing means (101), the access request is made to the bus (10) for one cycle of the clock signal.
3) an arbitration means (112) for giving the right to use, and a synchronizing signal corresponding to each procedure of access to the memory (102) in synchronization with the clock signal,
Synchronous signal generation means (1 for sending to the memory (102)
13) A direct memory access circuit comprising: