JPH0581132A - Access circuit for address conversion buffer - Google Patents

Abstract

PURPOSE:To execute an operation for enhancing a hit rate when a program with the unsatisfactory hit rate in an address conversion buffer is running. CONSTITUTION:An address conversion buffer 2 storing logical address conversion tag data 22, physical address conversion data 23 and a valid bit 21, a means obtaining access information of the address conversion buffer 2 from logical address information via a hash circuit 3, a coincidence detecting circuit 5 detecting that physical address conversion data 23 being valid for the address conversion buffer 2 is stored by logical address information, logical address conversion tag data 22 and the valid bit 21 and a non-coincidence time monitoring circuit 7 monitoring the time of register data non-coincidence in the address conversion buffer 2 as against the reference time of the address conversion buffer 2 are provided in an access circuit which is characterized by resetting the valid bit 21 and changing the hash system of the hash time when the fixed time of register data non-coincidence is detected within the fixed reference time of the address conversion buffer 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation buffer access circuit. Address translation buffer (hereinafter T
LB) is widely known as a device that translates a logical address into a physical address associated with a main memory access.

[0002]

2. Description of the Related Art A conventional TLB access circuit is a TLB.
Even if there is a high probability that the registered data will not match,
The access information of TLB was not changed.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the access circuit, since the access information of the TLB memory is fixed, even if a program having a poor TLB hit rate runs, there is no means for increasing the hit rate, so that the multiprocessing capability cannot be improved. There is.

[0004]

A TLB access circuit according to the present invention comprises a TLB memory consisting of TAG information, translated address information and a valid bit, a hash circuit for obtaining access information of the TLB memory, logical address information and TAG information. And a match detection circuit for detecting that valid translation address information is stored in the TLB from the valid bit, and the TLB.
A mismatch count monitoring circuit that monitors the number of times of TLB memory data mismatch with respect to the memory reference count, a register that stores a specified count value of TLB memory reference that is updated by a microprogram, and a microprogram that updates the TLB memory reference
LB memory Register for storing valid data for register data mismatch detection and register for storing specified value of TLB memory registration data mismatch detection in order to instruct change of hash formula for creating access address of TLB memory, and TLB memory updated by microprogram It has a register that stores a code value that specifies the hash method for creating the access address.

[0005]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The register 1 stores logical address information or physical address information at the time of access to the main memory, and the TLB 2
Stores V bit 21 indicating that the information registered in TLB 2 is valid, physical address conversion data 23 from the logical address, and logical address conversion tag data 22.

The hash circuit 3 generates address information for indexing the TLB 2, and the switching circuit 4 selects a register if the address information for main memory access is a physical address, and for main memory access. If the address information is a logical address, the physical address conversion data 23 of the TLB 2 is selected.

When the address information of the main memory address is a logical address, the match detection circuit 5 detects whether the information registered in the TLB 2 is the converted physical address information.

The register 6 stores physical address information that is actually sent to a main storage device (not shown) when the main storage is accessed.

The disagreement count monitoring circuit 7 includes a coincidence detection circuit 5.
In the main memory access for monitoring the output of TLB2 and referring to TLB2, when the number of times the registered data in TLB2 is not valid (hereinafter referred to as TLB no hit) at the time of referring to TLB2 m times, hashing to hash circuit 3 is performed. A method change instruction and a V bit 21 reset instruction are given.

The register 8 is used by the mismatch count monitoring circuit 7 for T
The specified number of times when referring to LB2 is stored, and the value is set by the firmware.

The register 9 is the TL specified by the register 8.
A specified detection count value indicating how many TLB no-hit counts are detected within the reference count of B2 is stored, and the value is set by the firmware.

The register 10 is a TLB in the hash circuit 3.
A code value designating a hash method for creating address information for accessing 2 is stored.

Registers 8, 9 and 10
Is not necessarily required for the present invention, and if it does not exist, it operates as a fixed value by recognizing that the mismatch count monitoring circuit 7 and the hash circuit 3 have obtained the necessary value.

Now, the operation when the value of 100 is set in the register 8 and the value of 30 is set in the register 9 will be described.

In such a setting, when the main memory access referring to TLB2 is executed 100 times and the number of TLB no hits is detected 30 times or more, V bit 21
Is reset and the hash method change instruction is given to the hash circuit 3 by the mismatch count monitoring circuit 7.

If the number of TLB no-hit detections is 29 or less while the number of TLB2 referenced main memory accesses is 100 or more, the number of TLB2 referenced main memory accesses counted in the mismatch count monitoring circuit 7 is , TL
Re-measure the number of B-no-hit detections from the beginning.

[0019]

As described above, according to the present invention, when the number of TLB no-hits is detected n times during the TLB reference time of m times in the main memory access referring to the TLB, the TL is detected.
By determining that the hash method for creating the address information for B registration / reference is not appropriate and correcting the hash method, there is an effect of increasing the probability of a TLB hit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1, 6, 8, 9, 10 register 2 address conversion buffer (TLB) 3 hash circuit 4 switching circuit 5 mismatch detection circuit 7 mismatch count monitoring circuit

Claims (5)

[Claims] 1. An address translation buffer for storing logical address translation tag data, physical address translation data, and a valid bit; means for obtaining access information of the address translation buffer from a logical address information via a hash circuit; and the logical address. A coincidence detection circuit for detecting that information, the logical address translation tag data and the valid bit store valid physical address translation data in the address translation buffer, and registration of the address translation buffer with respect to the reference count of the address translation buffer. A mismatch count monitoring circuit for monitoring the number of data mismatches, and when the registered data mismatch is detected a fixed number of times within the reference count of the address translation buffer, a reset of the valid bit and the hash You can change the hashing method Access circuitry of the address translation buffer according to claim. 2. The address translation buffer access circuit according to claim 1, further comprising a register which stores a prescribed number of times of access to the main memory referenced by the address translation buffer and updated by a microprogram. 3. A specified value for detection of address translation buffer registration data inconsistency detection in order to perform a valid bit reset by a microprogram update by address translation buffer registration data inconsistency detection and a hash method change instruction for creating an access address of the address translation buffer. The address translation buffer access circuit according to claim 1, further comprising a register for storing 4. The address translation buffer access circuit according to claim 1, further comprising a register which stores a code value which is updated by a microprogram and specifies a hash method for creating an access address of the address translation buffer. . 5. A main memory access count for address translation buffer reference and address translation buffer registration data when the number of address translation buffer registration data disagreements exceeds a specified number within a prescribed number of main memory access for address translation buffer reference. 2. The address translation buffer access circuit according to claim 1, further comprising a mismatch count monitoring circuit for restarting the measurement of the mismatch count from the beginning.