JPH0581048B2 - - Google Patents
Info
- Publication number
- JPH0581048B2 JPH0581048B2 JP61155978A JP15597886A JPH0581048B2 JP H0581048 B2 JPH0581048 B2 JP H0581048B2 JP 61155978 A JP61155978 A JP 61155978A JP 15597886 A JP15597886 A JP 15597886A JP H0581048 B2 JPH0581048 B2 JP H0581048B2
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- electrode
- forming
- group compound
- ohmic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 239000004065 semiconductor Substances 0.000 claims description 38
- 150000001875 compounds Chemical class 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 18
- 239000007772 electrode material Substances 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000005275 alloying Methods 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004943 liquid phase epitaxy Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- XSTXAVWGXDQKEL-UHFFFAOYSA-N Trichloroethylene Chemical group ClC=C(Cl)Cl XSTXAVWGXDQKEL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
〔概要〕
本発明は、オーミツク電極の形成方法に於い
て、−Ｖ族化合物半導体上に直接接触するSb
のみの第一の電極材料膜及びAuを含む第二の電
極材料膜を順に形成し、これを熱処理して前記
−Ｖ族化合物半導体の表面に禁制体幅が小さい化
合物半導体の合金化領域を生成させてオーミツク
電極を形成することに依り、順逆対称の直線的な
電圧対電流特性を有する良好なオーミツク・コン
タクトが得られるようにした。Detailed Description of the Invention [Summary] The present invention provides a method for forming an ohmic electrode in which Sb is directly contacted on a -V group compound semiconductor.
A first electrode material film containing Au and a second electrode material film containing Au are sequentially formed, and these are heat-treated to form an alloyed region of a compound semiconductor with a small forbidden width on the surface of the -V group compound semiconductor. By forming an ohmic electrode in this manner, a good ohmic contact having linear voltage versus current characteristics with forward and reverse symmetry can be obtained.
本発明は、Alを含有した−Ｖ族化合物半導
体にオーミツク電極を形成するのに好適な方法に
関する。
The present invention relates to a method suitable for forming an ohmic electrode on a -V group compound semiconductor containing Al.
一般に、化合物半導体装置に用いる材料として
は族及びＶ族に属する物質からなる、所謂、
−Ｖ族化合物半導体が重用され、そして、化合物
半導体を用いても、半導体装置であるからには、
オーミツク電極を設けることが必須である。
In general, materials used in compound semiconductor devices include substances belonging to Groups and V Groups, so-called
-V group compound semiconductors are heavily used, and even if compound semiconductors are used, since it is a semiconductor device,
It is essential to provide an ohmic electrode.
従来、−Ｖ族化合物半導体に対するオーミツ
ク電極としては、該化合物半導体がｎ型である場
合、In、InSn、AuSn、AuGe、AuGeNiなどの
電極金属を、また、該化合物半導体がｐ型である
場合、In、InZn、AuZnなどの電極金属或いは
Au／Zu／Au多層膜、Ti／Pt／Au多層膜などを
蒸着法或いはスパツタリング法を適用して被着
し、その後、熱処理に依る合金化を行つて完成し
ている。 Conventionally, as ohmic electrodes for −V group compound semiconductors, electrode metals such as In, InSn, AuSn, AuGe, AuGeNi, etc. are used when the compound semiconductor is n-type, and when the compound semiconductor is p-type, Electrode metal such as In, InZn, AuZn or
Au/Zu/Au multilayer films, Ti/Pt/Au multilayer films, etc. are deposited by vapor deposition or sputtering, and then alloyed by heat treatment to complete the process.
第４図乃至第５図は従来のオーミツク電極を形
成する方法を説明する為の工程要所に於ける
GaAs系化合物半導体装置の要部切断側面図を表
し、以下、これ等の図を参照しつつ説明する。 Figures 4 and 5 show key points in the process to explain the conventional method of forming ohmic electrodes.
1 shows a cutaway side view of a main part of a GaAs-based compound semiconductor device, and will be described below with reference to these figures.
第４図参照
(1) 面指数が（100）であるGaAs基板１に液相
成長（liquid phase epitaxy：LPE）法を適用
することに依り、アン・ドープｎ型GaAs層２
を成長させる。See Figure 4 (1) By applying liquid phase epitaxy (LPE) to a GaAs substrate 1 with a plane index of (100), an undoped n-type GaAs layer 2 is formed.
grow.
この場合に於ける主要データを例示すると次
の通りである。 Examples of main data in this case are as follows.
GaAs層２の厚さ：１〔μm〕
不純物濃度：１×1016〔cm-3〕
第５図参照
(2) 直径が500〔μm〕の円形孔が１〔mm〕間隔で形
成されているMoのマスクを用い、蒸着法或い
はスパツタリング法を適用することに依り、
GaAs層２上にAuSnからなる電極３を形成す
る。尚、この場合における電極３の厚さとして
は、約2000〜3000〔Å〕程度の範囲で選択する。
尚、電極３の材料としては、前記AuSnに限定
されることなく、前掲の各種材料を適宜に選択
することができる。また、前記Moなど金属の
マスクと蒸着法などを用いて電極３を形成する
技術の外、電極材料膜をフオト・リソグラフイ
技術にてパターニングして所望形状の電極３を
得ることもできる。Thickness of GaAs layer 2: 1 [μm] Impurity concentration: 1×10 16 [cm -3 ] See Figure 5 (2) Circular holes with a diameter of 500 [μm] are formed at intervals of 1 [mm]. By using a Mo mask and applying the vapor deposition method or sputtering method,
An electrode 3 made of AuSn is formed on the GaAs layer 2. Note that the thickness of the electrode 3 in this case is selected within a range of about 2000 to 3000 [Å].
Note that the material for the electrode 3 is not limited to the above-mentioned AuSn, and any of the various materials listed above can be selected as appropriate. In addition to the technique of forming the electrode 3 using a metal mask such as Mo and vapor deposition, it is also possible to obtain the electrode 3 in a desired shape by patterning the electrode material film by photolithography.
第６図参照
(3) 窒素雰囲気中にて、温度を約400〜500〔℃〕
程度、時間を３〜５〔分〕程度として熱処理を
行う。See Figure 6 (3) In a nitrogen atmosphere, reduce the temperature to approximately 400 to 500 [℃].
The heat treatment is performed for about 3 to 5 minutes.
これに依り、GaAs層２とAuSn電極３のそ
れぞれの一部が合金化され、合金化領域４が生
成される。尚、この合金化領域４の深さは約
100〜200〔Å〕程度である。 As a result, a portion of each of the GaAs layer 2 and the AuSn electrode 3 is alloyed, and an alloyed region 4 is generated. The depth of this alloyed region 4 is approximately
It is about 100 to 200 [Å].
ところで、−Ｖ族化合物半導体がGaAs、
InGaAs、InP、InGaAsPである場合は、前記方
法でオーミツク電極を形成することができる。然
しながら、−Ｖ族化合物半導体がInP基板上に
成長されたAlInAsなどAlを多量に含有するもの
である場合に於いて、前記従来の方法で電極を作
成した試料を測定してみると、その電圧（Ｖ）−
電流（Ｉ）特性が直線的にはならず、所謂、ダイ
オード特性を呈する。これは、AuSnの代わりに
AuGeを用いても同様であつた。 By the way, the −V group compound semiconductor is GaAs,
In the case of InGaAs, InP, or InGaAsP, an ohmic electrode can be formed by the method described above. However, when the -V group compound semiconductor contains a large amount of Al, such as AlInAs grown on an InP substrate, when measuring a sample with electrodes made using the above-mentioned conventional method, the voltage (V)-
The current (I) characteristics are not linear and exhibit so-called diode characteristics. This instead of AuSn
The same result was obtained when AuGe was used.
前記説明したように、−Ｖ族化合物半導体に
オーミツク電極を形成する場合、その化合物半導
体がAlを含有していると良好なオーミツク特性
を得ることができず、Alの含有量が多い、例え
ば、AlGaAs或いはAlInAsなどに電極を形成し
てオーミツク・コンタクトを得ようとしてもダイ
オードのような整流特性を示すようになる。
As explained above, when forming an ohmic electrode on a -V group compound semiconductor, if the compound semiconductor contains Al, good ohmic characteristics cannot be obtained, and if the compound semiconductor contains Al, it is difficult to obtain good ohmic characteristics. Even if an attempt is made to obtain an ohmic contact by forming electrodes on AlGaAs or AlInAs, the electrodes will exhibit rectifying characteristics similar to those of a diode.
本発明は、オーミツク電極を構成する材料を適
正に選択することで、−Ｖ族化合物半導体に対
して良好なオーミツク特性が得られるようにする
ものである。 The present invention is intended to provide good ohmic characteristics for -V group compound semiconductors by appropriately selecting the material constituting the ohmic electrode.
本発明に依るオーミツク電極の形成方法に依れ
ば、−Ｖ族化合物半導体（例えばアン・ドープ
ｎ型AlInAs層１２）上にSbのみからなる第一の
電極材料膜及びAuを含む第二の電極材料膜（例
えばAuSn膜或いはAuGe膜など）を順に形成す
る工程と、次いで、合金化の為の熱処理を行なつ
てオーミツク電極（例えばオーミツク電極１３）
を形成する工程とが含まれてなることを特徴とす
る構成になつている。
According to the method for forming an ohmic electrode according to the present invention, a first electrode material film consisting only of Sb and a second electrode containing Au are formed on a -V group compound semiconductor (for example, an undoped n-type AlInAs layer 12). A process of sequentially forming a material film (for example, an AuSn film or an AuGe film) and then a heat treatment for alloying are performed to form an ohmic electrode (for example, an ohmic electrode 13).
The structure is characterized in that it includes a step of forming.
前記手段を採つた場合、−Ｖ族化合物半導体
とSbとが反応し、界面には合金化領域として禁
制帯幅が小さい化合物半導体が生成され、−Ｖ
族化合物半導体と電極金属との間のエネルギ障壁
を小さくすることができ、従つて、ダイオード特
性は生成され難くなり、順逆対称の直線からなる
Ｖ−Ｉ特性を持つ良好なオーミツク電極が得られ
る。
When the above method is adopted, the -V group compound semiconductor and Sb react, and a compound semiconductor with a small forbidden band width is generated as an alloying region at the interface, and -V
The energy barrier between the group compound semiconductor and the electrode metal can be reduced, and therefore diode characteristics are less likely to be generated, and a good ohmic electrode with VI characteristics consisting of straight lines with forward and reverse symmetry can be obtained.
第１図乃至第３図は本発明一実施例を説明する
為の工程要所に於ける化合物半導体装置の要部切
断側面図を表し、以下、これ等の図を参照しつつ
説明する。
1 to 3 are cross-sectional side views of essential parts of a compound semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures.
第１図参照
(1) 面指数が（111）ＡであるInP基板１１に
LPE法を適用することに依り、該InP基板１１
と格子整合させてアン・ドープｎ型AlInAs層
１２を成長を行う。Refer to Figure 1 (1) On the InP substrate 11 whose plane index is (111)A.
By applying the LPE method, the InP substrate 11
An undoped n-type AlInAs layer 12 is grown with lattice matching.
この場合に於ける主要データを例示すると次
の通りである。 Examples of main data in this case are as follows.
AlInAs層１２の厚さ：〜0.5〔μm〕
不純物濃度：１×1014〜１×1015〔cm-3〕
ここでの不純物濃度は、本発明に依つてオー
ミツク電極を形成した後、ホール測定に依つて
得たものである。Thickness of AlInAs layer 12: ~0.5 [μm] Impurity concentration: 1 x 10 14 - 1 x 10 15 [cm -3 ] The impurity concentration here is determined by hole measurement after forming an ohmic electrode according to the present invention. This was obtained based on the following.
第２図参照
(2) AlInAs層１２を成長させたInP基板１１をト
リクロルエチレン、アセトン、メタノールなど
で洗浄する。See Figure 2 (2) The InP substrate 11 on which the AlInAs layer 12 has been grown is cleaned with trichlorethylene, acetone, methanol, or the like.
(3) 直径が500〔μm〕の円形孔を１〔mm〕間隔で形
成してあるMoのマスクでAlInAs層１２の表面
を覆い、蒸着法或いはスパツタリング法を適用
することに依り、純度6N（99.9999〔％〕）のSb
を〜1000〔Å〕程度の厚さに形成してから、引
き続き、AuSnを2000〔Å〕程度に形成する。(3) By covering the surface of the AlInAs layer 12 with a Mo mask in which circular holes with a diameter of 500 [μm] are formed at 1 [mm] intervals, and applying a vapor deposition method or a sputtering method, a purity of 6N ( 99.9999 [%]) Sb
is formed to a thickness of about 1000 [Å], and then AuSn is formed to a thickness of about 2000 [Å].
これに依り、AlInAs層１２上には、円形パ
ターンを有するSb・AuSnからなる電極１３が
形成される。 As a result, an electrode 13 made of Sb/AuSn and having a circular pattern is formed on the AlInAs layer 12.
第３図参照
(4) 窒素雰囲気中にて、温度450〔℃〕、時間を３
〔分〕の熱処理を行う。See Figure 3 (4) In a nitrogen atmosphere at a temperature of 450 [℃] for 3 hours.
Perform heat treatment for [minutes].
これに依り、合金化領域１４が形成される
が、この合金化領域１４は、SbがAlInAsと反
応して生成された混晶系化合物半導体が構成さ
れ、これに電極金属が合金化された状態になつ
ていて、AuSnを直接被着した場合のように整
流性を示すことは皆無である。 As a result, an alloyed region 14 is formed, and this alloyed region 14 is composed of a mixed crystal compound semiconductor produced by reacting Sb with AlInAs, and an electrode metal is alloyed with this. However, it does not exhibit any rectifying properties as it does when AuSn is directly deposited.
このようにして作成された試料を測定したとこ
ろ、Ｖ−Ｉ特性は順逆対称の直線となり、良好な
オーミツク・コンタクト特性を示した。 When the sample prepared in this way was measured, the VI characteristic was a straight line with forward and reverse symmetry, indicating good ohmic contact characteristics.
ところで、Sbのみからなる電極材料膜とAuを
含む電極材料膜を別体にせず、Auを含む電極材
料膜にSbを混在させることも可能であるが、そ
の場合、本発明のようにSbのみからなる電極材
料膜を−Ｖ族化合物半導体に直接接触させる構
成と比較すると、−Ｖ族化合物半導体のエネル
ギ・バンド・ギヤツプを狭めて、エネルギ障壁を
小さくする旨の作用が減殺されることは云うまで
もない。 By the way, it is possible to mix Sb in the electrode material film containing Au without separating the electrode material film consisting only of Sb and the electrode material film containing Au, but in that case, as in the present invention, only Sb is mixed. Compared to a configuration in which an electrode material film made of 3-V compound semiconductor is brought into direct contact with the -V group compound semiconductor, the effect of narrowing the energy band gap and reducing the energy barrier of the -V group compound semiconductor is diminished. Not even.
また、Auが−Ｖ族化合物半導体中に侵入し
ないように、所謂、バリヤ・メタル膜を用いる、
例えばTi／Pt／Auなどからなる多層膜を使用す
る場合には、SbはAuと同様に阻止されてしまう
ので、前記した作用、即ち、エネルギ障壁を小さ
くする為の合金化領域を生成させることは不可能
である。 In addition, to prevent Au from entering the -V group compound semiconductor, a so-called barrier metal film is used.
For example, when using a multilayer film consisting of Ti/Pt/Au, etc., Sb is blocked in the same way as Au, so the above-mentioned effect, that is, the formation of alloyed regions to reduce the energy barrier. is impossible.
本発明に依るオーミツク電極の形成方法では、
−Ｖ族化合物半導体上に直接接触するSbのみ
の第一の電極材料膜及びAuを含む第二の電極材
料膜を順に形成し、これを熱処理して前記−Ｖ
族化合物半導体の表面に禁制体幅が小さい化合物
半導体の合金化領域を生成させてオーミツク電極
を形成するようにしている。
In the method for forming an ohmic electrode according to the present invention,
A first electrode material film containing only Sb and a second electrode material film containing Au are sequentially formed in direct contact on the -V group compound semiconductor, and these are heat-treated to form the -V group compound semiconductor.
An ohmic electrode is formed by forming an alloyed region of a compound semiconductor having a small forbidden width on the surface of a group compound semiconductor.
このような構成を採つた場合、−Ｖ族化合物
半導体とSbとが反応し、界面には合金化領域と
して禁制帯幅が小さい化合物半導体が生成され、
−Ｖ族化合物半導体と電極金属との間のエネル
ギ障壁を小さくすることができ、従つて、ダイオ
ード特性は生成され難くなり、順逆対称の直線か
らなるＶ−Ｉ特性を持つ良好なオーミツク電極が
得られる。 When such a configuration is adopted, the -V group compound semiconductor and Sb react, and a compound semiconductor with a small forbidden band width is generated as an alloyed region at the interface.
- The energy barrier between the V group compound semiconductor and the electrode metal can be reduced, and therefore diode characteristics are less likely to be generated, resulting in a good ohmic electrode with VI characteristics consisting of straight lines with forward and reverse symmetry. It will be done.
第１図乃至第３図は本発明一実施例を説明する
為の工程要所に於ける化合物半導体装置の要部切
断側面図、第４図乃至第６図は従来例を説明する
為の工程要所に於ける化合物半導体装置の要部切
断側面図をそれぞれ表している。
図に於いて、１１はInP基板、１２はアン・ド
ープｎ型AlInAs層１２，１３は電極、１４は合
金化領域をそれぞれ示している。
1 to 3 are cross-sectional side views of essential parts of a compound semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIGS. 4 to 6 are process steps for explaining a conventional example. 2A and 2B each represent a cutaway side view of a main part of a compound semiconductor device at important points. In the figure, 11 is an InP substrate, 12 is an undoped n-type AlInAs layer 12, 13 is an electrode, and 14 is an alloyed region.
Claims (1)
第一の電極材料膜及びAuを含む第二の電極材料
膜を順に形成する工程と、 次いで、合金化の為の熱処理を行なつてオーミ
ツク電極を形成する工程と が含まれてなることを特徴とするオーミツク電極
の形成方法。[Claims] 1-A step of sequentially forming a first electrode material film made only of Sb and a second electrode material film containing Au on a V group compound semiconductor, and then heat treatment for alloying. 1. A method for forming an ohmic electrode, the method comprising the step of forming an ohmic electrode by forming an ohmic electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15597886A JPS6313327A (en) | 1986-07-04 | 1986-07-04 | Formation of ohmic electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15597886A JPS6313327A (en) | 1986-07-04 | 1986-07-04 | Formation of ohmic electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6313327A JPS6313327A (en) | 1988-01-20 |
| JPH0581048B2 true JPH0581048B2 (en) | 1993-11-11 |
Family
ID=15617683
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15597886A Granted JPS6313327A (en) | 1986-07-04 | 1986-07-04 | Formation of ohmic electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6313327A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5317863A (en) * | 1976-08-02 | 1978-02-18 | Hitachi Ltd | Coupling means |
| JPS53116776A (en) * | 1977-03-22 | 1978-10-12 | Ito Kiyuuji | Ohmic electrode for iiiiv group compound semiconductor |
| JPS5723222A (en) * | 1980-07-17 | 1982-02-06 | Matsushita Electric Ind Co Ltd | Formation of semiconductor element electrode |
-
1986
- 1986-07-04 JP JP15597886A patent/JPS6313327A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5317863A (en) * | 1976-08-02 | 1978-02-18 | Hitachi Ltd | Coupling means |
| JPS53116776A (en) * | 1977-03-22 | 1978-10-12 | Ito Kiyuuji | Ohmic electrode for iiiiv group compound semiconductor |
| JPS5723222A (en) * | 1980-07-17 | 1982-02-06 | Matsushita Electric Ind Co Ltd | Formation of semiconductor element electrode |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6313327A (en) | 1988-01-20 |
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