JPH0580984A - Multiplication device - Google Patents

Abstract

PURPOSE:To provide an inexpensive multiplication device which can perform the multiplication of bits of higher orders at a high speed. CONSTITUTION:A DSP 1 inputs the higher order bit X1 and the lower order bit X0 of the length measurement data from a memory X and also inputs the higher order bit Y1 and the lower order bit Y0 of the coefficient data from a memory Y respectively. Then the DSP 1 adds 24 bits of higher orders of (X0XY0) to (X1XY0+X0XY1) and latches 24 bits of higher order of this addition through a 1st latch circuit R1. A DSP 2 adds (X1XY1) to 24 bits of higher orders of (X0XY0+X1XY0+X0XY1) latched by the circuit R1. Then the DSP 2 latches the result of addition by a higher order bit R21 and a lower order bit R20 of a 2nd latch circuit R2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for multiplying digital values having a large number of bits at high speed.

[0002]

2. Description of the Related Art For example, in the case of realizing a device for multiplying digital values of 33 bits or more, conventionally, a digital value is divided into upper bits and lower bits, and lower bits, upper bits and lower bits, and upper bits. It is possible to carry out each multiplication of two by using four existing 32-bit multipliers and realize the value (product) obtained by each multiplication by using three 32-bit adders.

It is also possible to obtain a multiplier of 33 bits or more by customizing it as an IC (ASIC).

[0004]

However, the 33-bit multiplier is expensive, and the use of four multipliers increases the cost and complicates the circuit.
In addition, the method using ASIC requires tens of millions of yen or more for development, and is not suitable for product design of a wide variety of products.

The present invention has been made in view of the above-mentioned conventional circumstances. A low-cost circuit configuration using a plurality of digital signal processors having a high-speed product-sum operation function allows high-bit digital values to be multiplied at high speed. The purpose is to provide a multiplier that can be executed.

[0006]

Therefore, in the multiplication device according to the present invention, a set of digital signal processors, a set of latch circuits, and two digital values are divided into upper bits and lower bits, respectively, and stored. A digital signal processor for multiplying the lower bits of the two digital values with each other, and selecting only the upper bit of the obtained value; and two digital signals. The second multiplication means for multiplying the high-order bit and the low-order bit of the value, the first addition means for adding the respective values multiplied by the first multiplication means and the second multiplication means, and the addition result A first latch means for selecting the upper bit of the obtained value and latching it in the first latch circuit, and the other digital signal processor is connected to the upper bit of the two data. A third multiplying means for performing the first
Second addition means for adding the value latched in the latch circuit of the third multiplication means and the value multiplied by the third multiplication means, and the value added by the second addition means is divided into upper bits and lower bits. And a second latching means for latching in a second latch circuit.

[0007]

Operation: One digital signal processor (hereinafter DS
(Referred to as P) multiplies the lower bits of the two digital values input from the memory by the first multiplying means and selects only the upper bit thereof, and the second multiplying means generates the upper bit of the two digital values. Multiply the lower bits,
The selected high-order bit and each multiplication value of the second multiplication means are added by the first addition means, and the high-order bit of the addition value is latched in the first latch circuit by the first latch means. As a result, the upper bits having the same number of bits as the upper bits stored in the memory of the original digital value are latched.

The other DSP multiplies the upper bits of the two digital values input from the memory by the third multiplying means, and the third bit and the value latched by the first latch circuit by the second adding means. And the value multiplied by the multiplying means is added, and the value added by the second adding means by the second latching means is divided into upper bits and lower bits and latched in the second latch circuit. As a result, the final result is latched by the total number of bits of the upper bits and the lower bits of the memory and output as needed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a laser length measuring machine will be described below with reference to the drawings. The resolution of the laser length measuring device is 0.6 angstrom unit, and when measuring 1 meter, a data length of 10 ¹⁰ ≈ 2 ^33, that is, 33 bits is required, and 32 bits is insufficient. The maximum data length is 48 bits, and in order to prevent loss of digits, the same 48-bit data is also multiplied to correct the unit exchange and other factors, and real-time output requires a throughput of 4 MHz or higher.

FIG. 1 shows the hardware configuration of this embodiment. As the DSP, two Motorola DSP56001 are used. The data measured by the laser length-measuring device is added with 0 bit below the effective 33 bits.
The upper 24 bits and the lower 24 bits are arranged in the areas X1 and X0 of the memory X and stored. The areas X1 and X0 of the memory X are connected to one DSP1 (first digital signal processor), and the area X1 is the other D1.
It is also connected to SP2 (second digital signal processor). In addition, the count data for temperature correction etc. multiplied by the length measurement data is also adjusted to 48 bits,
The 24 bits and the lower 24 bits are areas Y1 and Y0 of the memory Y.
To be divided into storage regions _Y1, Y0 is connected to the DSP 1, the region Y ₁ is also connected to the DSP 2.

Further, the DSP ₁ has two built-in 48-bit memories A _{1 and} B ₁ for temporarily storing the result during calculation, and the DSP 2 has 2 bits of 48 bit for temporarily storing the result during calculation. Two memories A _{2 and} B ₂ are built in.
Furthermore, the first latch circuit R ₁ for latching the upper 24 bits of the operation result of DSP1 and the upper 24 bits of the operation result of DSP2
A second latch circuit R ₂ for latching the bit and the lower 24 bits separately is provided.

[0012] Next, FIG. 2 a calculation of the multiplier comprising the arrangement in _accordance with the flowchart of FIG. 3, FIG. _4, will be described with reference to FIG. FIG. 2 shows a calculation routine on the DSP 1 side. In step (denoted as S in the figure. The same applies hereinafter) 1, initialization is performed. In step 2, the upper bit Y1 and the lower bit Y0 of the coefficient data are input from the memory Y.

In step 3, the lower bit X0 of the length measurement data input from the memory X is multiplied by the lower bit Y0 of the coefficient data input from the memory Y, and the result is DSP.
No. 1 memory B ₁ . In parallel with this, the upper 24 bits of the previous calculation result stored in the memory A ₁ of the DSP are latched in the first latch circuit R ₁ . This function corresponds to the first latch means. The lower 48 bits are invalid data in the numerical calculation of physics and do not make sense, so they are truncated in advance.

In step 4, the upper bit X1 of the length measurement data input from the memory X is multiplied by the lower bit Y0 of the coefficient data input from the memory Y, and the result is DSP.
No. 1 memory A ₁ is stored. In parallel with this, memory B ₁
Re-storing the results of the X0 × Y0 which has been stored in the lower bits B ₁ 0 of the memory B _1, the upper bits of the memory B ₁ and 0. This is a process for matching and adding the digits of the upper bit of X0 × Y0 and the lower bit of X1 × Y0 + X0 × Y1 described later. The function of the latter stage of step 4 and the X0 × Y0 calculation function of step 3 correspond to the first multiplication means.

In step 5, the lower bit X0 of the length measurement data input from the memory X and the upper bit Y1 of the coefficient data input from the memory Y are multiplied, and the result is multiplied by X1 × Y0 stored in the memory A _1. And add memory A
Update the stored value of ₁ . In parallel with this, the lower bit X0 of the new length measurement data is input from the memory X. In step 6, stored in the lower bits of the memory B ₁ X0
X1 × Y0 + X0 stored in the memory A ₁
The value of × Y1 is added, and the stored value of the memory A ₁ is updated with the result. The upper bits of these are latched in the first latch circuit R ₁ by the function of the subsequent stage of the next step 3. This function corresponds to the first adding means. In parallel with this, the upper bit X1 of the new length measurement data is input from the memory X.

In step 7, the same coefficient data Y1,
It is determined whether or not Y0 has been multiplied by a predetermined number of data, and until it is completed, the process returns to step 3 to repeat the multiplication, and when completed, the process returns to step 2 to input new coefficient data Y1 and Y0. And multiply. FIG. 3 shows the DS
The calculation routine of DSP2 performed in parallel with the calculation by P1 is shown. In step 11, initial setting is performed.

At step 12, the upper bit Y1 of the coefficient data is input from the memory Y. In step 13, the upper bit X1 of the length measurement data is input from the memory X. In step 14, the X latched in the _first latch circuit R ₁
The upper bit of the result of 0 × Y0 + X1 × Y0 + X0 × Y1 is stored in the lower bit of the memory A ₂ of DSP2. In parallel with this, the upper bit of the memory A ₂ is set to 0.

In step 15, memory B of DSP 2₂To
The upper bits of the stored multiplication value of X1X0 × Y1Y0
Second latch circuit R₂Upper bit R of_{twenty one}Latch to.
In step 16, the upper bit X1 of the length measurement data and the coefficient
Multiply with the upper bit Y1 of the data, and the result is X1 × Y1
To the memory A₂X0xY0 + X1xY0 stored in
Memory X by adding the upper bits of the result of + X0 × Y1₂
Remember. This function is the third multiplication means and the second adder
Corresponds to a step. In parallel with this, memory B ₂Lower bit of
To the second latch circuit R₂Lower bit R of₂₀Latch to
It This function and the function of step 15 are the second latch.
It corresponds to the means.

In step 17, it is judged whether or not the multiplication of a predetermined number of data is completed for the same coefficient data Y1, and until it is completed, the process returns to step 13 to repeat the multiplication, and when it is completed, it goes to step 12. Return to new coefficient data Y
Enter 1 to perform multiplication. In this way, the result of multiplication of 48 bits is adjusted to have an effective length of 48 bits. Figure 4
The operation cycle is shown. In DSP1, the data input (sample) and the latch are processed in parallel with the multiplication. As a result, the operation is completed in 4 cycles, _{and the} latch is completed. _{Then, the} latch is ended, and the DSP1 _and DSP2 perform the operation in parallel, so the operation _{and the} latch are completed in four cycles as a whole.
Therefore, since 1 cycle is executed in 60ms, 60ms ×
4 = 240ms, which gives a throughput of about 4MHz,
A very fast multiplication function can be obtained.

[0020]

As described above, according to the present invention, the parallel processing function of the DSP and the truncation of the invalid bit are achieved while having a simple and low-cost circuit configuration using only one set of DSP and latch circuit. Thus, multiplication of high bit numbers can be processed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing arithmetic processing on the DSP 1 side of the above embodiment.

FIG. 3 is a flowchart showing arithmetic processing on the DSP 2 side of the above embodiment.

FIG. 4 is a time chart showing the operation cycle of the above embodiment.

FIG. 5 is a diagram showing a calculation process of the above embodiment.

[Explanation of symbols]

DSP1 first digital signal processor DSP2 second digital signal processor A ₁ DSP1 memory B ₁ DSP1 memory A ₂ DSP2 memory B ₂ DSP2 memory X measurement data memory Y coefficient data memory R ₁ first for a the Latch circuit R ₂ Second latch circuit

Claims (1)

[Claims] 1. A multiplication device for multiplying two digital values, comprising a set of digital signal processors, a set of latch circuits, and a memory for storing two digital values by dividing them into an upper bit and a lower bit, respectively. , And a first multiplication means for selecting only the high-order bit of the value obtained by multiplying the low-order bits of the two digital values by one digital signal processor, and the high-order of the two digital values. Second multiplication means for multiplying bits and lower bits, first addition means for adding each value multiplied by the first multiplication means and the second multiplication means, and a value obtained by addition First latch means for selecting the upper bit of the above and latching it in the first latch circuit, and multiplying the other digital signal processor with the upper bits of the two data. Third multiplying means, second adding means for adding the value latched by the first latch circuit and the value multiplied by the third multiplying means, and addition by the second adding means. Second latch means for dividing the obtained value into upper bits and lower bits and latching them in a second latch circuit;
A multiplying device characterized by being equipped with.