JPH0578967B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a bipolar semiconductor device, and more particularly to a semiconductor integrated circuit with improved resistance to alpha rays.

(2) Technical background With advances in semiconductor manufacturing technology, highly integrated circuits have become possible. This is due to, for example, etching techniques that have made it possible to form metal wiring lines of 1 micron, etc., and the highly integrated mask patterns used to form them.

In particular, in recent years, semiconductor integrated circuits using bipolar transistors have become highly integrated, and the size of the transistors constituting the circuits, as well as the current flowing through them, are decreasing, and the amplitude values are also becoming smaller. This has made it possible to achieve high integration, but on the other hand, the alpha ray resistance has decreased. That is, resistance to alpha rays has been a problem in conventional semiconductor integrated circuits using MOS transistors, but it has become desirable to improve the resistance to alpha rays even in bipolar transistor semiconductor integrated circuits.

(3) Conventional technology and problems When the α-ray tolerance decreases, circuit malfunctions occur more frequently. That is, for example, in the depletion layer formed at the PN junction between the collector and the substrate, pairs of electrons and holes are generated by irradiation with α rays, and the electrons are absorbed by the collector and the holes are absorbed by the substrate, so the collector potential decreases. will decrease. Since the output of a simple combination of gate circuits, that is, a combinational circuit, is determined only by the input, temporary noise due to alpha rays (noise for a short period of time that is faster than the operating speed of the circuit) does not pose much of a problem. However, a circuit containing a feedback loop,
For example, a sequential circuit consisting of a flip-flop or the like has a problem in that the circuits forming the loop respond to the high-speed noise. That is, since the output of a sequential circuit is determined by the input and the holding state, if the holding state is reversed by α rays, the output will also be reversed. Therefore, as mentioned above, when the potential of the output collector of an ECL circuit decreases due to alpha ray irradiation, the held contents of a flip-flop (FF) composed of an ECL circuit and having a feedback loop are reversed. There are some problems with this. Therefore, the latch circuit,
Sequential circuits made of FF or other memory circuits have the problem that if the circuit itself or its input stage transistors are irradiated with alpha rays, the contents held will change and the circuit will no longer function normally.

(4) Purpose of the invention The present invention solves the above-mentioned problems,
The objective is to provide a semiconductor integrated circuit that has improved resistance to alpha rays and can be operated at higher speeds and with higher integration. In particular, in the present invention, when configuring a sequential circuit in an ECL circuit, the holding current is set larger than in other combinational circuits to increase speed and
It is designed to achieve both high integration and resistance to alpha rays.

(5) Structure of the Invention The present invention is characterized by a semiconductor device in which, in a sequential circuit, the holding current of the data holding circuit is set to be larger than the operating current of the gates constituting other combinational circuits.

(6) Embodiment of the invention Hereinafter, an embodiment of the invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

Transistors Tr ₁ and Tr ₂ whose emitters are commonly connected and connected to the power supply V _EE1 via the current source Ix ₁
The bases of each are connected to the input terminal D and the reference power supply Vref, respectively. Further, the collectors of the transistors Tr ₁ and Tr ₂ are commonly connected through resistors R ₁ and R ₂ respectively, and further connected to the power supply V _CC through a resistor R ₀ . The collector is connected to the power supply V _CC , the base of the transistor Tr ₃ is connected to the collector of the transistor Tr ₂ , and its emitter is connected to the power supply V _EE2 via a resistor R3. OR gate 1 consisting of transistors Tr ₁ and Tr ₂
is a current switching type circuit called ECL (Emitter).
Current Logic), and if there is another input, that input is applied to the base of a transistor (not shown) whose emitter and collector are connected to the emitter and collector of transistor Tr ₁ , respectively. The output of this OR gate 1 is applied from the emitter output of the emitter follower transistor Tr ₃ via the terminal A to the base of the input transistor Tr ₄ of the ECL OR gate 2 formed by transistors Tr ₄ and Tr ₃ . The emitters of the transistors Tr ₄ and Tr ₅ , whose respective emitters are commonly connected, are connected to the power supply V _EE1 via the current source Ix ₂ , and their respective collectors are commonly connected via the resistors R ₄ and R ₅ . Furthermore, it is connected to the power supply V _CC via _R8 . Transistor Tr ₅
The collector is the output of OR gate 2, and the collector is connected to the power supply V _CC , and the emitter is connected to the power supply through resistor ₆ .
Emitter follower transistor connected to V _EE1
Connected to the base of Tr ₆ . transistor
Tr ₇ , Tr ₈ and Tr ₉ are ECL or gates 3. The collectors of transistors Tr ₇ and Tr ₈ whose collectors and emitters are commonly connected are resistors R ₇ ,
Connected to power supply V _CC via R ₇ ′. Resistance _R7 ,
The connection point of R ₇ ' is connected to the common connection point of resistors R ₄ and R ₅ . The base of the transistor _Tr7 is connected to the emitter of the emitter follower transistor _Tr6 , and the base of the transistor _Tr8 is connected to the terminal B as another input. The emitters of transistor Tr ₉ are further connected to the emitters of the commonly connected transistors Tr ₇ and Tr ₈ to form a current switching type, and these emitters are connected to a current source.
Connected to power supply V _EE1 via Ix ₃ . A reference power supply Vref is applied to the bases of transistors Tr ₅ and Tr ₉ .
The output of the ECL OR gate 3 with transistors Tr ₈ , Tr ₇ and Tr ₉ is the collector C' of transistor Tr ₉ . Point C' is fed back to the input of emitter follower transistor Tr ₆ to maintain logic. As described later, point C′ is Tr ₄ ,
Since it forms a wired AND with the output A' of OR gate 2 by Tr ₅ , the output of this AND is fed back to OR gate 3 by Tr ₇ , Tr ₈ , and Tr ₉ .
It is used as an input. The wired AND output C' is connected to the base of an emitter follower transistor _Tr10 whose emitter is connected to the power supply _VEE2 via a resistor _R9 , and its emitter is applied via a terminal C to the OR gate 4 at the next stage. OR gate 4 has the same configuration as the above-mentioned OR gate 1, and has a resistance R ₁₀ ~
R ₁₃ is connected to resistor R ₀ to R ₃ , transistors Tr ₁₁ to _{Tr 13}
correspond to Tr ₁ to _{Tr 3} , respectively. In addition, current source Ix ₄
also corresponds to the current source Ix ₁ , but its current value is Ix<Ix ₁ for reasons described later. The output of the OR gate 4 is the terminal E.

If Figure 1 is expressed at the gate level, it will be as shown in Figure 2, where OR gate 1 has an input of D and an output of A, and OR gate 2 has an input of A and an output of
It becomes A′. Then, OR gate 3 inputs B input and wired output C', and this OR gate 3
The output of is wire-ANDed with A′ to become C′.
Then, point C' becomes point C via Emifluoro Tr ₁₀ , which becomes an input to OR gate 4, and its output becomes E. Next, the operation of the embodiment configured as described above will be explained.

In the OR gate 1, when the input D is high, that is, when it is larger than Vref, the transistor Tr ₁ is turned on, and a current Ix ₁ flows through R ₀ and R ₁ .
Therefore, since no current flows through R ₂ , the collector or output of transistor Tr ₂ is at a high level (V _CC
−R ₀ Ix ₁ ). Therefore, when the logic of D is high, the output will be high. Further, when D is at a low level, that is, when it is lower than Vref, the transistor Tr ₂ is turned on, and the current Ix ₁ also flows through R ₂ . Therefore, the output is low level {V _CC − (R ₀ + R ₂ )
×Ix ₁ }. That is, the input logic is transmitted to the output logic. If the input is only D, it is just a buffer, but if other inputs are given to the bases of transistors Tr ₁ and other transistors whose collector-emitters are each connected in common, this circuit becomes an OR circuit as described above. Become. Since the transistor Tr ₃ is an emitter follower, the emitter terminal A has a level that is only about 0.8V lower than the collector potential of the transistor Tr ₂ , which is the OR output.
The logic of the point is the same as the logic of the collector output of Tr ₂ . Similarly, since 2 is a one-input OR gate, the output A' of OR gate 2 is the same as the logic of the input A, and since the transistor Tr ₆ is an emitter follower, the logic of its emitter is also the same as A'.
That is, the logic of the input D is transmitted as is to the output A' of the OR gate 2.

Next, a latch circuit using OR gate 3 and wired AND C' will be explained. The logic that is maintained is the potential of C', and it is assumed that C' is currently at a low level.

Furthermore, in order for the potentials at points C and C' to be latched as shown in FIG. 2, it is assumed that input A is high and input B is low. At this time, since point A is at high level in OR gate 2, transistor Tr ₅ is turned off, and point A' is about to go to high level, but since point C' is assumed to be at low level, Tr ₅ Even though R5 is off, current flows through resistor _R5 .
It is flowing towards point C′. Therefore, when point C' is at low level, point A' is also at low level, transistor Tr ₇ is turned off, and point B is also at low level, so transistor Tr ₈ is also turned off. That is, in the OR gate 3, the transistor _Tr9 is turned on. Therefore, point C′ and point A′ are
Due to the ON state of Tr ₉ , the voltage is maintained at a low level due to the voltage drop caused by the current Ix ₃ flowing through R ₅ .

Next, assume that point C′ is at a high level. Again, assume that A is high and B is low.
When point C' is at a high level, point A' is at a high level, so transistor Tr ₅ is off, no current flows through _R5 , and point C' is at a high level of V _CC −R ₈ × Ix _2. , the transistor Tr ₇ is turned on. Therefore, no current flows through the transistor Tr ₉ , and the point C' is held at a high level. Therefore, when A is high and B is low, the level will be maintained regardless of whether point C' is low level or high level, and the OR gate 3 and wired AND C' will hold that level. This constitutes the holding circuit of the sequential circuit. Therefore, if the logic at point C' is inverted by the α ray, the inverted logic will be retained.

To write an input to the holding circuit, keep the B point high and apply the opposite logic to the latch output as the A input, thereby writing the opposite logic to the holding circuit. The output C' of the wired AND is also the output of the holding circuit, and is taken out to the emitter of the emitter follower transistor _Tr10 .

In the circuit shown in Figure 1, wired and output
It is desirable that the holding voltage at point C′ is not affected by noise. In other words, the high level is once
Once held at point C', point C' should always remain high level and should not be flipped to low level due to noise in the latched state. This is because once the logic of the holding circuit is inverted, the inverted data is held as it is, and as a result, the output of the sequential circuit is determined by the input data and the held data, so it is inverted. This is because there are things. However, as bipolar transistors are integrated on a large scale, the size of each transistor formed individually becomes smaller, and the influence of α rays as noise increases.

In order to reduce the influence of the α rays, the inventors have found that it is sufficient to keep the size of the transistor small and to increase the holding current at the output point C' of the holding circuit.

In Fig. 1, holding current Ix ₃ is the current required to hold point C' at low level, and Ix ₂ is:
This is the current to maintain point C′ when it is at a high level. Therefore, in order to reduce the influence of α rays, the holding currents Ix ₂ and Ix ₃ are made larger than the current Ix of other combinational circuits, such as the OR circuit 4 at the subsequent stage. Furthermore, the output point C′ of the latch circuit is
In particular, when maintaining a high level, it is also affected by the current flowing through transistor Tr ₄ , that is, the current flowing through R ₈ , and it is necessary to maintain the current so that it does not flow through R ₅ . Therefore, as the input of the holding circuit
It is necessary to prevent the potential at point A' from decreasing due to the influence of alpha rays, etc. This is because, as is clear from FIG. 2, in order to maintain the logic of the output C' of the wired AND C via feedback, the input A of the wired AND C' must be held high. For this reason, the current Ix ₁ of the gate at the front stage of the holding circuit, that is, the OR gate 1 in FIG. It is necessary to keep it. In general, the noise generated by alpha rays is faster and shorter time noise than the operating speed of the ECL, so by passing it through a multi-stage, for example, two-stage gate circuit, the noise can be reduced to a logic level. It will no longer have any influence. In other words, the noise is attenuated by the response speed of each gate circuit, and it almost never passes through multiple stages.
For this reason, as described above, the gate circuit at least one stage before the holding circuit must also be a circuit that is not affected by alpha rays.

In the present invention, as described above, the holding current of the holding circuit and the operating current of the preceding stage circuit are set to be large. By increasing the holding current, even if the junction between the collector of the transistor in the holding circuit and the substrate is irradiated with alpha rays and the collector potential drops, the effect can be minimized and the held data can be inverted. To prevent.

The method for setting the current connected to the common emitter of a current-switched circuit is as shown in Figure 3.
There are two types: a transistor type, which functions as a current source with a resistance at its emitter, and a resistance type, which is simply a resistor, as shown in FIG.

In the constant current type shown in Figure 3, the base voltage (V _CS ) - the forward voltage between base and emitter (V _BE )
is applied to one end of the resistor R, so the current value obtained by subtracting the other end potential V _EE and dividing by R becomes Ix. Therefore,
If R is fixed, the base potential V _CS may be increased in order to increase Ix.

On the other hand, in the case of _the resistor type shown in _FIG .
Since the voltage subtracted by 0.8V is the emitter voltage, a current flows through the resistor R so that the emitter voltage becomes that potential. Therefore, in order to increase the current Ix,
It is better to reduce the resistance.

(7) Effects of the Invention According to the present invention, it is possible to avoid malfunction of data held in a data holding circuit such as a latch circuit due to fluctuations in voltage level caused by α rays, especially in large-scale integrated bipolar circuits. can. By increasing only the holding current of the data holding circuit and the operating current of its input circuit, the influence of the α rays is suppressed, so the current sources of the other combinational circuits may remain small. Therefore, since the power consumption remains low, it is possible to achieve high integration, and at the same time, it is possible to provide resistance to alpha rays, which is a great effect.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of one embodiment of the present invention, Fig. 2 is a block diagram of the above embodiment, Fig. 3 is a circuit diagram showing an example of the current supply section in the above embodiment, and Fig. 4 is a circuit diagram of the above embodiment. FIG. 3 is a circuit diagram showing another example of the current supply section of FIG. 1, 2, 3, 4...OR gate, C'...wired and, Ix ₁ , Ix ₂ , Ix ₃ ...constant current source, Ix...
...constant current source.

Claims (1)

[Scope of Claims] 1. A sequential circuit and a combinational circuit configured by an ECL circuit are provided, the current value flowing through the common emitter terminal of the ECL circuit constituting the data holding circuit of the sequential circuit is higher than that of the combinational circuit. A semiconductor integrated circuit characterized by having a large size. 2 Configure the input circuit of the data holding circuit
2. The semiconductor integrated circuit according to claim 1, wherein a current value flowing through the common emitter terminal of the ECL circuit is set larger than that of the combinational circuit.