JPH0577788U - Electronic circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to reduce the number of input terminals for switching between the test mode and the normal mode and performing the reset operation at the time of such switching. According to the present invention, in an electronic circuit having a test mode for confirming an operation and a normal mode for performing a normal operation, one input terminal for inputting a switching signal for the above two modes, Means for detecting a change in the switching signal and generating a reset signal for resetting the circuit.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an electronic circuit having a test mode for confirming an operation and a normal mode for performing a normal operation.

[0002]

[Prior Art]

 Generally, in an electronic circuit, for example, a gate array, a test terminal for performing an operation test of whether the gate array operates normally is provided.

This test terminal is used in a test mode for confirming whether the gate array is operating normally, and is no longer used during normal operation of the gate array.

Further, a reset terminal for inputting a reset signal for resetting the gate array is provided at the time of switching to the test mode and at the time of switching from the test mode to the normal mode in which normal operation is performed. There is.

[0005]

[Problems to be solved by the device]

 As mentioned above, the gate array requires a reset terminal and a test terminal, but in order to reduce the number of required terminals as much as possible, it is desirable to remove the test terminals that are not used during normal operation. By the way.

However, if the test terminals are lost, the operation test cannot be performed.

Therefore, the present invention aims to reduce the number of input terminals by switching between the test mode and the normal mode and the reset operation at the time of switching by an input signal to one input terminal. Is to

[0008]

[Means for Solving the Problems]

 According to the present invention, in an electronic circuit having a test mode for confirming an operation and a normal mode for performing a normal operation, one input terminal for inputting a switching signal between the above two modes and the above Means for detecting a change in the switching signal and generating a reset signal for resetting the circuit.

[0009]

[Action]

 According to the present invention, when a switching signal for switching between a test mode for confirming an operation and a normal mode for performing a normal operation is input from one input terminal, a change in the switching signal is detected. Then, a reset signal for automatically resetting the circuit is generated.

[0010]

【Example】

 FIG. 1 shows a circuit diagram of an embodiment of the present invention. The circuit is provided, for example, in the gate array. 1 is a first inverter that inverts the RST signal input from one input terminal and outputs the inverted signal as a TEST signal. 2, 3 and 4 are first and second serially connected first inverters. The second and third D flip-flops (hereinafter, referred to as D-FF). Specifically, the output signal of the first inverter 1 is applied to the D terminal of the first D-FF2, and the output signals of the Q terminals of the first D-FF2 and the second D-FF3 are It is applied to the D terminals of the second D-FF3 and the third D-FF4, respectively. A CLOCK signal is applied to each T terminal of the D-FFs 2, 3 and 4.

Further, 5 is an exclusive OR gate to which the output signals of the Q terminals of the first D-FF 2 and the third D-FF 4 are applied, and 6 is an output of the exclusive OR gate 5. It is a second inverter that inverts and outputs it as a RESET signal to a gate array (not shown).

FIG. 2 shows a timing chart of the operation of such a circuit diagram.

Now, assuming that the RST signal is in the HIGH state (hereinafter referred to as the H state), the output of the second inverter 6, that is, the RESET signal is also in the H state, so that the gate array operates normally. It is in the normal mode.

When the RST signal changes from this state to the LOW state (hereinafter, referred to as the L state), the output of the first inverter 1 changes to the H state and in synchronization with the first rising edge of the CLOCK signal. , The output signal of the Q terminal of the first D-FF 2 changes to the H state. At this time, the output signal of the Q terminal of the third flip-flop 4 is still in the L state, so that the output of the exclusive argument gate 5 is in the H state. Therefore, the output of the second inverter 6, that is, the RESET signal changes to the L state, and the reset mode is started.

After that, the output signal of the Q terminal of the second D-FF3 becomes the H state in synchronization with the rising edge of the next CLOCK signal, and further, in synchronization with the rising edge of the next CLOCK signal, the third D -The output signal from the Q terminal of FF4 is in the H state. At this point, the two input signals to the exclusive OR gate 5 (that is, the output signals of the Q terminals of the first and third D-FFs 2 and 4) are both in the H state, and therefore the second inverter 6 The RESET signal, which is the output of, changes to the H state, and the reset mode is released.

As a result, the gate array is reset.

At this time, the TEST signal that is the output signal of the first inverter 1 is in the H state, and after the reset, the gate array is in the test mode.

Next, the change from the TEST mode to the normal mode is performed by changing the RST signal from the L state to the H state. That is, when the RST signal changes to the H state, the TEST signal first changes to the L state. Then, in synchronization with the first rise of the CLOCK signal, the output signal of the Q terminal of the first D-FF2 becomes L state, and the output of the exclusive OR gate 5 changes to H state. Therefore, the RESET signal becomes L state, and the reset mode starts.

Thereafter, with the application of the two CLOCK signals, the output signal of the Q terminal of the third D-FF 4 changes to the L state, and as a result, the output signal of the exclusive OR gate 5 changes to the L state. Then, the RESET signal becomes the H state, the reset mode is released, and the normal mode is set.

[0020]

[Effect of the device]

 According to the present invention, in an electronic circuit having a test mode for confirming an operation and a normal mode for performing a normal operation, one input terminal for inputting a switching signal for the above two modes, Since it has means for detecting a change in the switching signal and generating a reset signal for resetting the circuit, it is possible to switch between the test mode and the normal mode by simply changing the signal applied to one input terminal. Also, the reset operation at the time of such switching can be performed, and the number of input terminals can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the circuit of the present invention.

[Explanation of symbols]

 1 1st inverter 2 1st D-FF 3 2nd D-FF 4 3rd D-FF 5 Exclusive OR gate 6 2nd inverter

Claims (1)

[Scope of utility model registration request] 1. A test mode for confirming operation,
In an electronic circuit having a normal mode for performing a normal operation, one input terminal for inputting a switching signal for the two modes, and a reset for detecting a change in the switching signal and resetting the circuit An electronic circuit comprising means for generating a signal.