JPH057747B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for automatically generating logic circuits, and in particular to a method suitable for converting functional logic expressed in Boolean algebra into an electronic circuit using basic elements of a specific technology. This paper relates to a method for automatically generating logic circuits.

[Traditional background]

Attempts have been made for a long time to automate the generation of logic circuits at the gate logic level from Boolean algebraic expressions using so-called logic circuit design support systems, and there are many known examples. However, the conventional method of automating the generation of logic circuits from Boolean algebraic expressions has the disadvantage that the number of gates increases compared to manual design. For example, IBM's "Logic generation by local transformation" (JA
Darniger et al., IBM J.RES.DEVELOP.Vol25, No.
4.Jul.'81), (1) simplification of AND/OR level,
Conversion and local optimization have been attempted in three stages: (2) simplification at the NAND (NOR) level and (3) simplification at the hardware level, but the processing is complex and compared to manual design. Gates will increase by 0-15%,
The drawback was that an optimal logic circuit could not be generated.

[Purpose of the invention]

It is an object of the present invention to make Boolean expressions more technology-dependent by introducing an explicit concept of polarity in the variables and outputs of Boolean expressions.
To provide a method for automatically generating logic circuits that enables gate-level logic circuits to be automatically generated directly from Boolean algebraic expressions without converting to NAND or NOR format, and that has conversion performance comparable to that of manual design. be.

[Summary of the invention]

The key point of the present invention is to create a binary tree structure corresponding to two-input basic elements by converting Boolean algebraic expressions expressing functional logic into Polish notation, and to create basic elements of a specific technology that can continue to use the same operator group. Convert it into a multi-tree by grouping considering fan-in conditions, and then consider constraints such as input/output polarity, minimization of fan-in number, delay time, etc. for basic elements that can be used with the specific technology. A logic circuit is generated by selecting basic elements that satisfy the conditions of a specific technology by tracing the polygon tree backward (root side) based on a parts list created by prioritizing It is.

Here, the specific technology refers to the configuration method of circuit components such as transistors and resistors when realizing logical functions. In other words, bipolar LSI and CMOS LSI have different basic elements, electrical characteristics, and design constraints depending on the configuration method.
There are LSIs, each with a NOR gate (OR gate +
The device is basically composed of a NAND gate (AND gate + inverter) and a NAND gate (AND gate + inverter). When creating an electronic circuit (logic circuit) for a specific LSI (LSI to be created) from a given functional logic, use the basic elements and design constraints prepared based on the technology of the specific LSI (specific technology). It is necessary to create an electronic circuit.

[Embodiments of the invention]

An embodiment of the method for automatically generating a logic circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a method of describing functional logic that introduces the concept of polarity. In the figure, 1 is a negative electrode,
2 is a positive electrode, and 3 is an input variable. The positive electrode 2 is shown as going in and out of the box directly, and the negative electrode 1 is shown going in and out through a circle. Boolean algebraic expressions must always be written in positive logic within the box.

(1) First, a Boolean algebraic expression written in positive logic is converted into a binary tree using Polish notation conversion. This binary tree converted is shown in FIG. 2.1.

(2) Regarding the binary tree created in (1) above, group consecutive identical operators (AND, OR, etc.) within the number of fines of the specific technology that can be used. As a result, a binary tree as shown in FIG. 1 is converted into a multitree as shown in FIG. 2. That is, the nodes (branch points) 5 and 6 in FIG. 2 are converted into nodes 9 in FIG. 2.

(3) After the conversion from a binary tree to a multi-tree is completed, backward tracing is performed from node 8, which is the root of the tree shown in FIG. Node 8 is
OR, since the number of fines of the node is 2 and the output polarity is positive, basic elements satisfying these conditions are selected in accordance with the order of priority from the parts list shown in FIG. 4 prepared in advance. This bill of materials is created in advance by prioritizing the basic elements that can be used with a specific technology, taking into account constraints such as input/output polarity, number of fines, minimization of the number of elements, and delay time. For node 8,
Specifically, the elements to be selected correspond to the 3-input OR and the 6-input OR, but since the 3-input has a higher selection order than the 6-input OR, the 3-input OR is selected.
As a result of the selection, basic element 11 in FIG. 3 is obtained as a component corresponding to node 8 in FIG. 2.

(4) Check the input conditions of the selected basic element 11 and decide whether to continue or end backward tracking. Since the input variable D is directly input to the right side of the node 8 in FIG. 2, backward tracking ends, but the input polarity of the input variable D is negative (see D in FIG. 1).
Since the input polarity of the basic element 11 does not match the positive (see the table in FIG. 4), the polar positive matching inverter 12 shown in FIG. 3 is generated, and the polarity matching is completed by matching the two. On the other hand, since the output of node 9 is input to the left side of node 8, backward tracking is continued. At this time, the positive input polarity of the node 8 (that is, the input polarity condition of the basic element 11) is propagated as the output polarity of the node 9.

(5) The above processes (3) and (4) are performed sequentially for node 9 and node 10. Since the operator of node 9 is AND, the number of fines of the node is 3, and the output polarity is positive, the basic element 13 that satisfies these conditions is selected using the parts list shown in FIG.
The input variables A and B are directly input to the left side of the node 9, and the input polarities of the input variables A and B are negative, and the input polarity of the basic element 11 is also negative, so the backward tracking ends because they match. Complete. Since the output of node 9 is input to the right side of node 9, backward tracking is continued. At node 10, the operator is NOT, the number of fines is 1, the output polarity is negative like the input polarity of node 9, and the input polarity of input variable C is positive, so basic element 14 is determined from the parts list shown in Figure 4. selected.

(6) After completing the selection of basic elements for all nodes, delete unnecessary inverters.
Since the basic element 13 in FIG. 3 is a NAND circuit, it has a function of inverting an input variable having a positive input level. Therefore, the basic element 14 generated to invert the input variable C becomes unnecessary, and this basic element 14 is deleted as an unnecessary inverter. The final logic circuit thus obtained is shown in FIG. 3.

FIG. 5 is a flowchart showing the processing procedure of the method for automatically generating a logic circuit according to the present invention, which is executed on a logic design support system. In the figure, reference numerals indicate each step of the flow.

Input the Boolean algebraic expression written in positive logic for which the logic circuit is to be designed (step 21). The Boolean algebraic expression is converted into a binary tree by Polish notation conversion (step 22). Continuous groups of identical operators are grouped within the number of fines of a specific technology and converted into a polygon tree (step
twenty three). Backward tracking is performed from the root node of the tree (step 24), a basic element is selected by referring to the parts list (step 25), an input variable is reached (step 26), and the backward tracking of the corresponding node is completed. It is determined whether basic elements have been selected for all nodes (step 27), and if there is a node for which basic elements have not been selected, the process returns to step 24. When the selection of basic elements for all nodes is completed, unnecessary inverters are deleted (step 28), and the process of generating the target logic circuit is completed.

〔Effect of the invention〕

As explained above, in the method for automatically generating a logic circuit according to the present invention, the basic electronic components constituting a Boolean algebraic expression are limited by a specific technology, and these components are selected and combined to operate electronically. In order to create a possible electronic circuit, the output of the Boolean algebraic expression and the polarity of the input variable are uniformly given as positive or negative logic, and the logic function and polarity of the input/output terminal are determined for each component, which is the basic element of a specific technology. is uniformly expressed using positive or negative logic, has a parts list that refers to it in a certain priority order, converts the Boolean algebraic expression into a binary tree using Polish notation conversion, and then converts it into a multitree structure using operator synthesis. Then, after selecting a component from the parts list using the output polarity of the Boolean algebra expression as a key, backward tracing is continued until the input variable of the Boolean algebra is reached, and the polygon tree is mapped to the component, making the process simple. It has an excellent effect of having conversion performance similar to that of a procedural and manual design.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram showing a method for describing functional logic that introduces the concept of polarity, Figure 2 1 and 2 are explanatory diagrams showing a multitree representation method for Boolean algebraic expressions, and Figure 3 1 and 2 are diagrams showing how to express functional logic to basic elements. FIG. 4 is an explanatory diagram showing the conversion process, FIG. 4 is a diagram showing a parts list, and FIG. 5 is a flowchart showing the processing procedure according to the present invention. 1...Negative pole, 2...Positive pole, 3...Input variable, 4
~10...Node number, 11-14...Basic element.

Claims (1)

[Scope of Claims] 1. A method for automatically generating a functional logic logic circuit expressed in a Boolean algebraic expression using basic elements of a specific technology, which comprises:
It is equipped with a bill of materials showing its logic functions, fan-in/fan-out numbers, polarity input/output conditions, and selection priority, and a step for uniformly providing the output of a Boolean algebraic expression and the polarity of variables with positive or negative logic; Convert Boolean algebraic expressions to Polish notation,
a step of decomposing the binary tree into a binary tree structure of operators and variables, and a step of converting the binary tree structure into a multitree structure by integrating consecutive identical operators in the decomposed binary tree according to the fine conditions of a specific technology. Then, regarding the multitree structure, refer to the parts list using the output polarity of the Boolean algebraic expression as a key, select parts that satisfy the logical function and output polarity according to the selection priority, and then Using the input polarity as the output polarity for the next component selection, sequential backward tracing is continued until the input variable of the Boolean algebraic expression including the polarity is reached, and each node of the polygon tree is mapped to a component to calculate the functional logic of the Boolean algebraic expression. A method for automatically generating a logic circuit, comprising: steps for generating a logic circuit; and a method for automatically generating a logic circuit.