JPH0575018A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable realization of three-dimensional IC which can operate at a high speed, by a method wherein polycrystalline InP is used for a device material of each layer, while a material having a higher melting point than the one for formation of the polycrystalline InP is used for an electrode wiring. CONSTITUTION:Devices such as MIS transistors are formed respectively in a first layer 2 and a second layer 3 formed on an Si substrate 1 and they function as three-dimensional IC. As a device material for the second layer 3, polycrystalline InP of which the carrier mobility is larger by one order of magnitude or above than that of polycrystalline Si and which is formed at a lower temperature than Si is used. Accordingly, it is unnecessary to use a high-melting metal material as a material for an electrode wiring 5 and Al having a melting point lower than the one of tungsten and higher than the temperature of formation of the polycrystalline InP may be used therefor. It is unnecessary to make it be of single crystal, unlike Si, and thus the device which can operate at a high speed can be prepared with ease.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer structure used for an image sensor and the like and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, parallel processing circuits capable of handling enormous amounts of information, intelligent image sensors, and the like have been in the limelight in the field of electronic devices, etc. A semiconductor device having a structure as a three-dimensional IC is required.

A semiconductor device of this kind has a multi-layer structure as shown in FIG. 2, for example, and in the example of FIG.
It has a two-layer structure of a first layer 51 formed on the i substrate 50 and a second layer 52 formed on the first layer 51. That is, each of the first layer 51 and the second layer 52 has M
Devices such as IS transistors are formed, and three-dimensional ICs
It has a function as.

In the conventional method of manufacturing such a semiconductor device, as the first layer 51, S is first formed on the Si substrate 50.
An insulating film such as iO ₂ is formed, the insulating film is subjected to predetermined etching, and the substrate 50 is doped with a predetermined impurity to form a source or drain region 53, or a predetermined electrode wiring 54 is formed. Alternatively, the gate electrode 55 of polycrystalline Si is formed to form a device such as a MIS transistor. After that, an insulating film of SiO ₂ or the like is formed again with a predetermined thickness to form the first layer 51.

Then, the second layer located on the upper layer of the first layer 51.
When forming the layer 52, a polycrystalline Si film 56 is first formed on the first layer 51, and then an insulating film such as SiO ₂ is formed, and the insulating film is formed through this insulating film. Lower polycrystalline S
The film 56 of i is subjected to predetermined etching, the film 56 of polycrystalline Si is doped with predetermined impurities to form the source and drain regions 57, and the gate electrode 58 of polycrystalline Si is used.
To form a device such as a MIS transistor. After that, an insulating film of SiO ₂ or the like is formed to a predetermined thickness to form the second layer 52.

[0006]

By the way, polycrystalline Si
Has a small carrier mobility of about 10 to 100 cm ² / V · S. Therefore, in order to obtain a device capable of high speed operation, for example, in the second layer 52 of FIG. It is necessary to form a single crystal by scanning or the like. However, it is technically difficult to form a single crystal having good crystallinity into a fine pattern as shown in FIG. 2. As a result, in the field of three-dimensional IC and the like, a device having a large mobility and capable of operating at high speed has been developed. There was a problem that it was difficult to form.

Further, in order to form polycrystalline or single crystal Si, a high heating temperature of about 600 ° C. or higher is required. Therefore, as shown in FIG. 2, the electrode wiring 54 is formed on the first layer 51, When the polycrystalline Si film 56 or the like is formed on the second layer 52 above it, the polycrystalline Si film 56 is used as the electrode wiring 54.
It is necessary to use a material that does not melt when forming the above, that is, a material that has a melting point higher than the above high temperature. Therefore, conventionally, the material of the electrode wiring 54 is, for example, W, M _O , P, or the like, a silicide that is a reaction product of these, and Si, or a two-layer structure of polycrystalline Si and the refractory metal. The polycide was used. However, the specific resistance of these refractory metals, silicides, and polycides is about 10 μΩ · cm, which is smaller than the specific resistance of polycrystalline Si, but the specific resistance of metals such as Al (about 2.5 μΩ · for Al). cm), which is about an order of magnitude larger and is inferior in conductivity. As a result, there is a problem in that the characteristics of a device that requires high speed operation are deteriorated.

As described above, in the conventional semiconductor device, since Si is used as the material of the device such as the MIS transistor located in the upper layer of the multi-layer structure, it cannot have a large carrier mobility and the lower layer of It is extremely difficult to realize a practical three-dimensional IC capable of operating at high speed because it is not possible to use an electrode wiring having a small specific resistance.

It is an object of the present invention to provide a semiconductor device suitable for realizing a practical three-dimensional IC or the like that can operate at high speed, and a manufacturing method thereof.

[0010]

In order to achieve the above object, the present invention uses a polycrystalline InP as a device material of each layer in a semiconductor device having a multilayer structure, and the electrode wiring is made of a polycrystalline InP. A material having a melting point higher than the temperature at which it is formed, such as Al, is used.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a semiconductor device according to the present invention.

The semiconductor device of this embodiment has a multi-layer structure as shown in FIG. 1 corresponding to FIG. 2, for example.
This example has a two-layer structure of a first layer 2 formed on the Si substrate 1 and a second layer 3 formed on the first layer 2. That is, the first layer 2 and the second layer 3 each have M
Devices such as IS transistors are formed, and three-dimensional ICs
It has a function as.

By the way, in this embodiment, the second layer 3 is provided with MI.
In order to form a device such as an S-transistor, as a device material thereof, polycrystalline InP having a carrier mobility higher than that of polycrystalline Si by one digit or more and formed at a temperature lower than that of Si is used. .. Specifically, polycrystalline InP can be formed to have a large carrier mobility of about 500 to 1000 cm ² / V · S, and can be formed at a low temperature of 400 ° C. or lower.

In order to manufacture the semiconductor device as shown in FIG. 1, first, an insulating film such as SiO ₂ is formed on the Si substrate 1 as the first layer 2, and the insulating film is subjected to predetermined etching. The substrate 1 is doped with a predetermined impurity to form a source / drain region 4 therein, a predetermined electrode wiring 5 is formed therein, and a polycrystalline Si gate electrode 6 is formed to form a MIS transistor. Etc. to form a device.

At this time, as a device material of the second layer 3 to be formed after the first layer 2 is formed, in this embodiment, polycrystalline InP formed at a low temperature of 400 ° C. or lower as described above. Therefore, it is not necessary to form the electrode wiring 5 by using a high melting point metal or a material having a high melting point such as silicide or polycide as in the related art, and a material such as Al having a lower melting point than W, M _O , The electrode wiring 5 can be formed by using this.

After that, an insulating film of SiO ₂ or the like is formed again with a predetermined thickness to complete the formation of the first layer 2. Next, when forming the second layer 3 located above the first layer 2, the polycrystalline InP film 7 is first formed on the first layer 2. Then, an insulating film such as SiO ₂ is formed at a low temperature, and the polycrystalline InP film 7 thereunder is formed through this insulating film.
The polycrystalline InP film 7 is doped with a predetermined impurity to form a source / drain region 8 and a predetermined gate electrode 9 is formed to form a device such as a MIS transistor. To do. After that, an insulating film such as SiO ₂ is formed to a predetermined thickness to form the second layer 3.

In the semiconductor device thus manufactured, polycrystalline InP having a large carrier mobility of about 500 to 1000 cm ² / V · S is used as a material for a device such as a MIS transistor located in the upper layer of the multilayer structure. Therefore, a device capable of high-speed operation can be provided. Further, when Si is used as the device material, a complicated and difficult manufacturing technique such as forming polycrystalline Si into single crystal Si in order to increase the carrier mobility is required. Since polycrystalline InP having a large carrier mobility is used, it is not necessary to convert it to a single crystal, so that a device that can operate at high speed can be manufactured very easily.

Furthermore, polycrystalline InP can be formed at a low temperature, and the material of the electrode wiring in the lower layer can be a metal such as Al. When the lower layer electrode wiring is formed of, for example, Al, the specific resistance of the electrode wiring can be reduced by about one digit as compared with the conventional one, so that the conventional problem that the device characteristics are deteriorated by the electrode wiring is improved. You can

As a result, it becomes possible to realize a practical three-dimensional IC capable of high-speed operation. In addition, in the above-described embodiment, the multi-layered structure including the two layers of the first layer 2 and the second layer 3 has been described as an example, but various layers are formed above the second layer 3 to make a more complicated structure. 3D IC with functions
Can be realized. Also in this case, by using polycrystalline InP for the device material of the second layer 3 or higher layers, a practical three-dimensional IC capable of high-speed operation can be provided in the same manner as described above. Further, as a device material, in addition to polycrystalline InP, 3-5 having a large mobility is used.
It is also possible to use a group compound, for example GaAs.
However, in a GaAs MIS transistor, it is difficult to form an n-type inversion layer. Therefore, when forming an n-channel type MIS transistor as a device, it is preferable to use InP, which easily forms an n-type inversion layer, as a device material. .

[0020]

As described above, according to the semiconductor device of the present invention, polycrystalline InP having a high mobility is used as the device material of each layer of the multilayer structure, and Al having a low specific resistance is used for the electrode wiring. Since these materials are used, a practical three-dimensional IC capable of high-speed operation can be realized.

Further, since the device capable of high-speed operation as described above is manufactured by using polycrystalline InP, it is not necessary to make it into a single crystal like Si, and thus a device capable of high-speed operation is extremely high. It can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a configuration diagram of an example of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 First layer 3 Second layer 4 Source and drain region 5 Electrode wiring 6 Gate electrode 7 Polycrystalline InP film 8 Source and drain region 9 Gate electrode

Claims (3)

[Claims] 1. In a semiconductor device having a multi-layer structure, polycrystalline InP is used as a device material of each layer, and a material having a melting point higher than the temperature at which polycrystalline InP is formed is used for electrode wiring. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein the electrode wiring is formed of a material containing at least Al. 3. A method of manufacturing a semiconductor device having a multi-layer structure, wherein a multi-layer InP material is used to form a multi-layer device, and an electrode wiring is formed of a material containing at least Al. Method for manufacturing semiconductor device.