JPH0256965A - Semiconductor device - Google Patents

Abstract

PURPOSE:To ensure large capacitor capacitance without thinning a capacitor insulating film by making the thickness of an electrode arranged to a lower section larger than the radius of a connecting hole electrically connecting the electrode and a conductive film or a diffusion layer in the lower layer of the electrode. CONSTITUTION:A MOS transistor, a data line 8, an inter-layer insulating film 9, and a storage-electrode connecting hole 15 are formed onto a P-type silicon substrate 1. An silicon film is shaped, and the silicon film is worked through plasma etching and used as a storage electrode 10, and a capacitor insulating film 11 and a plate electrode 12 are formed and employed as a capacitor. The thickness of the electrode 10 disposed to a lower section in the two electrodes is made larger than the radius of the connecting hole 15 electrically bonding the electrode 10 and the conductive film or diffusion layer 2, 5 of the lower layer of the electrode 10 at that time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a memory including a capacitor and at least one transistor.

[Conventional technology]

Semiconductor devices 5 For example, high integration of read-and-write memory devices (hereinafter referred to as DRAMs) that require memory retention operations is being achieved at a remarkable speed.Currently, the mainstream is 256-bit products, but Mass production of 1Mbit products has also begun. Such high integration has been achieved mainly by miniaturizing element dimensions. At that time, the area of the capacitor has also been reduced by about 40% with each generation, almost in proportion to the area of the memory cell. As a result, the capacitor capacity decreases and the signal-to-noise ratio (S/N ratio) decreases.

Adverse effects such as signal inversion (so-called soft errors) due to alpha rays have become apparent, and this has become a major problem in terms of reliability. For this reason, capacitor insulating films have been made thinner for the purpose of increasing capacitor capacitance. The thickness is already 10 nm in terms of thermal oxide film for a 1M bit product, and it is said that a 4M bit product of the next generation will require an insulating film with a thickness of 4 to 6 nm. Thermal oxide film conversion means converting so that it is the same as the capacitance of a silicon oxide film capacitor due to thermal oxidation. However, when the insulating film becomes thin like this, a problem arises in that a tunnel current flows between the electrodes of the capacitor, causing the accumulated charge to disappear. In this regard, see, for example, Solid State Electronics, Vol. 10 (1967), pp. 865-87.
Page 3 (Solid-5tate Electronic
s.

vol, 10. pp865-873 (1967))
It is discussed in

In order to solve this problem, a capacitor having a laminated structure was proposed and discussed in Japanese Patent Publication No. 55258/1983. Since a stacked capacitor is formed so that a portion thereof overlaps the top of a MOS transistor, the area of the capacitor can be increased. Therefore, even if an insulating film of 10na+ is used in terms of thermal oxide film,
It becomes possible to secure the capacity necessary for a 4M bit DRAM, and it is possible to prevent the problem of loss of accumulated charge.

[Problem to be solved by the invention]

The above-mentioned conventional technology requires further high integration, for example 1.
No consideration was given to realizing a 6M bit product. When the insulating film has a thickness of about 5nrQ in terms of thermal oxide film, the loss of charge due to tunnel current becomes a problem again. Although there are reports that a 5 nm insulating film can be put into practical use, it is extremely difficult to make the film even thinner. Therefore, there is a concern that higher integration will lead to a decrease in manufacturing yield due to variations in film thickness, etc., and there is a problem that it is difficult to further increase integration.

The object of the present invention is to
An object of the present invention is to provide a semiconductor device that can ensure a large capacitor capacity.

[Means to solve the problem]

The above object is to (1) provide a semiconductor device having a memory cell consisting of a capacitor having two electrodes disposed with an insulating film interposed therebetween and at least one transistor; A semiconductor device, characterized in that the thickness of the electrode is larger than the radius of a connection hole that electrically connects the electrode to a conductive film or a diffusion layer below the electrode;
(2) In a semiconductor device having a memory cell consisting of a capacitor having two electrodes arranged through an insulating film and at least one transistor, the capacitance on the side wall of at least one of the two electrodes is (3) A semiconductor device having a memory cell including a capacitor having two electrodes arranged with an insulating film interposed therebetween and at least one transistor. A value obtained by multiplying the thickness of the upper electrode of the two electrodes is larger than the distance between the lower electrode and the electrode of another adjacent memory cell. This is achieved by a semiconductor device.

In the present invention, when comparing the capacitance on the side wall of the electrode with the capacitance on the plane, the recessed portion on the plane is included in the plane.

Further, the present invention can take the following configuration. In other words, the minimum dimension of the lower electrode of the electrodes that make up the capacitor is smaller than the dimensions of any of the other components and other elements, and the lower electrode of the electrodes that make up the capacitor is formed with a groove. Among the electrodes constituting the capacitor, the thickness of the lower electrode is made larger than its minimum dimension. Among the electrodes constituting the capacitor, the lower electrode and the underlying conductive film or diffusion layer are electrically At least a portion of the contact hole connected to the capacitor is not covered by the electrode, and the contact hole that electrically connects the lower electrode of the electrodes forming the capacitor and the lower conductive film or diffusion layer is filled. The material and the material of the above electrode are made of different materials, and the capacitor insulating film is
A thermal nitride film formed by heat treatment in an atmosphere containing the nitrogen element, and a silicon nitride film formed by a vapor phase growth method.

At least a portion thereof includes an oxide film formed by thermal oxidation.

Further, it is preferable that at least one of the two electrodes of the semiconductor device of the present invention is an electrode formed by forming a silicon film while performing doping. Moreover, this silicon film can be formed at 560° C. or higher at 400° C. or higher using a reactive gas containing at least part of disilane or trisilane.
It is preferable to form at a temperature of 0.degree. C. or less.

Further, in manufacturing the semiconductor device of the present invention, it is preferable that the formation of the lower electrode of the two electrodes and the subsequent manufacturing steps are performed at a temperature of 850° C. or lower,
When processing the above lower electrode, the silicon substrate is
It is preferable to cool to 0°C or higher and 0°C or lower. Also,
The processing of the lower electrode is preferably carried out by forming side walls in a self-aligned manner on an etching mask.Furthermore, it is preferable to grow a conductive film selectively within the connection hole or to form a conductive film over the entire surface of the substrate. After formation, it is preferable to selectively form a conductive film within the contact hole by etching.

[Effect]

Until now, it has been believed that the capacitor area of a DRAM decreases approximately in proportion to the memory cell area. by the way,
In a stacked capacitor, it is known that the side surfaces of the storage electrode also contribute to the capacitance. Therefore, the capacitance of the capacitor is not necessarily simply proportional to the memory cell area.Based on this recognition, the knowledge obtained as a result of quantitatively examining the capacitance when miniaturized is the basis of the present invention. This is an opportunity. This will be explained in detail below.

Conventionally, when designing a memory cell, it was common to optimize it based on the experience of a specific processing technology, and if the underlying processing technology was different, the design had to be redone. However, in the present invention, based on the outlook for microfabrication technology with a minimum dimension of 0.5 μm and beyond, the precision of mask alignment is assumed to be 172 of the minimum dimension U.
When the layout was performed using U as a unit, it was found that the capacitance of the capacitor could be predicted with considerably high accuracy. FIG. 3 shows a planar layout of a conventional multilayer capacitor designed in this manner. From the figure, the surface area Sc of the storage electrode is approximated by the following equation.

5c=5.25*u2+10 rights a*u”
■α=d/u ■Here, d is the thickness of the storage electrode. Therefore, the capacitance Cs of the capacitor is expressed by a linear equation.

Cs= Sc umbrella E OX ” E 6 / d OX
■In the above equation, εox is the relative dielectric constant of the silicon oxide film, ε. is the permittivity of vacuum (8,854X 10
-''F/cm), dox is the equivalent thickness of the silicon oxide film of the capacitor insulating film.

Figure 4 shows the relationship between capacitor capacity and minimum processing size.
The results calculated using the above formula are shown. Here d. x =
5 nm. Ta. In addition, the conventional limit of d≦0.3
The results are shown for μm and α≦172.

This is due to the following circumstances.

(1) If the capacitor has a large step difference, short circuits are likely to occur between wiring lines when data lines are subsequently formed.

(2) A large step has already occurred before the storage electrode is formed;
In order to process the storage electrode on such a high level difference without etching residue, it is necessary to make the electrode thin.

(3) Polycrystalline silicon has so far been used for storage electrodes. In order to impart conductivity to the polycrystalline silicon, it is necessary to perform doping by diffusion or ion implantation after film formation.

At that time, if the film is thick, it is difficult to dope the entire film. Note that due to this doping restriction, the thickness of the storage electrode is approximately half of the minimum processing dimension (α = d / u
There is also an upper limit of ≦172). This is due to the following reasons. The size of the connection hole that electrically connects the storage electrode to the diffusion layer of the MOS transistor is often formed to be equal to or slightly larger than the minimum processing dimension.

At this time, if polycrystalline silicon is formed to be thicker than the radius of the connection hole, the inside of the connection hole will be completely filled. This is because, as a result, it becomes extremely difficult to dope into the connection hole.

According to FIG. 4, the 0.3 pm process (64M
(RAM), even if it is a stacked capacitor.

It can be seen that only a capacitance of 10 fF or less can be obtained.

On the other hand, 64MDRAM requires a capacity of 20 to 30 fF. As described above, with the conventional technology, it is not possible to realize a 64M DRAM using a stacked capacitor.

In contrast, in the present invention, the above (1) is performed as follows.
) to (3) have been solved, thereby making it possible to increase the thickness of the storage electrode. First, problem (1) above was solved by forming the storage electrode after forming the data line. Problem (2) was solved by optimizing the processing conditions for the storage electrode and achieving both selectivity to the underlying silicon oxide film and processing anisotropy. that time,
It is particularly effective to maintain the silicon substrate at 0° C. or lower. Regarding the problem (3), we can solve the problem by developing a technology to form a silicon thin film while performing doping.
I solved this.

FIG. 5 shows a planar layout according to the present invention. According to this layout, 5c = 6 fists u" + 11 umbrellas (!Iu"). Figure 6 shows the relationship between capacitor capacitance and minimum processing size in the present invention. In the figure, the broken line indicates the storage electrode This shows a case where the area of the plane portion of No. 10 is equal to the area of the side wall, and in the region above the broken line, the area of the side wall is larger.

The figure also shows the conventional results for d≦0.3μ-, but the capacitance for the same U and d values is larger in this figure than in Figure 4. .

This is because when forming the storage electrode 10, the data line 8 has already been formed and the connection hole 23 for the data line shown in FIG. 3 does not exist, so the storage electrode 10 is enlarged to the processing limit. This is because it can be formed.

FIG. 7 shows a planar layout in which the present invention is even more effective. In this layout, when processing the storage electrode 10, the side walls are formed on the etching mask.
The distance between adjacent storage electrodes is less than or equal to the minimum processing dimension. The surface area Sc of the accumulated charge pito is expressed by the following equation.

5e=9 Umbrella u"+13$ a Umbrella u2 ■8th
The figure shows the relationship between capacitor capacitance and minimum processing size based on the same layout. In the same figure.

Similar to FIG. 6, the broken line indicates the case where the area of the planar portion of the storage electrode is equal to the area of the side wall.

From FIG. 8, if the thickness d of the storage electrode 10 is set to 0.5 μm or more, a capacitor capacity of 15 fF or more can be secured even in a 0.3 μm process (u = 3), and 64 MDRA
It turns out that M can be realized. In addition, in the 0.5 μm process, the capacitor capacitance is 40 fF, and conversely, even if the thickness of the capacitor insulating film (silicon oxide film equivalent thickness) is increased from 5 nm to 7 nm, a capacitance of 30 fF or more is secured. It can be seen that it is easy to realize a 16MDRAM.

In both Fig. 6 and Fig. 8, when the area of the side wall is larger than the flat area (area above the broken line), the storage electrode is miniaturized while keeping the thickness constant (minimum processing dimension U).
When the capacitance is reduced), the capacitance decreases more slowly (the slope of the curve becomes smaller). Such an area has been made possible for the first time by the present invention, and is also an area where the present invention is effective.

〔Example〕

FIG. 1 shows a cross-sectional structural diagram of a DRAM equipped with a multilayer capacitor, which is a first embodiment of the present invention.
On top, a MoS transistor, a data line 8, an interlayer insulating film 9
．． Form up to the storage electrode connection hole 15. Next, a silicon film is formed to a thickness of 0.8 μm by doping phosphorus to a concentration of IXIO "am-" by low pressure chemical vapor deposition. After forming an etching mask using a conventional method, the silicon film is processed by plasma etching.
It was used as a storage electrode IO. In the processing, a μ wave excitation type plasma etching apparatus was used, SFs gas was used as a reaction gas, and the temperature of the silicon substrate 1 was maintained at -110°C.

As a result, although long over-etching was performed to remove the silicon film on the side walls of the step, there was only slight scraping of the lower glabella insulating film 9 and side etching of the storage electrode 10.

Then, a capacitor insulating film 11 and a plate electrode 12 were formed to form a capacitor. Thereafter, the wiring layer 14 and the like were formed again by a known method to complete the DRAM.

In this embodiment, a processing technique with a minimum dimension of 0.6 .mu.m is used, and the area of the memory cell is 4.4 .mu.m.sup.2. In addition, the capacitance of the capacitor is 47 fF, and the DRAM
This is a sufficient value. It goes without saying that if the storage electrode 10 is made thicker, the capacitor capacity increases), but the upper limit is 5 μm. This is due to the following reasons. The μ wave excitation type plasma etching device has a storage electrode 1
Although the selectivity ratio between the silicon film forming the line 0 and the silicon oxide film forming the glabellar insulating film 9 is large, the value of the ratio is about 100. Therefore, the amount of abrasion of the interlayer insulating film 9 when 100% overetching is performed is 50%.
If nanometers are allowed, the maximum thickness of the silicon film that can be processed is 5 μm. In addition, in this example, -
Although processing was performed at 110° C., the anisotropy will be further improved if the temperature is lowered. However, since it is almost saturated at -150℃, it can be cooled relatively easily at -200℃.
There is no need for further cooling beyond this point.

Below, points to be kept in mind when manufacturing the nine embodiments will be described. First, in the capacitor of the present invention, the contribution from the side walls of the storage electrode 10 is extremely large in terms of capacitance, and it is important to ensure the reliability of the capacitor insulating film 11 there. This is due to the following reasons. Storage electrode 10
contains a high concentration of impurities and is polycrystalline due to the capacitor insulating film formation process or prior heat treatment, so not only are there many grain boundaries, but the sidewalls are
There is damage and contamination due to plasma etching.

Therefore, the thermal oxidation method using a normal diffusion furnace is required to form an insulating film with excellent dielectric strength and long-term reliability. Therefore, in the present invention, the capacitor insulating film 1
1 was formed as follows. After forming the storage electrode 10, first, it was heated at 850° C. in an NH atmosphere of 1 atm.
By performing heat treatment for 0 minutes, a thin thermal nitride film is formed. Thereafter, a 3 nm silicon nitride film is formed by low pressure chemical vapor deposition, and a silicon oxide film is formed on the surface of the silicon nitride film by steam oxidation at 850°C, thereby forming a capacitor insulating film. Complete. The thickness of the insulating film in terms of oxide film determined from capacitance measurement was 5 nm. If the capacitor insulating film is formed in this way, various problems that occur in the case of a single layer of thermal oxide film, such as a decrease in film thickness controllability due to accelerated oxidation due to phosphorus in the polycrystalline silicon film, and phosphorus oxidation It is possible to prevent deterioration of the film quality due to incorporation into the film, and the effects of the present invention can be further exhibited. Note that the silicon nitride film and silicon oxide film have various thicknesses (including those that are not subjected to the final thermal oxidation), 7a, O, film, AQ, O, film, or a stacked layer containing these. Good results were also obtained for the membrane. Furthermore, a thermal nitride film or a thermal oxide film formed in a short time using a lamp also had excellent reliability.

Next, a method for forming electrodes constituting a capacitor will be explained. The silicon films constituting these electrodes were formed at a temperature of 525° C. using a reaction gas containing disilane (Si, H, ) and phosphine (PH3) as main components. The characteristics of these silicon films formed as storage electrodes and plate electrodes are that they are almost amorphous in the film formation state and exhibit almost no conductivity, but exhibit sufficient conductivity when annealed at 650° C. or higher. Therefore, for the storage electrode, sufficient conductivity is already obtained in the process of forming the capacitor insulating film, and for the plate electrode, it is sufficient to perform heat treatment at 650° C. or higher in any step after film formation. As in this example, when the data line is formed first and it is necessary to reduce the temperature of the process after forming the data line as much as possible in order to miniaturize the device, such amorphous silicon is used. Forming a film is extremely effective.

In particular, the effect is even greater when a substantial low-temperature technique, such as a low-temperature film formation technique or a short-time heat treatment using a lamp, is used to form the capacitor. Note that in order to make the formed silicon film amorphous, it is more effective to lower the formation temperature. The problem with this is that the film grows slowly. this is,
Trisilane (sia
Hs). However, even in that case, the practical lower limit of the formation temperature is 400°C.

FIG. 2 is a schematic cross-sectional view of a DRAM which is a second embodiment of the present invention. In this embodiment, the etching mask used when processing the storage electrode 10 in the first embodiment is
A method for forming zero sidewalls is disclosed in Japanese Patent Laid-Open No. 62-25, which differs in that the gap between adjacent storage electrodes is kept below the minimum processing dimension by forming sidewalls in a self-aligned manner.
9445. The distance between the storage electrodes after processing was 0.3 μm. As the gap between the storage electrodes becomes smaller as described above, it becomes a problem how to perform doping when forming the plate electrode 12 after forming the capacitor insulating film. This is because the gap is completely filled with the plate electrode. However, in this example, the silicon film is formed while being doped even in the plate electrode, so there is no problem. A DRAM was completed in the same manner as in the first example except for the above. In this embodiment, the area of the memory cell is 4.
The capacitance of the capacitor is increased to 65 fF although it is 4 μl 112, which is the same as the first example.

This is because, as described above, the planar area of the storage electrode increases and the area of the sidewalls also increases.

FIG. 9 shows a planar layout of a third embodiment of the present invention, and a method for creating it will be described below. After forming the storage electrode 10 in the same manner as in the second embodiment, an etching mask having an opening at a position corresponding to the groove 27 is formed, and the storage electrode 10 is etched again. At this time, the etching was completed before the silicon film constituting the W type electrode was used up.

The cross section of the storage electrode at the position indicated by xy is the 10th
Schematically shown in the figure. Here, the influence of the level difference in the base is omitted. Thereafter, in the same manner as in the second embodiment, a DRAM was completed through the steps after forming the capacitor insulating film. The capacitor capacity was 79 fF, which was 1.7 times that of the first example.

FIG. 11 shows a planar layout of a fourth embodiment of the present invention. The method for creating it will be explained below. After forming a silicon film to serve as a storage electrode in the same manner as in the first example, an etching mask was formed using an electron beam lithography system. The resolution of this electron beam lithography apparatus was 0.2 μm, and the pattern shown by diagonal lines in FIG. 11 could be formed almost faithfully. Thereafter, in the same manner as in the second embodiment, the steps after processing the silicon film were performed to complete a DRAM. The capacitor capacity is 74fF, which is 1.6f in the first embodiment.
It's double.

FIG. 12 shows a planar layout of a fifth embodiment of the present invention. The method for creating it will be explained below. After forming up to the storage electrode connection hole 15 in the same manner as in the first embodiment, tungsten is selectively grown in the connection hole using chemical vapor deposition to fill the connection hole. Thereafter, in the same manner as in the fourth embodiment, a DRAM was completed through the steps after forming the silicon film constituting the storage electrode. In this embodiment, the inside of the connection hole is filled with a material (tungsten) that is rarely etched when the silicon film constituting the storage electrode 10 is processed.

Therefore, as shown in FIG.
There is no problem even if 5 is exposed.As a result, it is possible to create a layout in which the side wall of the storage electrode is lengthened as shown in the same figure.
The effect of increasing the thickness of the storage electrode 10, which is the gist of the present invention, could be fully exhibited. When the capacitor capacitance was measured, it was 89 fF, which was the same as that of 2 of the first embodiment.
Almost twice the capacity was obtained. In order to fill the connection hole with tungsten, instead of selective growth, tungsten is formed on the entire surface by chemical vapor deposition, and then the entire surface is etched to remove the tungsten on the flat surface to connect the storage electrode. The present invention was also effective when tungsten was left only in the holes 15. Further, a material other than tungsten, such as molybdenum, tantalum, a silicon compound thereof, or a laminated film of these materials, may be used in the connection hole.

〔Effect of the invention〕

As described above, according to the present invention, a capacitor with a large capacity can be formed without making the capacitor insulating film thinner, so that the degree of integration of LSIs, especially DRAMs, is greatly improved.

[Brief explanation of the drawing]

1 and 2 are cross-sectional schematic diagrams showing an embodiment of the present invention, FIG. 3 is a conventional layout diagram, FIG. 5, FIG. 7, FIG. 9,
11 and 12 are layout diagrams of the present invention, FIG. 4 is a diagram showing calculation results regarding conventional capacitor capacitance, and FIG.
8 are diagrams showing calculation results regarding the capacitance of a capacitor according to the present invention, and FIG. 10 is a sectional view showing a part of an embodiment of the present invention. 1... Silicon substrate 2... Element isolation insulating film 3
．． 4... Diffusion layer 5... Gate oxide film 6...
・Word line 7.9.13...Interlayer insulating film 8
...Data line 10...Storage electrode 11...
・Capacitor insulating film 12...Plate electrode 14...
・AQ wiring 15...Storage electrode connection hole 23・
...Data line connection hole 27...Patent attorney representing Mizo
Junnosuke Nakamura Diagram Kaname J. Karoe, Seven Umu Ki No. 6 Diagram 7 Half-ho 770 Nisunte Gyo u/p□ Figure 8 Figure 11 Figure 12

Claims (1)

[Claims] 1. In a semiconductor device having a memory cell including a capacitor having two electrodes arranged through an insulating film and at least one transistor, of the two electrodes,
A semiconductor device characterized in that the thickness of an electrode disposed below is larger than the radius of a connection hole that electrically connects the electrode and a conductive film or a diffusion layer below the electrode. 2. The semiconductor device according to claim 1, wherein the thickness of the electrode arranged below is 0.4 μm or more and 5 μm or less. 3. The semiconductor device according to claim 1, wherein at least a part of the electrode arranged below is arranged above the data line. 4. In a semiconductor device having a memory cell including a capacitor having two electrodes arranged through an insulating film and at least one transistor, the capacitance on the side wall of at least one of the two electrodes is A semiconductor device characterized by having a capacitance larger than that in a plane. 5. In a semiconductor device having a memory cell consisting of a capacitor having two electrodes arranged through an insulating film and at least one transistor, of the two electrodes,
A semiconductor device characterized in that a value obtained by doubling the thickness of an electrode placed above is greater than a distance between an electrode placed below and an electrode of another adjacent memory cell.