JPH0574955A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for filling a conductor such as a tungsten film in contact holes having different depths and opened in a flattened insulating film without excess and insufficiency. CONSTITUTION:A method for manufacturing a semiconductor device comprises the steps of forming a flattened insulating film 8, opening the deepest contact hole 10, filling the contact hole 10 with a conductor such as a tungsten film 12 to a depth of a contact hole 14 to be formed next to the deepest, opening the contact hole 14, and filling the holes 10, 14 with the conductor such as tungsten 16. The same steps as these steps are repeated in the degree corresponding to the difference of the holes. When the step of opening the shallowest contact hole is finished, the step of filling metal in all the contact holes so as to become substantially the same surface or uneven state on the surface of the film 8 is conducted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a contact opening and a conductor in the contact opening.

[0002]

2. Description of the Related Art In recent years, due to high integration of MOS ICs,
The size of the contact opening and the wiring width have been reduced. Along with this, reliability of wiring, for example, disconnection of aluminum wiring in the contact step portion becomes a problem.

9A to 9C are cross-sectional views of a semiconductor device shown in the order of steps for explaining an example of a conventional method for manufacturing a semiconductor device.

As shown in FIG. 9A, an interlayer insulating film 53 is formed on a semiconductor substrate 52 on which an element region 51 having electrodes and wirings of a semiconductor element is formed, and the element region 51 is formed by photolithography. A contact opening 54 is formed in the upper interlayer insulating film 53.

Next, as shown in FIG. 9B, an aluminum film 55 for wiring is deposited by sputtering.

Next, as shown in FIG. 9C, the aluminum film 55 is patterned to form an aluminum wiring to form a semiconductor device. However, the above-described conventional method for manufacturing a semiconductor device improves the degree of integration of ICs,
When the diameter of the opening for contact becomes small and the aspect ratio (depth / diameter) of the opening becomes large, there is a drawback that the aluminum wiring is easily broken at the edge of the opening 54. As a means for solving this, there is known a method of filling a contact opening having a large aspect ratio by selectively growing a metal film, particularly a tungsten film.

This will be described with reference to FIGS. 10 (a) and 10 (b).

As shown in FIG. 10A, the element region 61
A contact opening portion 64 is formed in the upper interlayer insulating film 63 by anisotropic etching, and then a tungsten film 66 is formed on the semiconductor substrate exposed in the contact opening portion.
Are selectively grown to fill the contact opening portion 64 with the tungsten film 66. Next, as shown in FIG. 10B, an aluminum film 67 is deposited by the sputtering method and patterned to form an aluminum wiring.
If this method is used, the upper surface in the contact opening portion 64 becomes nearly flat, and it is possible to prevent disconnection of the aluminum wiring in the step portion at the edge of the contact opening portion 64.

[0009]

The conventional manufacturing method described above has a drawback in that it is not possible to simultaneously satisfactorily fill the steps of the contact opening portions having different depths. This will be described with reference to FIGS. 11 (a) and 11 (b).

FIGS. 11A and 11B are sectional views showing a part of the manufacturing process of a semiconductor device having contact openings having different depths. As shown in FIG. 11A, a field insulating film 72, a gate insulating film 73, and a diffusion layer 74 are formed on the semiconductor substrate 71. A polycrystalline silicon layer 75 is formed on the field insulating film 72.
A flattened interlayer insulating film 76 is formed on them, and contact openings 77 and 78 reaching the polycrystalline silicon layer 75 or the diffusion layer 74 are formed, respectively. Here, as is clear from the drawings, the contact hole portion 77 and the contact hole portion 78 have different step depths of the contact hole portion. In an actual semiconductor device, there are many steps of such contact opening portions having different depths. Here, when the tungsten film 79 is selectively grown to the surface of the interlayer insulating film 76 in the contact opening portion 77, the contact hole 77 is completely filled, but the contact opening portion 78 is only partially filled. Next, when the aluminum film 80 for wiring is formed in this state, as shown in FIG.
As shown in FIG. 0 (b), the aluminum film 80 on the surface of the interlayer insulating film 76 and the tungsten film 79 cannot be connected at the contact opening 78, and the aluminum film 80 is discontinuous. As a method for preventing aluminum wiring step disconnection, it is known to round the edge of the contact opening portion as shown in FIG. 12 by isotropic etching. Then, at the shallow portion of the contact step, the contact opening portion is formed. However, there is a problem in that the size of the arrow spreads laterally, and the edge of the arrow sticks out beyond a predetermined portion. As shown by the dotted line in FIG. 12, if the amount of isotropic etching is suppressed so that the contact hole is not spread even in the shallow portion of the contact step, a high vertical step remains in the deep portion of the contact step. Since the tungsten film cannot be sufficiently filled, it is difficult to obtain the coverage of the aluminum wiring. Hereinafter, specific numerical values will be described.

The insulating film thickness on polycrystalline silicon is about 0.6 μm.
m, about 1.6 μm on the diffusion layer, the depth that can be opened by isotropic etching is about 0.6 μm due to the above-mentioned restriction.
m, a vertical step of about 1.0 μm remains on the diffusion layer. Of this, about 0.4 μm is filled with tungsten, but a vertical step of about 0.6 μm still remains. When the contact size is about 0.6 μm to 0.8 μm, the aspect ratio is close to 1. When aluminum wiring having a thickness of about 0.5 μm is formed in this portion, the coverage is expected to be 10% or less.

As described above, according to the conventional manufacturing method, it is difficult to obtain good aluminum wiring coverage at each contact portion for contact steps having different depths.

[0013]

According to the manufacturing method of the present invention, a step of forming a region, a step of forming a flattened insulating film on a semiconductor substrate, and a step of forming a depth of reaching the element region in the insulating film are performed. A step of forming substantially the same first opening group, a step of selectively growing the first conductor material in the first opening group, and a depth of reaching the wiring region in the first insulating film are substantially the same. The method has a step of forming equal second opening portions and a step of embedding the first and second opening groups by selective growth of the second conductor material.

[0014]

Embodiment 1 Next, the present invention will be described with reference to the drawings.

Here, as an example of forming contact steps having different depths on the same semiconductor device, a contact opening portion on the diffusion layer and a contact opening portion on the polycrystalline silicon layer on the field insulating film are formed. Consider a case in which the two are formed on the same semiconductor device.

1 (a) (b), 2 (c) (d), 3 (e) (f), and 4 (g) (h) are for explaining the first embodiment of the present invention. FIG. 3B is a cross-sectional view of the semiconductor device in the order of steps.

First, as shown in FIG. 1A, a part of the semiconductor substrate 1 is formed to a thickness of about 0.
A field insulating film 2 of 6 μm is selectively formed, and then a gate insulating film 3 is formed.

Next, as shown in FIG. 1B, the well-known C
A polycrystalline silicon layer 4 having a thickness of about 4000 angstrom is formed on the field insulating film by the VD technique and the photo-etching method, and an impurity having a conductivity type opposite to that of the substrate is introduced by an ion implantation method to form a diffusion layer 5. Next, as shown in FIG. 2C, an interlayer insulating film, for example, B having a thickness of 2.0 μm is formed on the entire surface.
A PSG film 6 is deposited, and then a photoresist 7 is applied.

Next, as shown in FIG. 2D, dry etching is performed for a proper period of time so that the selection ratios of the photoresist 7 and the BPSG film 6 are substantially equal to each other to form a flattened insulating film 8. At this time, the thickness of the insulating film is, for example, the diffusion layer 5
About 1.5 μm above and about 0.8 μm above polycrystalline silicon 4
Is. In addition to this, as a method for forming a planarized insulating film, there are a method of depositing a TEOS film and a method of using a coating film. Next, as shown in FIG. 3E, a photoresist 9 is applied, and then the diffusion layer 5 is formed by a known PR technique.
An opening pattern is formed at a predetermined position above, and the insulating film 8 is removed by anisotropic etching using the opening pattern as a mask to reach the diffusion layer 5 with the first contact opening portions 10 and 11.
To form. The depth of the first contact opening is about 1.
It is 5 μm.

Next, as shown in FIG. 3 (f), the first conductor material such as a tungsten film is formed on the surface of the diffusion layer 5 exposed in the contact openings 10 and 11 after the photoresist 9 is removed. 12 is selectively grown up to the height of the surface of the polycrystalline silicon layer 4 (position A in the figure), that is, about 0.7 μm, and the contact openings 10 and 11 are partially buried.

Next, as shown in FIG. 4 (g), a photoresist 13 is applied, and then an opening pattern is formed at a predetermined position on the polycrystalline silicon layer 4 by a well-known PR technique, and this is used as a mask for insulation. The film 8 is removed by anisotropic etching to form second contact openings 14 and 15 reaching the polycrystalline silicon 4. The depth of the second contact opening is about 0.8 μm. Next, as shown in FIG. 4 (h), after removing the photoresist 13, a second conductor material, for example, a tungsten film 16 is formed on the exposed surface of the polycrystalline silicon layer 4 and the exposed surface of the tungsten film 12. The depth of the second contact hole, that is, 0.8μ
By selectively growing about m, the second contact opening portions 14 and 15 and the first contact opening portions 10 and 11 which have been partially embedded previously are filled with a conductor material substantially without excess or deficiency. .. As is clear from the drawing, the difference in height between the surface of the polycrystalline silicon layer 4 and the surface of the insulating film 8 is substantially equal to the difference in height between the surface of the tungsten film 16 and the surface of the insulating film 8. Both contact openings can be filled in properly.

In this way, all the contact openings having different depths on the semiconductor substrate can be completely filled with the conductor material.

Next, the aluminum wiring 17 is formed by the well-known PR technique and etching technique. As described above, each contact opening has a tungsten film 1
Since the surface of the insulating film is filled with 2 and 16 without excess or deficiency, almost 100% coverage can be obtained.

[0024]

Second Embodiment A second embodiment of the present invention will be described with reference to the drawings.

Here, as an example of forming contact steps having different depths on the same chip, a contact opening for connecting the second aluminum diffusion layer and a contact opening for connecting the second aluminum and the first aluminum. Consider the case of forming on the same chip.

FIGS. 5A, 5B, 6C, 6D, 7E, 7F and 8G are shown in the order of steps for explaining the second embodiment of the present invention. FIG. 3 is a cross-sectional view of the semiconductor device.

First, as shown in FIG. 5A, a field insulating film 2 having a thickness of about 0.6 μm is formed on the semiconductor substrate 1 by the well-known LOCOS method, and then a gate insulating film 3 is formed to remove ions. By the implantation method, an impurity having a conductivity type opposite to that of the substrate is introduced to form the diffusion layer 5. Next, as shown in FIG. 5B, a flattened interlayer insulating film 18 is formed by the same method as that of the first embodiment, and then an aluminum wiring 17 is formed by using a well-known PR etching technique. To do. Then, a silicon oxide film 19 is grown thereon to a thickness of 1.5 μm by plasma vapor deposition, and subsequently a silica film 20 is formed by spin coating. A photoresist may be used instead of the silica film. Next, as shown in FIG. 6C, dry etching is performed for a proper period of time so that the selection ratios of the silica film and the plasma oxide film are substantially equal to each other to form a flattened insulating film 21 made of a two-layer film. .. The insulating film thickness is, for example, 0.8 μm on the aluminum wiring 17 and about 3 μm on the diffusion layer 5. As another method for forming the insulating film on the aluminum wiring, the silicon oxide film 0.
A method of forming a silica film film of 6 μm and further growing a silicon oxide film of 0.3 μm is also conceivable.
Next, as shown in FIG. 6D, a photoresist 24 is applied, and then a well-known PR technique is used to form an aperture pattern at a predetermined position on the diffusion layer 5, which is used as a mask for planarization. The first contact opening 2 reaching the diffusion layer 5 by removing the insulating film 21 by anisotropic etching.
2, 23 are formed. The depth of the first contact opening is about 3 μm. Next, as shown in FIG. 7E, the tungsten film 12 is formed on the exposed surface of the diffusion layer 5 to the height of the aluminum wiring surface, that is, to the height of B in the figure.
About 2.2 μm is selectively grown. Next, as shown in FIG. 7F, after applying a photoresist 25, an opening pattern is formed on the aluminum wiring 17 by a well-known PR technique, and the insulating film is anisotropically etched using this as a mask. Then, the second contact openings 26 and 27 reaching the surface of the aluminum wiring are formed. The depth of the second contact opening is about 0.8 μm.
Next, as shown in FIG. 8G, after removing the photoresist 25, the aluminum wiring surface exposed at the second contact openings 26 and 27 and the first contact openings 22 and 23 are removed. A second conductor material, such as the second tungsten film 28, is applied to the surface of the tungsten 12 by about 0.8 μm.
m Selectively grown to form contact holes 22, 23, 2
6 and 27 are embedded. As is apparent from the drawing, the difference in height between the surface of the aluminum wiring 17 and the surface of the insulating film 21 in the second contact openings 26, 27 is equal to that in the first contact openings 22, 23. It is almost equal to the difference in height between the surface of the tungsten 12 and the surface of the insulating film 21.
Therefore, all the contact openings can be filled with the tungsten film 12 and the second tungsten film 28 without excess or deficiency. Next, the second aluminum wiring 29 is formed by using the well-known PR technique and etching technique. Similar to the first embodiment, a coverage close to 100% is obtained at each contact opening.

In Examples 1 and 2 described above, to the extent that tungsten does not necessarily grow until the contact hole is completely filled, there is no problem in the step coverage in the contact hole of the aluminum wiring. You may leave the step. For example, contact opening 1.0μ
There may be a step difference of 0.3 μm or less after the filling with respect to m. Further, as a material to be embedded, other than tungsten described in the present embodiment, it is natural from the gist of the present invention that the same effect can be obtained as long as it is a material that can be selectively grown and can be used for a semiconductor device such as molybdenum. is there. Also,
The example in which a plurality of contacts having different depths are divided into two groups, and the first group is filled with the first and second conductor materials and the second group is filled with the second conductor material has been described. It may be divided into the above groups. For example, by embedding the first group with the first, second and third conductor materials, the second group with the second and third conductor materials, and the third group with the third conductor material, For example, the contact opening connecting the first aluminum / diffusion layer, the contact opening connecting the first aluminum / polycrystalline silicon layer, and the contact opening connecting the second aluminum / diffusion layer are the same. It can be embedded on the semiconductor device in the same manner without excess or deficiency.

[0029]

As described above, according to the present invention,
Multiple fine contact openings with different depths can be filled by selective growth of conductor material, and the steps of the contact openings after filling can be formed uniformly, so that the contact openings can be used regardless of the location on the chip. It is possible to perform stable wiring connection with good coverage at the openings, and thus to realize a highly reliable semiconductor device.

[Brief description of drawings]

1 to 4 are cross-sectional views according to a manufacturing process of a first embodiment of the present invention.

5 to 8 are cross-sectional views according to a manufacturing process of a second embodiment of the present invention.

FIG. 9 is a sectional view of an example of a conventional semiconductor device for each manufacturing step.

FIG. 10 is a sectional view of another example of the conventional semiconductor device in each manufacturing process.

11 is a cross-sectional view of each manufacturing process to which the manufacturing process of FIG. 10 cannot be applied.

FIG. 12 is a cross-sectional view of another example of the structure of the conventional semiconductor device.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Field Insulating Film 3 Gate Insulating Film 4 Polycrystalline Silicon Layer 5 Diffusion Layer 6 BPSG Film 7 Photoresist 8 Planarized Insulating Film 9 Photoresist 10 First Contact Opening 11 For First Contact Opening part 12 Tungsten film 13 Photoresist 14, 15 Second contact opening part 16 Tungsten film 17 Aluminum wiring 18 Planarized interlayer insulating film 19 Silicon oxide film 20 Silica film 21 Planarized first insulation Films 22 and 23 First contact opening portion 24 Photoresist 25 Photoresist 26 and 27 Second contact opening portion 28 Second tungsten film 29 Second aluminum wiring 51 and 61 Element region 52 Semiconductor substrate 53 , 63 Inter-layer insulation film 54, 64 Contact opening 55 Aluminum film 66 Tungsten film 67 Aluminum film 71 Semiconductor substrate 72 Field insulating film 73 Gate insulating film 74 Diffusion layer 75 Polycrystalline silicon layer 76 Interlayer insulating film 77, 78 Contact openings 79 Tungsten film 80 Aluminum film

Claims (1)

[Claims] 1. A step of forming a first element formation region,
Forming a second element formation region having an upper surface at a position higher than the upper surface of the first element formation region with respect to the surface of the semiconductor substrate, and covering the first and second element formation regions with a flat surface Forming an insulating film, forming a first contact opening reaching the upper surface of the first element formation region in the insulating film, and forming the first contact opening in the first contact opening. Second step of embedding a conductor to the height of the upper surface of the element formation region, forming a second contact opening reaching the upper surface of the second element formation region in the insulating film, 2. A method of manufacturing a semiconductor device, comprising the step of embedding a conductor in the contact opening portion of 2.