JPH0574819A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To provide a high electron mobility transistor, performance of which is improved. CONSTITUTION:A compound semiconductor device has a compound semiconductor substrate 1, an electron supply layer 4 forming a hetero-junction and an electron transit layer 31 on the compound semiconductor substrate 1, a gate electrode 6 formed onto the electron supply layer 4 and a source electrode 7 and a drain electrode 8 shaped onto the electron supply layer 4 and arranged on both sides of the gate electrode 6. The electron transit layer 31 is composed of a III-V compound semiconductor mixed crystal layer, and the composition of the mixed crystal layer is constituted of a compound semiconductor device, in which band gap energy is reduced toward a hetero-junction surface and a lattice constant is change so as to be separated from the lattice constant of the compound semiconductor substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device, and more particularly to a high electron mobility transistor. High electron mobility transistors (HEMTs) are known to operate at high speeds and are used for high frequency communication in the millimeter wave band as well as in the microwave band, but their performance continues to improve. Has been.

[0002]

2. Description of the Related Art FIG. 11 is a sectional view showing a conventional example of a high electron mobility transistor. 1 is a GaAs substrate, 2a and 2b are buffer layers, 3 is an electron transit layer, 4 is an electron supply layer, and 5 is a contact layer. , 6 is a gate electrode, 7 is a source electrode, and 8 is a drain electrode.

FIG. 12 is an energy band diagram of a high electron mobility transistor. E _C is the conduction band bottom energy, E _V is the valence band top energy, E _g1 is the band gap energy of the electron supply layer, and E _g2 is the electron transit. The band gap energy of the layer, E _F is the Fermi level, ΔE _C is the difference in conduction band bottom energy at the heterojunction interface, and ΔE _V is the difference in valence band top energy at the heterojunction interface.

As a low noise HEMT, there is a HEMT in which an AlGaAs type compound semiconductor layer formed on a GaAs substrate is used as an electron supply layer 4 and an InGaAs type compound semiconductor layer is used as an electron transit layer 3. With such a configuration, it is possible to increase ΔE _C , increase the concentration of the two-dimensional electron gas, and increase the electron velocity, so that high performance can be expected.

By the way, it is known that there is the following relationship between ΔE _C and E _g1 and E _g2 .

[0006]

[Equation 1] ΔE _C = 0.85 × (E _g1 −E _g2 ) If the In composition of the In _x Ga _{1 -x} As system of the electron transit layer 3 is increased, E _g2 is decreased, and as a result, ΔE _C is increased to 2 An increase in the concentration of the dimensional electron gas can be expected.
If the In composition is increased, the electron velocity can be expected to be improved. However, if the In composition is too large, the deviation from the substrate lattice constant becomes large, causing lattice imperfections, so that x = 0.
The limit is about 25.

Further, using an InP substrate, the electron supply layer 4 is an InAlAs compound semiconductor, and the electron transit layer 3 is InG.
The same applies to HEMTs using an aAs-based compound semiconductor.

[0008]

SUMMARY OF THE INVENTION In view of the above problems, the present invention forms an electron transit layer 3 or an electron supply layer 4 or a compound semiconductor layer of both layers so that the composition of each layer changes in a gradient type. An object of the present invention is to provide a compound semiconductor device having a structure in which lattice mismatch is not caused and high performance can be obtained.

[0009]

1 (a) to 1 (c) are sectional views of a high electron mobility transistor of the present invention, in which 1 is a compound semiconductor substrate, 2 is a buffer layer, and 3 is an electron transit layer. , 31
Reference numerals 35 and 35 are electron transit layers having a gradient composition, 4 is an electron supply layer, 43 and 45 are electron supply layers having a gradient composition, 5 is a contact layer, 6 is a gate electrode, 7 is a source electrode, and 8 is a drain electrode.

The above problem is solved by the compound semiconductor substrate 1, the electron supply layer 4 and the electron transit layer 31 on the compound semiconductor substrate 1 which form a heterojunction, and the gate electrode formed on the electron supply layer 4. A compound semiconductor device having a source electrode 7 and a drain electrode 8 formed on the electron supply layer 4 and arranged on both sides of the gate electrode 6,
The electron transit layer 31 is composed of a III-V group compound semiconductor mixed crystal layer, and the composition of the mixed crystal layer is such that the band gap energy becomes smaller toward the heterojunction surface and the lattice constant of the compound semiconductor substrate 1 is smaller. It is solved by a compound semiconductor device changing away from it.

Further, the compound semiconductor substrate 1 and an electron supply layer for forming a heterojunction on the compound semiconductor substrate 1
43 and an electron transit layer 3, a gate electrode 6 formed on the electron supply layer 43, a source electrode 7 and a drain electrode 8 formed on the electron supply layer 43 and arranged on both sides of the gate electrode 6. And the electron supply layer 43 is composed of a III-V group compound semiconductor mixed crystal layer, and the composition of the mixed crystal layer is such that the band gap energy increases toward the heterojunction surface. Solved by a changing compound semiconductor device.

Further, the compound semiconductor substrate 1 and an electron supply layer which forms a heterojunction on the compound semiconductor substrate 1
45 and the electron transit layer 35, the gate electrode 6 formed on the electron supply layer 45, the source electrode 7 and the drain electrode 8 formed on the electron supply layer 45 and arranged on both sides of the gate electrode 6. And the electron transit layer 35 is composed of a first III-V compound semiconductor mixed crystal layer, and the composition of the first III-V compound semiconductor mixed crystal layer is the heterojunction. The band gap energy decreases toward the surface and the lattice constant changes away from that of the compound semiconductor substrate 1, and the electron supply layer 45 is formed into the second II.
A compound semiconductor device comprising an I-V group compound semiconductor mixed crystal layer, wherein the composition of the second III-V group compound semiconductor mixed crystal layer changes so that the band gap energy increases toward the heterojunction surface. Will be solved by.

Further, the compound semiconductor substrate 1 and an electron supply layer which forms a heterojunction on the compound semiconductor substrate 1
46 and the electron transit layer 3, a gate electrode 6 formed on the electron supply layer 46 to form a Schottky junction, and a source electrode formed on the electron supply layer 46 and arranged on both sides of the gate electrode 6. 7 and a drain electrode 8, the electron supply layer 46 is composed of a III-V group compound semiconductor mixed crystal layer, and the composition of the mixed crystal layer is on the heterojunction surface side on the heterojunction surface side. The problem is solved by the compound semiconductor device in which the band gap energy changes toward the Schottky junction surface side toward the Schottky junction surface side.

[0014]

In the present invention, the electron transit layer 31 is composed of a III-V group compound semiconductor mixed crystal layer, and the composition of the mixed crystal layer changes so that the band gap energy decreases toward the heterojunction plane. , Delta E _C near the heterojunction surface is increased to increase the two-dimensional electron gas concentration, and the lattice constant shifts away from the value of the lattice constant of the substrate. It can be prevented from occurring.

The electron supply layer 43 is composed of a III-V group compound semiconductor mixed crystal layer, and the composition of the mixed crystal layer changes so that the band gap energy increases toward the heterojunction surface. By increasing ΔE _C in the vicinity of the bonding surface to increase the two-dimensional electron gas concentration, the performance of the compound semiconductor device can be improved.

The electron transit layer 35 is composed of a first III-V compound semiconductor mixed crystal layer, and the composition of the mixed crystal layer changes so that the band gap energy becomes smaller toward the heterojunction plane. The supply layer 45 is composed of a second III-V group compound semiconductor mixed crystal layer, and the composition of the mixed crystal layer changes so that the band gap energy increases toward the heterojunction surface. The ΔE _C in the vicinity of the heterojunction surface becomes larger than that when only one of the electron supply layers has a graded composition, and the two-dimensional electron gas concentration can be made larger.

The electron supply layer 46 is composed of a III-V group compound semiconductor mixed crystal layer, and the composition of the mixed crystal layer changes so that the band gap energy increases toward the heterojunction surface on the heterojunction surface side. In addition, since the bandgap energy on the Schottky junction surface side increases toward the Schottky junction surface, ΔE _C near the heterojunction surface increases and the height of the Schottky barrier also increases. Therefore, the gate leakage current can also be reduced.

[0018]

EXAMPLE FIGS. 2A to 2D are cross-sectional views in order of the processes, showing a first example. Below, referring to these figures,
An example will be described.

See FIG. 2 (a). GaAs substrate 11 is formed by molecular beam epitaxy (MBE).
I-GaAs layer 21a, i-Al serving as a buffer layer on top
_0.23 Ga _0.77 As layer 21b, 3500Å, 1000Å, respectively
To the thickness of.

Next, i-InGaA which becomes the electron transit layer 31 is formed.
The s layer is grown. First, the temperature of the In source is set to 1000 ° C, and the temperature is gradually raised to 1150 ° C during 150Å. The growth layer begins with i-GaAs and ends with i-In.
It should be _0.45 Ga _0.55 As.

Next, n ⁺ -Al _0.23 which becomes the electron supply layer 41 is formed.
A Ga _0.77 As layer is grown to a thickness of 400 Å, and an n ⁺ -GaAs layer serving as the contact layer 51 is grown to a thickness of 700 Å on it.

Referring to FIG. 2 (b), the thickness of the contact layer 51 is, for example,
A 400 Å AuGe film and an Au film with a thickness of, for example, 4000 Å are continuously formed and patterned to form the source electrode 7,
The drain electrode 8 is formed.

After that, alloying treatment is performed at 450 ° C. See Fig. 2 (c). Opening 9a for applying resist and forming gate electrode.
A resist mask 9 having is formed. The contact layer 5 is removed from the opening 9a by etching with, for example, CCl ₂ F ₂ gas. At this time, some side etching occurs.

See FIG. 2D. With the resist mask 9 left, the entire surface has a thickness of, for example, 20
A Ti film having a thickness of 00 Å and an Al film having a thickness of, for example, 2000 Å are successively deposited, the resist mask 9 is removed, and the gate electrode 6 is formed by lift-off.

The electron transit layer 31 has a graded composition in which the composition gradually changes. 3 (a) and 3 (b) show the transition of the mixed crystal ratio and the transition of the bandgap energy E _g2 in the electron transit layer having the graded composition.

The composition of the electron transit layer is i-GaAs at the interface (P ₁ ) with the buffer layer and i-In _0.45 Ga _0.55 As at the heterojunction surface (P ₂ ), during which In is continuously formed. It has increased.

On the other hand, the band gap energy E _g2 is
It is about 1.4 eV at the P ₁ point and about 0.8 eV at the P ₂ point, and gradually decreases during that period. The lattice constant is G alone
Although aAs is 5.654 Å and In _0.45 Ga _0.55 As is 5.8 Å, when an electron transit layer with a graded composition is formed as described above, the lattice constant changes from the interface with the buffer layer (P ₁ ) to the heterojunction plane. Since the lattice constant of the GaAs substrate gradually departed toward (P ₂ ), no defect due to lattice misalignment was observed near the heterojunction plane (P ₂ ) even if the In composition increased.

In the high electron mobility transistor thus formed, the mutual conductance g _m is 550 mS / mm,
The noise figure was 0.45 at 12 GHz. In contrast, the figure
In the conventional high electron mobility transistor having the structure shown in FIG. 11, the transconductance g _m was 450 mS / mm and the noise figure was 0.60 at 12 GHz.

As described above, by adopting the structure of the present invention, the mutual conductance g _m can be increased and the noise figure can be decreased. Instead of the _{i-In x Ga 1-x} As with _{i-GaSb y} As _1-y as an electron transit layer, the boundary surface between the buffer layer (P ₁₎ from the heterojunction plane (P ₂₎ in over y value Even if the value is gradually increased, the same action and effect can be obtained.

Next, the second embodiment will be described. FIG. 4 is a cross-sectional view showing a second embodiment, which is an example of a high electron mobility transistor having an electron transit layer having a graded composition formed on an InP substrate.

In the figure, 12 is an InP substrate, 22a and 22b are buffer layers, respectively, an i-InP layer having a thickness of 3500Å and a thickness of 1000.
Å is an In _x Al _1-x As layer, 32 is an electron transit layer having a gradient composition with a thickness of 150 Å, i-In _y Ga _1-y As layer, and 42 is an electron supply layer with a thickness of 430 Å n ⁺ -In _x Al _1-x A
s layer, 52 is a contact layer n ⁺ -In _y Ga _1-y A
It is the s layer.

The gate electrode 6, source electrode 7 and drain electrode 8 are the same as in the first embodiment. The manufacturing process is similar to that of the first embodiment. The boundary surface between the composition of the electron transit layer buffer layer (P ₁₎ in _{i-In y Ga 1-y} As (y = 0.53), at the heterojunction plane _{(P 2) i-In y} Ga 1-y As ( y = 1.
0), during which y changes continuously.

On the other hand, the band gap energy E _g2 is
It is 0.73 eV at P ₁ point and 0.35 eV at P ₂ point,
Meanwhile, it is gradually decreasing. Lattice constant is In _y
Ga _1-y As (y = 0.53) is 5.869 Å, In _y Ga _1-y
As (y = 1.0) was 6.058Å, but when the electron transit layer having the above graded composition was formed, no defect due to lattice misfit was observed.

As an electron transit layer having a graded composition, i-
Instead of the In _y Ga _1-y As layer, i-InAs _x P
_1-x can also be used. Next, a third embodiment will be described.

FIG. 5 is a cross-sectional view showing a third embodiment of Ga.
It is an example of a high electron mobility transistor having an electron supply layer of a graded composition formed on an As substrate. In the figure, 13 is Ga
As substrates, 23a and 23b are buffer layers, each having a thickness of 35
I-GaAs layer of 00Å and 1000Å, i-Al _0.23 Ga
_0.77 As layer, 33 is an electron transit layer, i-In with a thickness of 150Å
_0.25 Ga _0.75 As layer, 43 is an electron supply layer having a graded composition of 430 Å, n ⁺ -In _x Ga _{1 -x} P layer, and 53 is an n ⁺ -GaAs layer serving as a contact layer.

The gate electrode 6, the source electrode 7 and the drain electrode 8 are the same as in the first embodiment. The manufacturing process is similar to that of the first embodiment. FIGS. 6A and 6B show transitions of the mixed crystal ratio and the bandgap energy E _g1 in the electron supply layer having the graded composition.

The composition of the electron supply layer was n ⁺ -In _0.70 Ga _0.30 P at the heterojunction surface (P ₂ ) and n ⁺ -In _0.51 Ga _0.49 P at the Schottky junction surface (P ₃ ), with In Is continuously increasing from the Schottky junction surface (P ₃ ) toward the hetero junction surface (P ₂ ).

On the other hand, the band gap energy E _g1 is
It becomes 1.90 eV at the P ₃ point and 2.20 eV at the P ₂ point, during which the Schottky junction surface (P ₃ ) to the hetero junction surface (P ₂ )
Is gradually increasing towards.

The lattice constant of In _0.51 Ga _0.49 P is
5.654Å and In _0.70 Ga _0.30 P are 5.6 Å, and as described above, when an electron supply layer having a graded composition was formed, no defects due to lattice mismatch were observed.

As an electron supply layer having a gradient composition, Ga
On the As substrate, instead of the n ⁺ -InGaP layer, n ⁺ -I
n _y Al _1-y P layer, n ⁺ −GaAs _1-y P _y layer, n ⁺ −
_{In 1-yz Al y Ga z} P layers can also be used.

Next, a fourth embodiment will be described. FIG. 7 is a cross-sectional view showing the fourth embodiment, which is an example of a high electron mobility transistor having an electron supply layer having a graded composition formed on an InP substrate.

In the figure, 14 is an InP substrate, 24a and 24b are buffer layers, each having an i-InP layer thickness of 3500Å and a thickness of 1000.
Å i-In _x Al _1-x As layer, 34 has a thickness of 150 Å
Of the electron transit layer of i-In _y Ga _1-y As layer, and 44 has a thickness of 4
N ⁺ -In _x Al that becomes an electron supply layer with a gradient composition of 30 Å
_1-x As layer, 54 is a contact layer n ⁺ -In _y Ga
_{It is a 1-y} As layer.

The gate electrode 6, the source electrode 7 and the drain electrode 8 are the same as in the first embodiment. The manufacturing process is similar to that of the first embodiment. The composition of the electron supply layer 44 is the heterojunction plane (P
₂ ), n ⁺ -In _0.37 Al _0.63 As, and Schottky junction surface (P ₃ ) n ⁺ -In _0.52 Al _0.48 As, during which the composition changes continuously.

On the other hand, the band gap energy E _g1 is
It becomes 1.55 eV at the P ₃ point and 1.75 eV at the P ₂ point, during which the Schottky junction surface (P ₃ ) to the hetero junction surface (P ₂ )
Is gradually increasing towards.

The lattice constant is In _0.52 Al _0.48 As alone.
Is 5.869Å and In _0.37 Al _0.63 As is 5.82 Å, but as described above, when an electron supply layer having a graded composition is formed, no defects due to lattice misalignment were observed.

It should be noted that n ⁺ − which becomes an electron supply layer having a graded composition
Instead of In _x Al _1-x As, n ⁺ on the InP substrate
_{-In 1-y Ga y P,} n + -InP 1-y Sb y, n + -
It is also possible to use a mixed crystal of _{In 1-yz Al y Ga z} P.

Next, a fifth embodiment will be described. FIG. 8 is a cross-sectional view showing the fifth embodiment, which is an example of a high electron mobility transistor having an electron supply layer having a gradient composition and an electron transit layer having a gradient composition formed on an InP substrate at the same time.

In the figure, reference numeral 15 is an InP substrate, and 25a and 25b are buffer layers, each having an i-InP layer thickness of 3500Å and a thickness of 1000.
Å is an i-InAlAs layer, 35 is an electron transit layer with a gradient composition of 150 Å in thickness, i-In _x Ga _1-x As layer, 45 is an electron supply layer with a gradient composition of 430 Å in thickness n ⁺ − In _y A
l _1-y As layer, 55 is a contact layer n ⁺ -InGa
It is an As layer.

The gate electrode 6, source electrode 7 and drain electrode 8 are the same as in the first embodiment. The manufacturing process is similar to that of the first embodiment. Although the composition of the electron transit layer _{i-In x Ga 1-x} As and the electron supply layer ^{_{n + -In y Al 1-y}} As is continuously changed in each layer, x (boundary surface between the buffer layer) = 0.
53, x (heterojunction plane) = 1.0, y (heterojunction plane) =
0.37, y (Schottky junction surface) = 0.52.

In this way, ΔE _c can be increased to increase the two-dimensional electron gas concentration and prevent the occurrence of defects due to lattice misalignment. By making both the electron supply layer and the electron transit layer a gradient composition, the composition range that can be selected can be widened.

Next, a sixth embodiment will be described. FIG. 9 is a cross-sectional view showing a sixth embodiment, in which the composition of the electron supply layer formed on the InP substrate is directed toward the heterojunction plane (P ₂ ) and the Schottky junction plane (P ₃ ). It is an example of a high electron mobility transistor that is changed by.

In the figure, 16 is an InP substrate, 26a and 26b are buffer layers, each having an i-InP layer thickness of 3500Å and a thickness of 1000.
Å i-In _x Al _1-x As layer, 36 has a thickness of 150 Å
Electron transit layer of i-In _0.47 Ga _0.53 As layer, 46 is thickness
N ⁺ -In _x Al to be an electron supply layer with a graded composition of 430 Å
_1-x As layer, 56 is a contact layer n ⁺ -In _y Ga
_{It is a 1-y} As layer.

The gate electrode 6, the source electrode 7 and the drain electrode 8 are the same as in the first embodiment. The manufacturing process is similar to that of the first embodiment. FIG. 10 is a diagram showing changes in the mixed crystal ratio of the electron supply layer.

The composition of the electron supply layer is n ⁺ -In _y Al _1-y As (y = 0.37) at the heterojunction surface (P ₂ ), and y is changed from there toward the Schottky junction surface (P ₃ ). It is increased, and at the midpoint and (y = 0.52), from there toward the Schottky junction surface (P ₃₎ reduced the y, and the Schottky junction surface _{(P 3) (y = 0.37} ).

When the composition of the electron supply layer is changed in this way, the band gap energy E _g1 of the electron supply layer is changed.
Can be increased, and the Schottky barrier can be increased. That is, n ⁺ -In _y Al _1-y As (y
= 0.52), the Schottky barrier is 0.6 eV,
In ^{_{n + -In y Al 1-y}} As (y = 0.37) becomes 0.9 eV. By increasing the Schottky barrier, the gate leak current can be reduced.

In the embodiment, the boundary surface P with the buffer layer is
_Although the composition of the compound semiconductor layer from ₁ to the heterojunction plane P ₂ and the composition of the compound semiconductor layer from the heterojunction plane P ₂ to the Schottky junction plane P ₃ were continuously changed, they should be changed stepwise. May be.

[0057]

As described above, according to the present invention,
By making the composition of the electron transit layer and / or the electron supply layer a graded composition, it is possible to improve the performance of the high electron mobility transistor.

[Brief description of drawings]

1A to 1C are cross-sectional views of a high electron mobility transistor of the present invention.

2A to 2D are cross-sectional views in order of the processes, showing the first embodiment.

FIG. 3 is a diagram showing a transition of a mixed crystal ratio and E _g2 of an electron transit layer having a graded composition.

FIG. 4 is a sectional view showing a second embodiment.

FIG. 5 is a sectional view showing a third embodiment.

FIG. 6 is a diagram showing a transition of a mixed crystal ratio and E _g1 of an electron supply layer having a graded composition.

FIG. 7 is a sectional view showing a fourth embodiment.

FIG. 8 is a sectional view showing a fifth embodiment.

FIG. 9 is a sectional view showing a sixth embodiment.

FIG. 10 is a diagram showing a transition of a mixed crystal ratio of an electron supply layer.

FIG. 11 is a cross-sectional view showing a conventional example.

FIG. 12 is an energy band diagram of a high electron mobility transistor.

[Explanation of symbols]

1 is a compound semiconductor substrate 2 is a buffer layer 3 is an electron transit layer 4 is an electron supply layer 5 is a contact layer 6 is a gate electrode 7 is a source electrode 8 is a drain electrode 9 is a resist mask 9a is an opening 11, 13 is a compound semiconductor substrate And the GaAs substrates 12, 14, 15 and 16 are compound semiconductor substrates and InP substrates 21a, 21b, 22a, 22b, 23a, 23b, 24a, 24b, 25a, 25b,
26a, 26b are buffer layers 33, 34, 36 are electron transit layers 31, 32, 35 are electron transit layers, and electron transit layers 41, 42 having a graded composition are electron supply layers 43, 44, 45, 46 are electron supply layers The electron supply layers 51 to 56 having a graded composition are contact layers.

Claims (4)

[Claims] 1. A compound semiconductor substrate (1), an electron supply layer (4) and an electron transit layer (31) which form a heterojunction on the compound semiconductor substrate (1), and the electron supply layer (4). ) A gate electrode (6) formed on the source electrode (7) and a drain electrode (8) formed on the electron supply layer (4) and arranged on both sides of the gate electrode (6)
A compound semiconductor device including: the electron transit layer (31) comprising a III-V compound semiconductor mixed crystal layer, and the composition of the mixed crystal layer has a bandgap energy decreasing toward the heterojunction surface. And the lattice constant is changed so as to be separated from that of the compound semiconductor substrate (1). 2. A compound semiconductor substrate (1), an electron supply layer (43) and an electron transit layer (3) which form a heterojunction on the compound semiconductor substrate (1), and the electron supply layer (43). ) And a source electrode (7) and a drain electrode (8) formed on the electron supply layer (43) and arranged on both sides of the gate electrode (6).
A compound semiconductor device including: and the electron supply layer (43) is composed of a III-V compound semiconductor mixed crystal layer, and the composition of the mixed crystal layer has a bandgap energy increasing toward the heterojunction plane. The compound semiconductor device is characterized in that 3. A compound semiconductor substrate (1), an electron supply layer (45) and an electron transit layer (35) which form a heterojunction on the compound semiconductor substrate (1), and the electron supply layer (45). ) And a source electrode (7) and a drain electrode (8) formed on the electron supply layer (45) and disposed on both sides of the gate electrode (6).
Wherein the electron transit layer (35) comprises a first III-V compound semiconductor mixed crystal layer, and the composition of the first III-V compound semiconductor mixed crystal layer is The compound semiconductor substrate having a lattice constant such that the band gap energy becomes smaller toward the heterojunction surface
It changes away from that of (1) and the electron supply layer (45)
Is composed of a second III-V compound semiconductor mixed crystal layer,
3. The compound semiconductor device, wherein the composition of the III-V group compound semiconductor mixed crystal layer is changed so that the band gap energy increases toward the heterojunction surface. 4. A compound semiconductor substrate (1), an electron supply layer (46) and an electron transit layer (3) which form a heterojunction on the compound semiconductor substrate (1), and the electron supply layer (46). ) On which a Schottky junction is formed, and a source electrode (7) and a drain which are formed on the electron supply layer (46) and arranged on both sides of the gate electrode (6). Electrode (8)
Wherein the electron supply layer (46) is composed of a III-V compound semiconductor mixed crystal layer, and the composition of the mixed crystal layer is a band on the heterojunction surface side toward the heterojunction surface. A compound semiconductor device, characterized in that the gap energy changes so as to increase and the band gap energy increases toward the Schottky junction surface on the Schottky junction surface side.