JPH0574146A - Multi-port memory - Google Patents

Abstract

PURPOSE:To achieve a smaller scale of circuits by making a column decoder in common use to a plurality of ports. CONSTITUTION:Word lines W0-W3 and bit lines B0-B7 are led from a memory array 1 in which memory cells are arranged in a matrix. One of the work lines W0-W3 is specified by a select signal from a row decoder 2. A plurality of input/output lines IO0-IO2 are arranged. The input/output lines IO1-IO2 are connected to the bit lines B0-B7 selectively by select signals S0-S9. The select signals S0-S9 are so arranged to connect the bit lines B0-B7 to the input/output lines IO0-IO3 separately so that the bit lines are shifted one by one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiport memory in which a plurality of serial ports are derived from one semiconductor memory array.

[0002]

2. Description of the Related Art A semiconductor memory array in which a plurality of memory cells are arranged in a matrix and word lines for selecting memory cells in the row direction and bit lines for selecting memory cells in the column direction are derived. It has been known. A row decoder that generates a select signal for selecting a word line and a column decoder that generates a select signal for selecting a bit line are provided. For example, by decoding the upper bits of the address, the word select signal is generated, and by decoding the lower bits thereof, the bit select signal is generated.

In such a memory array, a multiport memory can be constructed by connecting a plurality of input / output ports to bit lines and providing a column decoder for designating the bit lines accessed at each port.

[0004]

In a multi-port memory, a structure which enables row designation and output data speed setting independently requires a number of control circuits and column decoders equal to the number of output ports. Will increase. For processing audio or video signals,
There are few processes that require a plurality of completely independent data, and there are many processes that calculate data that are temporally or spatially close to each other. For example, in a digital filter, the inner product operation of a plurality of temporally continuous data is performed. Therefore, when handling the processing of audio signals or video signals, a memory capable of accessing nearby data through a plurality of input or output ports is required.

Therefore, an object of the present invention is to provide a multiport memory suitable for processing an audio signal or a video signal, with a circuit size not so large.

[0006]

In a multiport memory according to the present invention, a plurality of memory cells are arranged in a matrix, and first lines W0 to W3 for selecting one of rows or columns in the memory cells. , A memory array (1) from which a second line B0 to B7 for selecting the other row or column in the memory cell is derived, and a select signal for selecting the first line W0 to W3 A first decoder (2) for inputting, and a plurality of input or output ports IO0, IO1, connected to the second lines B0 to B7.
IO2 and multiple input / output port IO
0, IO1, IO2 are shared and the second line B0
A second decoder (4) for generating select signals S0 to S9 for selecting B7, and a second line B0
The select signals S0 to S9 for selecting B0 to B7 couple the second lines B0 to B7 at positions shifted one by one to the plurality of ports IO0, IO1 and IO2, respectively.

[0007]

Since the second decoder 4 is shared by the plurality of input / output ports IO0 to IO2, the circuit scale is small. The input / output ports IO0 to IO2 are simultaneously accessed with three neighboring data at positions corresponding to those activated by the select signals S0 to S9.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 denotes a semiconductor memory array in which memory cells are arranged in a matrix. In this embodiment, as a simple example, the memory array 1 is composed of memory cells of 4 rows × 8 columns. Memory array 1
Word lines W0, W1, W2, W for selecting each row of
3 and bit lines B0, B1, for selecting each column
..., B7 is provided. Three input / output lines IO0, IO1, IO2 are arranged in parallel with the bit lines B0 to B7.
Are connected. In FIG. 1 and the drawings described below, the sense amplifier, the place where the load is heavy, for example, the strong buffer to be connected to the word line, etc. are not shown because they are not related to the gist of the present invention. ..

The row decoder 2 is connected to the word lines W0 to W3.
Select signal is selectively supplied, and one of the word lines (rows) is selected. A control signal from the control circuit 3 is supplied to the row decoder 2, and the control circuit 3 is also coupled to the column decoder 4. The control circuit 3 supplies, for example, the upper bits of the address to the row decoder 2, and the control circuit 3 supplies the lower bits to the column decoder 4.

The select signal from the row decoder 2 selects one row, while the select signals S0 to S9 from the column decoder 4 are supplied to a plurality of bit lines. That is, the select signal S0 is supplied to the bit line B0, the select signal S1 is supplied to the bit lines B0 and B1, the select signal S2 is supplied to the bit lines B0, B1 and B2, and the select signal S3 is supplied to the bit lines B1 and B2. , B3, and thereafter, the select signal is supplied to the bit lines so that the bit lines are sequentially shifted one by one.

In FIG. 1, as shown in FIG. 2A, a simple expression is used in which the bit line, for example, B0 and the input / output line IO0 are orthogonal to each other, and the supply line of the select signal S2 diagonally crosses this intersection. ing. This means that, as shown in FIG. 2B, the switching element SW is provided between the bit line B0 and the input / output line IO0, and the switching element SW is turned on by the active select signal S2. When the switching element SW is turned on, the bit line B0 and the input / output line IO0 are coupled.

As an example, the row decoder 2 is a word line W.
When the select signal for selecting 1 is output, eight memory cells connected to this word line W1 are designated. At the same time, the column decoder 4 causes the column lines B1, B2, B
When the select signal S3 for selecting 3 is activated,
The memory cells labeled A, B and C in FIG. 1 are accessed. Therefore, with respect to the memory cells A, B and C, data can be written or read through the input / output lines IO0, IO1 and IO2. Here, assuming that the memory array 1 corresponds to, for example, the spatial arrangement of video signals and one sample of data is stored in each cell, a plurality of neighboring pixel data can be simultaneously accessed.

FIG. 3 shows another embodiment of the present invention. Similar to the example of FIG. 1, the word lines W0 to W3 and the bit lines B0 to B0.
A memory array 1 from which B7 is derived is provided, and a row decoder 2 for selecting a word line is provided.
In FIG. 3, three input / output lines IO10, IO11, IO12 are connected in parallel to the bit lines B0 to B7, and the other three input / output lines IO20, I20.
O21 and IO22 are connected in parallel. Bit line B0
Similar to FIG. 2B, switching elements for selectively coupling B7 and input / output lines IO10, IO11, IO12 are connected to the intersections of the bit lines B0 to B0.
Switching elements for selectively coupling B7 and input / output lines IO20, IO21, IO22 are also connected to the intersections.

A row decoder 2 and two column decoders 4A and 4B are connected to the control circuit 3. And
Bit lines B0-B7 and input / output lines IO10, IO1
Select signals S10, S11, ..., S19 are respectively supplied from the column decoder 4A to the switching elements at the intersections with 1 and IO12 so that the bit lines are shifted by one. Bit lines B0 to B7 and input / output line I
Similarly, select signals S20, S21, ..., S29 are supplied from the column decoder 4B to the switching elements at the intersections with O20, IO21, IO22.

As shown in FIG. 3, by providing the two column decoders 4A and 4B independently, for example, when the word line W1 is selected, the select signals S13 and S are selected.
By activating 26, A in FIG.
B, C, D, E, and F memory cells can be accessed.

FIG. 4 is similar to the example of FIG. 3 and has six inputs / inputs.
Although it has output lines IO10 to IO22, the layout is different from that of FIG. Bit lines B10 to B17 and B20 to B27 are respectively derived from the memory array 1, column decoders 4A and 4B are arranged above and below (positional relationship in the drawing), and bits are selected by the select signals S10 to S19 from the column decoder 4A. Line B1
0 to B17 are selected, and bit lines B20 to B20 are selected by select signals S20 to S29 from the column decoder 4B.
27 is selected.

As shown in FIG. 5, input / output lines IO0, IO1 and IO2 are connected to memory array 1, bit lines B10 to B17 are accessed by select signals S0 to S9, and shift register 5 is connected. Alternatively, the serial input / output line SIO may be derived from the shift register 5. The control signal from the control circuit 5 is supplied to the shift register 5, and 8 bits on one word line of the memory array 1 are supplied.
The memory cells are coupled to the shift register 5 in parallel, and data is serially input / output to / from the shift register 5 through the serial input / output line SIO.
For example, the word line W1 is selected, the contents of the eight memory cells on the word line W1 are loaded into the shift register 5 in parallel, and the serial input / output line SI is transferred from the shift register 5.
Data of each memory cell is serially output to O. The example of FIG. 5 is suitable for video signals in raster scan order.

Further, a plurality of shift registers may be provided for the bit lines B20 to B27 and a plurality of serial ports may be provided. As a result, a multiport memory having a plurality of serial ports can be constructed.
The plurality of serial ports can independently specify a row in the memory array and serially output the data in the row with independent clocks.

In the above embodiments, the input port and the output port are shared, but it is possible to have them separately. As shown in FIG. 6, one input line I0 is connected to the bit lines B10 to B17 of the memory array 1, and three output lines O0, O1 and O2 are connected to the bit lines B20 to B27. To be done. An input column decoder 4I and an output column decoder 4O are coupled to the control circuit 3. The column decoder 4I selects signals S30 to S30 for selecting one input bit line.
S37 is generated. The select signals S40 to S49 generated by the column decoder 4O are shifted one by one and supplied to the bit lines B20 to B27, respectively, as in the above-described embodiment. The select signals S40 to S49
Causes three memory cells to be accessed.

[0020]

According to the present invention, the column decoder can be shared for a plurality of input / output ports,
The circuit scale can be reduced as compared with the case where a column decoder is provided for each input / output port. Multiple inputs /
Only a plurality of memory cells in the vicinity of the memory array can be accessed from the output port. However, in processing a video signal or an audio signal, it is almost the case that a plurality of data in the vicinity are required at the same time. The restrictions do not hinder.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a multiport memory according to the present invention.

FIG. 2 is a connection diagram for explaining a connection relationship between bit lines, input / output lines, and select signal supply lines.

FIG. 3 is a block diagram of another embodiment of the present invention.

FIG. 4 is a block diagram of still another embodiment of the present invention.

FIG. 5 is a block diagram of still another embodiment of the present invention.

FIG. 6 is a block diagram of an embodiment in which an input column decoder and an output column decoder are separately provided.

[Explanation of symbols]

 1 Memory Array 2 Row Decoder 4 Column Decoder W0-W3 Word Line B0-B7 Bit Line IO0-IO2 Input / Output Line

Claims (1)

[Claims] 1. A plurality of memory cells are arranged in a matrix, and a first line for selecting one of the rows or columns in the memory cells and the other of the rows or columns in the memory cells are selected. And a first decoder for generating a select signal for selecting the first line, and a plurality of memory arrays connected to the second line. Input / output port, and a second decoder for generating a select signal for selecting the second line, which is shared by the plurality of input / output ports. The multi-port memory, wherein the select signal for selecting the second line connects the second lines at positions shifted one by one to the plurality of ports, respectively.