JPH0574145A - Dynamic ram - Google Patents

Abstract

PURPOSE:To eliminate useless power consumption of a main amplifier in writing by controlling the operation period of the main amplifier in the writing to be shorter than the writing period. CONSTITUTION:When an ATD detection signal phiATD is inverted to an H level from an L level with the inversion of a writing operation control signal phiWE to the H level, a main amplifier control circuit 75 turns a main amplifier activation signal phiMA to the H level only while the ATD detection signal phiATD is at the H level. Therefore, the main amplifier 10 works only while the ATD detection signal phiATD is kept at the H level. In other words, the main amplifier 10 is allowed to work during a period shorter than the writing period. Thus, operation period of the main amplifier 10 enabled in the writing can be shortened thereby getting rid of useless power consumption of the main amplifier in the writing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called dynamic RAM (dynamic random access memory.
Hereinafter referred to as DRAM).

[0002]

2. Description of the Related Art Conventionally, as a DRAM, there has been known one whose main part is shown in FIG. Drawing, 1 ₀ to 1 _n is the row (row) address and the address input terminal input in time division column (column) address, 2 address input terminals 1
A row address buffer for latching the row address input to ₀ to 1 _n , and φ _R is a row address buffer activation signal for activating the row address buffer 2.

Reference numeral 3 is a row address decoder for decoding the row address latched in the row address buffer 2, WL ₀ , WL ₁ ... WL _m are word lines, and 4 is a memory cell array in which memory cells are arranged. ..

Numeral 5 is a column address buffer for latching the column address inputted to the address input terminals 1 ₀ to 1 _n , and φ _C is a column address buffer activation signal for activating the column address buffer 5.

Reference numeral 6 is a column address decoder for decoding the column address latched in the column address buffer 5, CLS ₀ ... CLS _K are column selection lines, and 7 is a column selection line.
Is from the column address decoder 6 to the column selection line CLS _0.
... A column gate row for selecting a column based on a column selection signal supplied via CLS _K.

BL ₀ ... BL _K bars are bit lines,
8 is a sense amplifier row for amplifying the data read to the bit lines BL ₀ ... BL _K bar, 9 is a sense amplifier drive for driving the sense amplifiers of the sense amplifier row 8 based on the sense amplifier drive control signal φ _SA The circuits, PSA and NSA are sense amplifier drive signals for driving the sense amplifier.

Also, DB and DB bar are bit lines BL ₀ ,
BL ₀ bar ... The data bus 10 commonly provided for BL _K and BL _K bars is a main amplifier that amplifies the data transmitted to the data buses DB and DB bar during reading and writing, and φ _MA is This is a main amplifier activation signal that activates the main amplifier.

The DO and DO bars are the main amplifier 10
, Complementary data DO output from the main amplifier 10, a data output buffer for latching DO bar, 12 a data output terminal, and D _OUT data output from the data output buffer 11.

Further, WE bar is a write operation control signal inputted from the outside, 13 is a buffer for write operation control signal for latching this write operation control signal WE bar, φ _WE
Is a write operation control signal output from the write operation control signal buffer 13.

Reference numeral 14 is a data input terminal, D _IN is input data, and 15 is a data input buffer for latching the data D _IN . This data input buffer 15 is activated by a write operation control signal φ _WE. Is configured.

Reference numeral 16 is an address transition detection circuit (hereinafter, ATD) for detecting a transition (change) of the column address.
[Address transition detector] circuit), φ _ATD
Is an address transition detection signal output from the ATD circuit 16, and 17 is a main amplifier control circuit for controlling activation / deactivation of the main amplifier 10.

The main amplifier control circuit 17 has a period during which the address transition detection signal φ _ATD is active, that is,
The period during which the address transition detection signal φ _ATD is at the H level is substantially the same as the period during which the write operation control signal φ _WE is active, that is, the period during which the write operation control signal φ _WE is at the H level, It is configured to activate the main amplifier 10.

Reference numeral 18 is a timing control circuit,
The timing control circuit 18 includes a row address strobe signal RAS bar and a column address strobe signal C.
Input AS bar, and activate row address buffer activation signal φ
_R , the column address buffer activation signal φ _C, and the sense amplifier drive control signal φ _SA are output.

FIG. 6 is a circuit diagram showing a part of FIG. 5 in more detail. In the figure, in the memory cell array 4,
Reference numerals 19 and 20 are memory cells, 21 and 22 are cell transistors forming transfer gates, 23 and 24 are cell capacitors, and CP is a plate.

In the column gate row 7, 25,
Reference numeral 26 is a column gate, and 27 to 30 are nMOSs. In the sense amplifier row 8, 31 is a sense amplifier, 32 and 33 are pMOS, and 34 and 35 are nM.
OS. In the sense amplifier drive circuit 9,
36 is an inverter, 37 and 38 are pMOS, 39 and 40
Is an nMOS, and VPR is a precharge voltage.

FIG. 7 is also a circuit diagram showing a part of FIG. 5 in more detail. In the figure, in the main amplifier 10, 4
1, 42 are differential amplifier circuits having a common current source, 4
3, 44 are differential amplifier circuits having a common current source, 45
Is a flip-flop circuit, and 46 is a flip-flop control circuit for fixing the output data of the flip-flop circuit 45.

In the differential amplifier circuits 41 to 44,
47 to 54 are pMOSs forming load transistors, 55 to 55
Reference numeral 62 is an nMOS forming a drive transistor (differential pair transistor), and 63 and 64 are nMOS forming a current source.
In the flip-flop circuit 45, 65, 66
Is a NAND gate. Further, in the flip-flop control circuit 46, 67 and 68 are pMOS.

In the data input buffer 15,
Reference numeral 69 is a buffer, 70 and 71 are inverters for converting input data D _IN into complementary signals, and 72 and 73 are nMOSs for connecting the output terminals of the inverters 70 and 71 to the data buses DB and DB bar at the time of writing.

FIG. 8 is a time chart for explaining the operation of the conventional DRAM, in which a row address is fixed and a plurality of memory cells connected to the same word line selected by the row address are connected to the column address. 1 shows an example of operation in a so-called fast page mode in which access is continuously changed without changing.

In the first page mode, the cycle a is a read cycle, which shows the read operation of the memory cell designated by the row address R1 and the column address C1.

Cycle b is a read-modify-write cycle, cycle b1 is a read operation of a memory cell designated by a row address R1 and column address C2, and cycle b2 is a row address R1. The write operation of the data WD to the memory cell designated by the column address C2 is shown.

Cycle c is a read cycle and shows a read operation of the memory cell written in the previous cycle, that is, the memory cell designated by the row address R1 and the column address C2.

This operation will be described in more detail. In the read cycle a, the row address strobe signal RAS bar and the column address strobe signal CAS.
It starts when the row address strobe signal RAS bar falls to the L level from the state where both the bars are at the H level.

Here, the row address strobe signal RA
When the S-bar falls from the H level to the L level, the timing control circuit 18 inverts the row address buffer activation signal φ _R from the L level to the H level to activate the row address buffer 2 to activate the column address. The signals supplied to the address input terminals 1 ₀ to 1 _n prior to the fall of the strobe signal CAS bar are latched in the row address buffer 2 as row addresses.

The row address latched in the row address buffer 2 is supplied to the row address decoder 3 to be decoded, and the word line to be selected changes from L level to H level.
Can be raised to a level.

Then, the cell transistor connected to the word line becomes conductive, and the charge accumulated in the cell capacitor connected to this cell transistor is precharged to a constant precharge potential. A potential difference is generated in the line pair.

The capacity of the cell capacitor is much smaller than the capacity of the bit line, and the potential difference between the bit lines is very small. Therefore, the potential difference between the bit lines generated by the charges accumulated in the cell capacitor needs to be amplified by the sense amplifier.

Here, the sense amplifier drive control signal φ
_SA is inverted from the L level to the H level after a potential difference is generated between the bit lines, whereby the sense amplifier drive circuit 9 raises the sense amplifier drive signal PSA, which was at the precharge potential VPR, to the Vcc level. Then, the sense amplifier drive signal NSA is lowered to the ground level.

Then, the bit line on the higher potential side is Vcc.
The bit line on the low potential side is lowered to the Vss level. Through the above operation, the data in the memory cell is amplified and latched by the sense amplifier.

Next, the column address strobe signal CA
The S bar is lowered from the H level to the L level, and in response to this, the timing control circuit 18 inverts the column address buffer activation signal φ _C from the L level to the H level.

[0031] As a result, the column address buffer 5 is activated, the signal supplied to the address input terminals 1 ₀ to 1 _n at that time is latched in the column address buffer 5 as a column address.

The column address latched in the column address buffer 5 is supplied to the column address decoder 6 to be decoded, and the corresponding column selection line is raised.

Then, the nMOS forming the column gate to which the selected column selection line is connected becomes conductive, the bit line of the selected column is connected to the data buses DB and DB bar, and the selected memory cell is selected. Data is transmitted to the data buses DB and DB bar.

Here, the main amplifier 10 is activated by the main amplifier activation signal φ _MA , and the data bus D
The differential amplifier circuits 41 to 41 transmit the data transmitted from the B and DB bars.
It is taken into the flip-flop circuit 45 via 44. The captured data is transmitted to the data output buffer 11 as DO and DO bar, and is output to the outside via the data output terminal 12.

Next, referring to FIG. 8, read modify
When the read operation b1 in the write cycle b is performed, specifically, the column address changes from C1 to C2, and the data D _C2 is read from the memory cell specified by the row address R1 and the column address C2. In the first page mode,
The column address is taken in whenever the column address strobe signal CAS bar is at H level.

That is, the column address strobe signal CA
If the column address changes while S bar is at H level,
The column is selected by the new column address,
Address transition detection signal φ supplied from ATD circuit 16
_{By ATD} , the main amplifier control circuit 17 sets the main amplifier activation signal φ _MA to H level for a certain period of time to operate the main amplifier 10. As a result, the data D _C2 is output to the data output terminal 12.

Next, referring to FIG. 8, read modify
When the write operation b2 in the write cycle b is performed, specifically, the case where the column address C2 does not change and the data WD is written to the memory cell specified by the row address R1 and the column address C2 Although shown, the write operation b2 is performed by the write operation control signal W
This is performed by lowering the E-bar from the H level to the L level and raising the write operation control signal φ _WE from the L level to the H level.

When the write operation control signal φ _WE rises, the write data WD given to the data input terminal 14 is taken into the data input buffer 15 and supplied to the data buses DB and DB bar. Data is written to the memory cell from the selected bit line.

Next, FIG. 8 shows a case where the read cycle c is performed. In this read cycle, the column address C2 does not change, and the memory cell specified by the row address R1 and the column address C2. Data from D _C2
This is a case where a (= WD) read operation is performed.

In this case, this read cycle c is performed by returning both the column address strobe signal CAS bar and the write operation control signal WE bar from the L level to the H level and causing only the column address strobe signal CAS bar to fall. ..

In this read cycle c, the memory cell written in the previous cycle, that is, the row address R
1. The read operation of the memory cell designated by the column address C2 is performed. Since the column address does not change, the data WD written in the write cycle b2 of the read modify write cycle b can be read. In the write cycle b2, the main amplifier 1
It is necessary to operate 0.

That is, in general, in the first page mode, when the data of the memory cell to which data has been written is read in the next cycle, the main amplifier 1 is written at the time of writing.
This is done because it is necessary to bring 0 into the active state.

[0043]

[Problems to be Solved by the Invention]
In the page mode, the operation period of the main amplifier 10 is set even when the main amplifier 10 is in the operating state at the time of writing because of the necessity of reading the data of the written memory cell in the next cycle. However, in the conventional DRAM, the main amplifier control circuit 17 has a shorter period than the writing period.
Since the main amplifier 10 is configured to operate during the entire writing period, unnecessary power is consumed, which is a problem.

In view of the above point, an object of the present invention is to provide a DRAM capable of reducing unnecessary power consumption by eliminating unnecessary power consumption of the main amplifier at the time of writing.

[0045]

A DRAM according to the present invention
Is configured to read the data of the memory cell through the bit line, the sense amplifier, the column gate, the data bus, the main amplifier and the data output buffer, and is connected to the same word line selected by the row address. In a dynamic RAM configured so that a plurality of memory cells can be continuously accessed without changing or changing the column address, a main amplifier that controls an operation period of the main amplifier during writing is shorter than the writing period. An amplifier operation period control means is provided to control the operation period of the main amplifier during writing to a period shorter than the writing period.

Here, for example, the main amplifier operation period control means can be composed of an ATD circuit for detecting a transition of a column address and a main amplifier control circuit for controlling activation / deactivation of the main amplifier. In this case, the AT output from the ATD circuit is shorter than the write period.
It can be substantially the same as the period during which the D detection signal is active.

For example, in the ATD circuit, in addition to the column address transition, the change of the write operation control signal or the change of the write operation control signal from the inactive state to the active state is performed similarly to the case of the column address transition. It can be achieved by configuring to detect.

[0048]

In the present invention, the main amplifier, which is sufficient to be in the operating state for the period shorter than the writing period and the writing period, is controlled to be in the operating state for the period shorter than the writing period and the writing period. It is possible to eliminate unnecessary power consumption in the main amplifier.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and duplicate description thereof will be omitted.

FIG. 1 is a block diagram showing an essential part of an embodiment of the present invention. This embodiment is structurally related to the conventional D shown in FIG.
The difference from the RAM is that an ATD circuit 74 and a main amplifier control circuit 75 having different circuit configurations from the ATD circuit 16 and the main amplifier control circuit 17 provided in the conventional DRAM shown in FIG. 5 are provided. about,
It is configured similarly to the conventional DRAM shown in FIG.

Here, the ATD circuit 74 is constructed as shown in the circuit diagram of FIG. In the figure, 76 is a pMO that serves as a load for supplying the power supply voltage Vcc to the node 77.
S _n , 78 ₀ , 78 ₁ ... 78 _n are column address / bit signal transition detection circuits that detect transitions (changes) of the respective bit signals of the column addresses CA0, CA1 ... CAn.

[0052] Further, in the column address bit signal transition detection circuit 78 _0, 79 to 82 are inverters, 83
86 are nMOSs. Here, the column address CA
When 0 is stable at the H level, the nMOSs 83 and 86 are turned on and the nMOSs 84 and 85 are turned off, and the column address / bit signal transition detection circuit 78 ₀ is in a high impedance state with respect to the node 77.

However, from this state, when the column address CA0 is inverted to the L level, the nMOS 85 is inverted from OFF to ON, so that the node 77 is connected to the nMOS 85,
It is grounded via 86 and the level of the node 77 is lowered to the ground level, that is, the L level.

After that, when the total delay time of the inverters 80 to 82 elapses, the nMOS 86 is turned off. At this time, therefore, the level of the node 77 is the Vcc level, that is, the level of the node 77.
It will return to the H level.

[0055] Further, in the column address bit signal transition detection circuit 78 _0, column address CA0 is L
When the level is stable, the nMOSs 83 and 86 are turned off,
nMOS84,85 is turned on, again, the column address bit signal transition detection circuit 78 ₀ is at the high-impedance state with respect to node 77.

However, from this state, when the column address CA0 is inverted to the H level, the nMOS 83 is inverted from off to on.
Grounded via 84, the level of node 77 is lowered to the ground level, that is, the L level.

After that, when the total delay time of the inverters 79 to 81 elapses, the nMOS 84 is turned off. At this time, therefore, the level of the node 77 is Vcc level, that is,
It will return to the H level. The other column address / bit signal transition detection circuits 78 ₁ ... 78 _n are similarly configured for the column addresses CA1 ... CAn, respectively.

Further, 87 is an L of the write operation control signal φ _WE .
A write operation control signal transition detection circuit for detecting the transition from the level to the H level, 88 to 90 are inverters, and 9
Reference numerals 1 and 92 are nMOS.

This write operation control signal transition detection circuit 87
, The write operation control signal φ _WEIs stable at L level
, NMOS91 is off and nMOS92 is on
Therefore, in this case, the write operation control signal transition
The transfer detection circuit 87 is connected to the node 77 with a high impedance.
State.

However, when the write operation control signal φ _WE is inverted from the L level to the H level, the nMOS 91 is inverted from OFF to ON.
Grounded via 92, the level of node 77 is lowered to the ground level, that is, the L level.

After that, when the total delay time of the inverters 88 to 90 elapses, the nMOS 92 is turned off, so that the level of the node 77 returns to the Vcc level, that is, the H level.

Further, 93 is a sense amplifier drive control signal φ.
An inverter 94 that inverts _SA is a NOR gate that NOR-processes the output of the inverter 93 and the level of the node 77 and outputs an ATD detection signal φ _ATD .

Here, the sense amplifier drive control signal φ
_SA is the first lead in first page mode.
Since it is set to H level in the cycle, the output of the inverter 93 is then set to L level. As a result, during the period when the level of the node 77 is L level, the NOR gate 9
4 outputs H level as the ATD detection signal φ _ATD .

That is, the ATD circuit 74 in this embodiment.
Indicates that the column addresses CA0, CA1 ... CAn have changed and the write operation control signal φ _WE has changed from L level to H level.
The ATD detection signal φ _ATD is output in any of the cases of transition to the level.

The main amplifier control circuit 75 which constitutes the present embodiment is constructed as shown in the circuit diagram of FIG. In the figure, 95 to 98 are inverters, 99 and 10
0 is a NAND gate.

FIG. 4 is a time chart for explaining the operation of this embodiment, showing an example of the operation in the first page mode similar to the case of FIG.
In FIG. 4, cycles a, b, b1, b2, c
Are the cycles a, b, b1, b2, c of FIG.
It corresponds to. That is, the cycle a is a read cycle and represents a read operation of the memory cell designated by the row address R1 and the column address C1.

Cycle b is a read-modify-write cycle, cycle b1 is a read operation of a memory cell specified by a row address R1 and column address C2, and cycle b2 is a row address R1. The write operation of the data WD to the memory cell designated by the column address C2 is shown.

Cycle c is a read cycle and shows the read operation of the memory cell written in the previous cycle, that is, the memory cell specified by the row address R1 and the column address C2.

In this embodiment, the main amplifier control circuit 75 uses the AT as shown in the read cycle a.
When the D detection signal φ _ATD is at the L level and the sense amplifier drive control signal φ _sA changes from the L level to the H level, the main amplifier activation signal φ _{MA is set} to the H level during the total delay time of the inverters 96 to 98. To do. Therefore, the main amplifier 10 operates during this period. This point is similar to the case of the conventional DRAM.

As shown in the read cycle b1 of the read modify write cycle b, the sense amplifier drive control signal φ _sA is at the H level and the column address is changed from C1 to C2. _{When ATD} is inverted from the L level to the H level, the main amplifier control circuit 75 causes the main amplifier activation signal φ _{MA to be} maintained only while the ATD detection signal φ _ATD is at the H level.
To H level. Therefore, the ATD detection signal φ _ATD
The main amplifier 10 operates only during the period when is at H level. This point is also similar to the case of the conventional DRAM.

Further, as shown in the write cycle b2 of the read modify write cycle b, the sense amplifier drive control signal φ _sA is at the H level and the write operation control signal WE bar is inverted from the H level to the L level. That is, since the write operation control signal φ _WE is inverted from the L level to the H level, the ATD detection signal φ _ATD is changed from the L level to the H level.
When inverted to the level, the main amplifier control circuit 75
The main amplifier activation signal φ _{MA is set} to the H level only while the ATD detection signal φ _ATD is at the H level. Therefore, the main amplifier 10 operates only while the ATD detection signal φ _ATD is at the H level.
This point is different from the conventional DRAM.

That is, in this embodiment, the ATD detection signal φ _{ATD is set} to H level as in the case of writing and reading.
The level is set so that the main amplifier 10 is operated only during the period when the ATD detection signal φ _ATD is at the H level (the period during which the ATD detection signal φ _ATD is active), that is, the period shorter than the writing period. ing.

As described above, according to the present embodiment, the operation period of the main amplifier 10 which is in the operating state at the time of writing is shortened because it is required when performing the reading operation from the same address after the writing operation. Therefore, unnecessary power consumption of the main amplifier at the time of writing can be eliminated, and low power consumption can be achieved.

[0074]

According to the present invention, it is possible to set the main amplifier, which is sufficient to be in the operating state at the time of writing and shorter than the writing period, to the operating state at the time of writing and shorter than the writing period. It is possible to reduce unnecessary power consumption by eliminating unnecessary power consumption of the main amplifier during writing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an ATD circuit that constitutes an embodiment of the present invention.

FIG. 3 is a main amplifier control circuit that constitutes an embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 5 is a block diagram showing a main part of an example of a conventional dynamic RAM.

FIG. 6 is a circuit diagram showing a part of FIG. 5 in more detail.

FIG. 7 is a circuit diagram showing a part of FIG. 5 in more detail.

FIG. 8 is a time chart for explaining the operation of the conventional dynamic RAM shown in FIG.

[Explanation of symbols]

1 ₁ , 1 _n Address input terminal 10 Main amplifier 74 ATD circuit 75 Main amplifier control circuit

Claims (4)

[Claims] 1. The same word line selected by a row address while being configured to read data of a memory cell through a bit line, a sense amplifier, a column gate, a data bus, a main amplifier and a data output buffer. In a dynamic RAM configured such that a plurality of memory cells connected to a memory can be continuously accessed without changing or changing a column address, an operation period at the time of writing of the main amplifier is shorter than a writing period. A dynamic RAM characterized in that a main amplifier operating period control means for controlling the main amplifier is provided to control the operating period of the main amplifier during writing to a period shorter than the writing period. 2. The main amplifier operation period control means comprises an address transition detection circuit for detecting column address transitions and a main amplifier control circuit for controlling activation / deactivation of the main amplifier. 2. The dynamic R according to claim 1, wherein the shortest period is substantially the same as the period during which the address transition detection signal output from the address transition detection circuit is active.
AM. 3. The address transition detection circuit is configured to detect a transition of a column address and a change of a write operation control signal in the same manner as a transition of a column address. 2 dynamic R
AM. 4. The address transition detection circuit is configured to detect a transition of a write operation control signal from an inactive state to an active state in the same manner as a column address transition, in addition to a column address transition. 3. The dynamic RAM according to claim 2, wherein: