JPH0573443A - Interface bus controller - Google Patents

Abstract

PURPOSE:To easily execute an analysis of a bus fault by storing a state of a signal on a bus related to a fault on the bus, in an exclusive storage circuit without delaying an original operation of the interface bus controller. CONSTITUTION:In an interface bus controller 400, a bus state monitoring circuit 2 for sampling a signal on a general interface bus and outputting its result, a storage circuit 1 for storing its output, holding a state until that time at the time when an alarm signal is applied and stopping a storage operation, and a timer 3 which starts, when an instruction addressed to an information processor sent out onto the general interface bus is detected, and generates and outputs the alarm signal, when a reception completing signal is not outputted onto the general interface within a prescribed time are provided, and the storage operation of the storage circuit 1 is stopped by the alarm signal, and by information stored in the storage circuit 1, a bus fault can be analyzed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface bus control device, and more particularly, to an interface bus control device for controlling signal transmission / reception by interposing a plurality of information processing devices and a host computer.

[0002]

2. Description of the Related Art In recent years, there are many situations in which a plurality of information processing devices, peripheral devices, measuring devices, etc., of different manufacturers and models must be connected to perform communication such as data transfer. At that time, in order to easily connect the devices, an internationally standardized interface bus standard between the devices is used. Generally, an interface bus called GP-IP, SCSI is used as an international standardized general-purpose interface bus. However, for these interface buses, even if the standard is unified, many troubles (bus failure) occur in the connection between different types of devices due to the difference in interpretation. is there. When a problem occurs when placed on a general-purpose interface bus, in order to investigate which device on the bus and what caused the failure, connect a measuring instrument such as a commercially available bus analyzer to the general-purpose interface bus, A general method is to wait for the reproduction of the current situation and collect the data of the communication state via the above-mentioned bus. Also, conventionally, although automatic collection and storage of communication status data via the general-purpose interface bus status have been performed, the circuit controlling those operations controls normal data transfer and the like. The interface bus controller is also used.

[0003]

In the conventional bus state storage system described above, a circuit for automatically collecting data of the communication state via the bus and controlling the storage controls normal data transfer and the like. Since it is used together with the circuit for performing the operation, the load of the normal operation is imposed, the performance of the normal data transfer operation is deteriorated, and there is a drawback that a large amount of memory resources are used for storing the collected data described above. Also,
Sampling of the communication status via the bus is generally performed when any signal on the bus changes, and the relationship between the change in the communication status via the bus and the trouble can be known. However, it is impossible to know the relationship between the change in the communication status via the bus and the trouble in real time. On the other hand, when collecting data on the communication status via the bus using a measuring instrument such as a commercially available bus analyzer, the reproducibility of troubles affects the degree of data acquisition required, and it takes a lot of time and effort. It has the drawback of requiring time. The object of the present invention is to improve the above-mentioned drawbacks and collect the data necessary for investigating the cause when a trouble occurs more easily without degrading the performance of the original general-purpose interface bus.
It is to provide an interface bus control device that can store.

[0004]

An interface bus control device of the present invention is interposed between a host computer and an information processing device, and the information processing device is subject to a predetermined protocol via a general-purpose interface bus. With respect to signals passing between the host computer and the information processing device, control is performed to convert a signal transmitted from one of the host computer and the information processing device into a signal format that can be received by the other device and transfer the signal to each destination. In the interface bus control device, a signal provided in the interface control device and transmitted from the host computer and a signal transmitted from the information processing device to the interface bus control device are transmitted from the general-purpose interface bus to the interface bus. From the cycle of the number of clocks of the signal A bus state monitoring circuit that samples at regular intervals and outputs as a sampling signal, and stores the sampling signal when the sampling signal is output in the interface bus control device and stores the sampling signal over the entire storage area. A memory circuit that repeatedly overwrites the memory area already stored when an abnormal signal is received and stops the memory operation and retains the information stored up to that time; When a signal on the interface bus is monitored and a command signal to the information processing device is detected from the host computer, time measurement is started and a response signal to the command signal sent from the information processing device which is the destination of the command signal is monitored. From the predetermined time after the command signal is output If the time until arrival of the response signal becomes large is configured to include a timer for outputting the abnormal signal.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. First, the normal operation will be described. The interface bus control device 400 includes the host computer 20.
In response to a command from the device, the information processing devices 21 and 22 connected via the general-purpose interface bus 100 operate such as data transfer. At this time, the command from the host computer 20 is sent to the bus conversion unit 11 via the system bus 300 connecting the host computer and the interface bus control device 400, and the data format is converted. It is sent to the device 400 via the internal bus 200 to the processor 13 or the local memory 12. Next, the processor 13 analyzes the above-mentioned command, generates a predetermined local command according to the result, and sends this local command to the general-purpose interface bus control unit 10 via the internal bus 200. Based on this local command, the general-purpose interface bus control unit 10 exchanges data with other information processing devices 21 and 22 via the general-purpose interface bus 100. In the present invention, a bus state monitoring circuit 2, a timer 3, and a memory circuit 1 are newly added to the conventional interface bus control device of this type. The bus state monitoring circuit 2 is connected to the general-purpose interface bus 100 in the interface bus control device 400, samples the bus state at regular time intervals, temporarily holds the result, and outputs it to the memory circuit. This sampling interval must be shorter than the bus cycle of the general-purpose interface bus 100 in order to easily and characterize the subsequent trace data analysis. The sampled data is sent to the storage circuit 1 and stored therein. When the memory is used up, the oldest data is overwritten and updated again. Here, the memory circuit 1 is provided with a memory necessary for storing the sampling data and a control circuit for controlling the operation of this memory. The timer 3 monitors the bus failure of the general-purpose interface bus 100, generates a warning signal when detecting the bus failure, and generates a warning signal.
An alarm signal is output to. This alarm signal is the memory circuit 1
Stop the memory operation applied to. This bus failure
The time from the sending time of the sending signal from the general-purpose interface bus control unit 10 to the time at which the reception completion signal returns from the destination device of the sending signal is counted, and the reception completion signal is returned within the preset time. If there is no bus fault Here, in the timer 3, a circuit for setting / holding a time recognized as a bus failure, a circuit for detecting that a signal is sent from the general-purpose interface bus control unit 10 to the general-purpose interface bus 100, and an information processing device A circuit for detecting that the reception completion signal has returned from the destination of the above-mentioned transmitted signal in 21, 22 and the like, and counting from the time when the signal is transmitted from the general-purpose interface bus control unit 10 to the general-purpose interface bus 100. There is a timer to start. If the alarm signal output from the timer 3 is also output to the general-purpose interface bus control unit 10 and the general-purpose interface bus control unit 10 receives the alarm signal, the normal operation is stopped. Under such an operation stop state, the information stored in the memory circuit 1 is read by an external device (not shown) and the content thereof is analyzed to find the cause of the failure that has occurred.

[0007]

As described above, according to the bus state storage system of the present invention, by providing an independent bus state storage circuit in the general-purpose interface bus control device, when a bus failure occurs, a commercially available bus Eliminates the trouble of collecting bus status data with a measuring instrument such as an analyzer, and can trace the bus status without degrading the normal operation performance of a general-purpose interface bus such as data transfer, wasting memory resources for tracing. The effect is that there is nothing to do. In addition, by sampling the bus state at regular intervals, it is possible to know the relationship between the bus state conversion and the trouble in real time, which has the effect of improving the efficiency of trace data analysis after a failure occurs.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an interface bus control device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 memory circuit 2 bus state monitoring circuit 3 timer 10 general-purpose interface bus control unit 100 general-purpose interface bus 400 interface bus control device

Claims (1)

[Claims] 1. A signal which is interposed between a host computer and an information processing apparatus, and which travels between the host computer and the information processing apparatus according to a predetermined protocol for the information processing apparatus via a general-purpose interface bus. In an interface bus control device for controlling a signal transmitted from one of the host computer or the information processing device into a signal format that can be received by the other device and transferring the signal for each destination, in the interface control device. The signal transmitted from the host computer and the signal transmitted from the information processing device to the interface bus control device are provided at regular intervals shorter than the cycle of the number of clocks of the signal on the interface bus from the general-purpose interface bus. Sampling signal to And a bus state monitoring circuit for outputting the sampling signal and storing the sampling signal when the sampling signal is output and storing the sampling signal over the entire storage area from the already stored storage area. A memory circuit for stopping the memory operation when repeatedly overwriting and receiving an abnormal signal and retaining the information stored up to that time, and the host computer provided in the interface bus control device and monitoring the signal on the general-purpose interface bus. When the command signal to the information processing device is detected from the, the time measurement is started, and the response signal to the command signal sent from the information processing device which is the destination of the command signal is monitored, and it is predetermined after the command signal is output. If the time until the response signal arrives is longer than the Interface bus controller, characterized in that it comprises a timer for outputting a normal signal.