JPH0573428A - Security circuit - Google Patents

Abstract

PURPOSE:To hold security by inhibiting read-out by a read-out inhibiting circuit, in the case a security code and a key code do not coincide with each other, and executing read-out in the case they coincide with each other. CONSTITUTION:In the case a security code and a key code compared by a comparing circuit 4 do not coincide with each other, a comparison output signal becomes '0', and an output of a NOT circuit 10 becomes '1'. Also, since an enable signal of a flip-flop 7 is '1', an output signal of a NOD circuit 11 becomes '0' and is written in a memory 12, and held. When it is written in the memory 12, its output signal. becomes '0'. Accordingly, an RE signal of an output of an AND circuit 8 being a read-out inhibiting means always becomes '0', and read-out of data stored in a memory 13 contained in a microcomputer, etc., becomes impossible unless data in the memory 12 is erased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a security circuit for protecting software by limiting the reading of data such as programs written in a memory built in a microcomputer, and more particularly to a one-chip microcomputer. Is what is used.

[0002]

2. Description of the Related Art A microprocessor is widely used for controlling a device, but it takes a lot of time and labor to develop software such as a control program that the microprocessor should execute in order to make the device perform a desired function. Has been spent. Therefore, it is important to prevent software embedded in a microprocessor or the like from being imitated or stolen. 1
In a so-called one-chip microcomputer in which the main function of the microprocessor is realized by only one chip, the control program and data are usually written in the memory formed in the same chip as the CPU. Therefore, as a software protection means, it has been considered to prohibit the reading of the data in the memory to the outside of the chip. In the conventional technique, the user writes "0" or "1" in the EPROM storing the security code (1 bit) to operate the security circuit and thereby the data (program) in the memory.
The security operation of prohibiting the reading of is performed.

[0003]

However, in the security circuit as described above, once the security circuit operates, it becomes necessary for the user of the microcomputer to check the data stored in the ROM in order to maintain or update the software. But it can no longer be read.

Therefore, the present invention provides a security circuit that prohibits reading of internal information of a microcomputer by a third party, while allowing only a user who has set security for the microcomputer to read internal information such as a program. With the goal.

[0005]

In order to achieve the above object, the security circuit of the present invention is a security circuit for restricting the reading of data stored in a memory built in a microcomputer. A non-volatile first memory for storing a code, a holding circuit for holding a key code input to read the data, a security code stored in the first memory, and a key held by the holding circuit. A comparison circuit that compares the codes to detect a mismatch between the codes, a non-volatile second memory that stores the detection of the mismatch, and data from the memory as long as the mismatch is stored in the second memory. Read prohibition means for prohibiting the reading of data.

[0006]

According to the security circuit of the present invention configured as described above, when a security code is input, the security code is stored in the non-volatile first memory. Next, when a key code for reading the data stored in the memory is input, this key code is held by the data holding circuit. Further, the held key code and the security code stored in the non-volatile first memory are compared in the comparison circuit, and the comparison result is stored in the non-volatile second memory. Based on the comparison result stored in the second memory, when the security code and the key code do not match, the reading of the data stored in the memory is prohibited by the read prohibition circuit. The data stored in the memory is read based on the output control signal input from the.

Thus, a user with security can read internal information such as a program stored in the memory any number of times by inputting a key code set by the user. Others cannot read the data from the memory unless the same code as the preset key code is entered once, and practically no third party can obtain the internal information of the microcomputer. ..

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a portion related to security among various circuits formed on the microcomputer chip. When a security code is input from a keyboard (not shown) in the security setting mode, a CP (not shown) is displayed.
It is output to the data bus 1 via U. When the CPU gives a write command (A ₁ WR) signal to the nonvolatile memory 2 via the AND circuit 6, the memory 2 stores the security code. The memory 2 is, for example, an EPROM (Erasable).
and Probrammable ROM) or E ² PROM (Elec
torically vErasable and Probrammable ROM) etc., and is in a normal read mode. The read security code is supplied to the comparison circuit 4 and the AND circuit 5. The signal S3 is sent from the memory 2 to the comparison circuit 4 to determine whether the security code is stored.
Is supplied to. When the signal S3 outputs the "1" level indicating the unstored state of the security code, the output of the comparison circuit 4 is forcibly set to the "1" level, and when the "0" level indicating the storage state is output, the comparison circuit 4 Is activated. One bit in the memory 2 is designated as a security bit. The user can prohibit the reading of the security code by setting "0" in this bit. The output of the security bit is supplied to AND circuits 5 and 6. Once "0" is set in the security bit, the AND circuit 6 is closed to prevent the transmission of the A ₁ WR signal and prevent the writing of a new security code. Further, the AND circuit 5 is closed to prevent the security code from being read onto the data bus 1. When the security bit is set to "1", the AND circuit 6 is turned on and the new security code can be stored. When the read command (RD) signal is supplied from the CPU, the security code is changed to the AND circuit 5. Is output to the data bus 1 via.

When a key code is input from a keyboard (not shown) in the security read mode, the CP
It is output to the data bus 1 via U. When the CPU gives a write command (A ₂ WR) signal to the latch circuit 3, the key code is taken into the latch circuit 3 and held until a reset (RESET) command is supplied from the CPU. This key code is supplied to the comparison circuit 4. When the A ₂ WR signal and the write voltage Vpp used for the memory are supplied to the flip-flop 7, the flip-flop 7 is set and the enable signal is generated from the Q output terminal. The enable signal is the enable input terminal of the comparison circuit 4 and the NAND.
It is supplied to the circuit 11 to operate the comparison circuit 4 and open the NAND gate 11.

The comparison circuit 4 starts its operation in response to the enable signal. The security code supplied from the memory 2 is compared with the key code supplied from the latch circuit 3, and if they match, a "1" level is output, and if they do not match, a "0" level is output. The output of this comparison result is AND
It is supplied to the circuit 8. In addition, the inverter 10, NAND
It is also supplied to the write command input of the non-volatile memory 12 via the circuit 11. The memory 12 is constituted by using, for example, EPROM or E ² PROM, and is normally in a read mode.

The AND circuit 8 is also supplied with an output command (/ OE) signal and the output of the memory 12 via an inverter 9. When the / OE signal is supplied from the CPU while the memory 12 stores the "1" level, the AND circuit 8 is opened, and the comparison output is applied to the read enable terminal of the memory 13 as the read enable (RE) signal. Supply. The memory 13 is, for example, EPROM or E ² PR.
It is composed of an OM and stores various internal information such as control programs and data. When the address signal (AD) is supplied from the CPU while the RE signal is supplied, the corresponding storage information is output to the data bus 1 or an external data bus (not shown). This allows memory 1
The internal information stored in 3 is read out of the chip.

Next, the operation of the security circuit will be described. First, the case where security is not applied will be described. Before the security code is stored in the memory 2, the signal S ₃ output from the memory 2 is always "1". This signal S ₃ forcibly sets the comparison output of the comparison circuit 4 to "1". Therefore, the output of the NOT circuit 10 becomes “0” and the output of the NAND circuit 11 becomes “1”, and the memory 12 is not written. The output signal of the memory 12 becomes "1". Therefore, at this time, the RE signal that is output from the AND circuit 8 and controls the reading of the data stored in the memory 13 is the output control signal / O supplied from the outside through the NOT circuit 9.
It corresponds to E. That is, the / OE signal is "1".
In the case of, the output of the NOT circuit 9 becomes “0”, and the RE signal output from the AND circuit 8 becomes “0”.
Do not read data from. Further, when the / OE signal is "0", the output of the NOT circuit 9 becomes "1", so that the RE signal which is the output of the AND circuit 8 becomes "1" and the data can be read from the memory 13. Becomes

Next, a case where security is applied will be described. When the security code is transferred to the data bus 1 by the CPU and the memory 2 is addressed,
The A1 WR signal sent to the memory 2 becomes "1". The memory 2 is ready to write data, and the data bus 1
Import the security code existing in
Remember.

This security code can be read out by an RD signal. As described above, any bit of the memory 2 is defined as a security bit.
For example, by writing “0” in the security bit, it is possible to prevent the security code held in the memory 2 from being read out and the security code from being overwritten later.

In this way, when the data stored in the memory 13, which is a built-in memory of a microcomputer or the like, is read after the security code is input to the memory 2, the verify mode (write voltage Vpp is I
Key code and latch circuit 3 (when added to C chip)
Address (in this case, the same as the memory 2) is input. When the key code and the address of the latch circuit 4 are input to the CPU, the latch circuit 3 and the flip-flop 7 receive A
2 WR signal is sent. The flip-flop 7 is set to "1" only when the write voltage Vpp is further applied to the chip.
SVpp signal is supplied and set. The comparator circuit 4 is enabled by the Q output of the flip-flop 7, and the key code is latched in the latch circuit 4. The memory 2 is in the normal read mode.

Next, the comparison circuit 4 compares the security code stored in the memory 2 with the key code held in the latch circuit 3. If they match,
The output signal from the comparison circuit 4 becomes "1", and R of the AND circuit 8 is the same as in the case where the security is not applied.
The E signal outputs a signal corresponding to the control signal / OE from the outside.

On the other hand, when the security code and the key code compared by the comparison circuit 4 do not match, the comparison output signal becomes "0" and the NOT circuit 10
Output becomes "1". Since the enable signal of the flip-flop 7 is "1", the output signal of the NAND circuit 11 becomes "0", and the memory 12 is written and held. When the memory 12 is written, its output signal becomes "0". Therefore, the AND circuit 8 serving as the read prohibition means
The RE signal, which is the output of, is always "0", and the data stored in the memory 13 built in the microcomputer or the like cannot be read unless the data in the memory 12 is erased.

If the data in the memory 12 is erased,
The data that should be prohibited from being read, that is, the data of the built-in memory 13 that stores the internal information such as the control program is also formed on the same chip and is erased at the same time because the power source and the like are shared, and security is secured. Further, a configuration may be provided in which a memory erasing circuit 14 that resets the memory content of the memory 12 is provided. The memory erase circuit 14 is activated by the "0" output of the memory 12 and, for example, the E ² PROM
Drive the erasing gate of the memory 13 configured by or the memory 13 configured by EPROM is forced to "1".
You can erase the memory by writing. By doing so, it is possible to prevent the reading of the software built in the microprocessor more reliably.

In this way, a microcomputer user with security can repeatedly read data.
It is possible to obtain a security circuit that makes it extremely difficult for a third party to read data.

[0020]

As described above, according to the present invention, data stored in the memory can be repeatedly read out only by the microcomputer user for whom security is set.
It is difficult for a third party to read the internal information of the microprocessor, and once the wrong key code is entered, subsequent reading becomes impossible, or the microprocessor loses its control program and operates. Since it will disappear, further confidentiality can be expected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a security circuit according to the present invention.

[Explanation of symbols]

 2 non-volatile memory 3 latch circuit 4 comparison circuit 12 non-volatile memory 13 non-volatile memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Tsukasa Miyawaki, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Semiconductor System Technology Center (72) Inventor, Osamu Hayashi, Kawasaki-ku, Kawasaki, Kanagawa Ekimae Honmachi 25-1 Toshiba Microelectronics Co., Ltd.

Claims (2)

[Claims] 1. A security circuit for restricting reading of data stored in a memory built in a microcomputer, comprising: a nonvolatile first memory for storing a security code inputted in advance; A holding circuit for holding the key code input for reading, and a comparison circuit for comparing the security code stored in the first memory with the key code held by the holding circuit to detect a mismatch between the two codes. A non-volatile second memory for storing the detection of the mismatch, and a read prohibition unit for prohibiting reading of data from the memory as long as the mismatch is stored in the second memory. A characteristic security circuit. 2. The security circuit according to claim 1, further comprising data erasing means for erasing the data stored in the memory in response to the detection of the mismatch.