JPH0573362A - Detection circuit for abnormal operation of microcomputer - Google Patents

Abstract

PURPOSE:To quickly detect the abnormal operation of a microcomputer. CONSTITUTION:An L pulse monostable multivibrator 2 is triggered by a timing signal CP0 of a microcomputer 1 and outputs a 1st pulse signal CP1 having its pulse width larger than the pulse width of the signal CP0 and larger than the single cycle width. Meanwhile an S pulse monostable multivibrator 3 is triggered by the signal CP0 and outputs a 2nd pulse signal NCP1 having its pulse width smaller than that of the signal CP0. The signal CP0 is compared with the signals CP1 and NCP1, and an LED 11 is actuated via an LED driving circuit 10 when a fault occurs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer operation abnormality detection circuit.

[0002]

2. Description of the Related Art Conventionally, as this kind of operation abnormality detection circuit, a circuit called a watchdog timer has been known. In this circuit, if the watchdog timer times out without being reset even after the time that should have been reset by the timing signal output from the microcomputer data bus port, and if the operation of the microcomputer is abnormal It is designed to display the status.

[0003]

In the conventional watchdog timer circuit described above, the timing signal output from the port of the data bus generated by the program of the microcomputer is used. If the period of is significantly shortened, this state cannot be detected. Further, when the execution time of the program is changed, it is necessary to change the set time of the watchdog timer, which has a drawback that the external circuit connected to the microcomputer becomes complicated.

Therefore, the present invention has been made in view of the above existing circumstances, and it is determined that the change of the cycle of the timing signal or the limitation of the limited pulse width is exceeded. It is an object of the present invention to provide a microcomputer operation abnormality detection circuit capable of promptly knowing an operation abnormality of a microcomputer by detecting an abnormality in a timing signal.

[0005]

[SUMMARY OF] To achieve the above object, in the present invention, is triggered by the timing signal CP _0, and a pulse duration less than the larger one cycle width than the pulse width of the timing signal CP ₀ Having a single first
(2) for generating the pulse of the timing signal CP
₀ is triggered by, and a means for generating a single second pulse having a smaller pulse width than the pulse width of the timing signal CP ₀ (3), a timing signal CP ₀ first pulse signal CP ₁ and the second when the period of the timing signal CP ₀ has changed by inputting a pulse signal NCP _1, or the pulse width of the timing signal CP ₀ is greater than the first pulse width of the pulse signal CP _1, the second pulse signal When the pulse width becomes smaller than the pulse width of NCP ₁ , it is characterized by having a determination circuit which determines that the microcomputer 1 is malfunctioning and outputs a signal.

[0006]

In the microcomputer operation abnormality detection circuit according to the present invention, the determination circuit is the microcomputer 1
The timing signal CP ₀ generated and output by the internal program is constantly monitored.

Then, when the cycle changes, or when the pulse width changes beyond a certain control limit, this is immediately detected, and an abnormal operation of the microcomputer 1 is immediately notified.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION In the following, one embodiment of the present invention will be described with reference to the drawings, in which reference numeral 1 in FIG. 1 is a microcomputer and has a certain duty cycle (usually 50).
%) Timing signal CP ₀ is generated and output.

The output timing signal CP ₀ is
It is input to the L-pulse monostable multivibrator 2 that is a means for generating a single first pulse, triggered by the rising edge of the L-pulse monostable multivibrator 2, and the pulse width T ₀ of the timing signal CP ₀ long,
The L pulse signal CP ₁ having a pulse width T ₁ shorter than the one cycle width is generated and output. On the other hand, the timing signal C
P ₀ is an S pulse monostable multivibrator 3 which is a means for generating a single second pulse via the inverter 5.
Input to this S-pulse monostable multivibrator 3
Triggered on the rising edge of at pulse width T
S pulse signal CP ₂ having a pulse width T ₂ shorter than ₀
Is generated and output.

That is, each pulse width T ₀ , T ₁ , T
₂ has the following relationship in the normal oscillation state of the timing signal CP ₀ . 0 <T ₂ <T ₀ <T ₁ <2T ₀ (1)

The first NAND gate 6 receives the L pulse inversion signal NCP _{1 obtained} by inverting the L pulse signal CP ₁ by the inverter 4 and the timing signal CP _0, and the second NAND gate 6 receives the second pulse.
The NAND gate 7 receives the S pulse signal CP ₂ and the timing signal CP ₀ , and the outputs of the first and second NAND gates 6 and 7 are both input to the third NAND gate 8.

The output of the third NAND gate 8 is R-
It is input to the set terminal S of the S-type flip-flop 9, the Q output thereof is received by the light emitting diode drive circuit 10, and the light emitting diode 11 is turned on by the drive operation.

A power-on initialization circuit 12 is provided for resetting the RS flip-flop 9 by a manual operation, and a momentary switch 13 and a monostable multivibrator 14 reset the microcomputer 1 to an initial state. It is provided for.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. (1) Setting of initial state When the momentary switch 13 is pressed to operate the monostable multivibrator 14, the system reset signal of "L" level is input to the reset input terminal RESET of the microcomputer 1 for a certain period of time. As a result, the address 0 is stored in the program counter (not shown), and a numerical register (not shown) for setting the operation-designable timing signal
The content of is indefinite. At the same time, when the power-on initialization circuit 12 is operated, the RS flip-flop 9 is set to the initial state and the light emitting diode 11 is turned off.

(2) When the timing signal CP ₀ has a normal cycle, the microcomputer 1 operates with a normal program,
When the timing signal CP ₀ oscillates in the normal cycle T ₀ , the timing signal CP ₀ and the L pulse inversion signal NCP ₁ are simultaneously at the “H” level as shown in the “normal time” portion of FIG. It will not be the first NAND gate 6
Output never goes low. Similarly, since neither the timing signal CP ₀ nor the S pulse signal CP ₂ becomes “H” level at the same time, the output of the second NAND gate 7 does not become “L” level.

Therefore, as long as the microcomputer 1 operates "normally", the first NAND gate 6,
Both outputs of the second NAND gate 7 are at the "H" level, the output of the third NAND gate 8 is at the "L" level, and the light emitting diode 11 remains in the off state.

(3) When the cycle of the timing signal CP ₀ becomes longer The cycle T ₀ of the timing signal CP ₀ becomes longer than normal, does not fall at the time t ₁ , and remains at the “H” level until the time t ₃ . If it continues as it is, the condition of the expression (1) is not satisfied, and T ₁ <T ₀ (2). Therefore, even if the L pulse inversion signal NCP _{1 obtained} by inverting the L pulse signal CP ₁ rises at the time t ₂ , The timing signal CP _{0 is} still at the “H” level and has not fallen to the “L” level.

That is, since the timing signal CP ₀ and the L pulse inversion signal NCP ₁ simultaneously become “H” level and the output of the first NAND gate 6 falls to “L” level, the output of the third NAND gate 8 becomes “H”. To the "H" level, the Q output of the RS flip-flop 9 also changes to the "H" level, and the light emitting diode 11 is turned on. Time t ₃
Then, the timing signal CP ₀ falls to the “L” level, and even if the output of the third NAND gate 8 returns to the “L” level, the RS flip-flop 9 is maintained as it is, and the light emitting diode 11 is Continue to light up.

(4) When the cycle of the timing signal CP ₀ is shortened: When the cycle of the cycle T ₀ of the timing signal CP ₀ is shorter than that in the normal state and T ₀ <T ₂ (3), the time is When the timing signal CP ₀ falls at t ₄ , the S pulse signal CP ₂ rises, and when the timing signal CP ₀ rises to “H” level at time t ₅ , both inputs of the second NAND gate 7 are both “H”. The output of the third NAND gate 8 changes to "H" level because its output changes to "L" level, the Q output of the RS flip-flop 9 also changes to "H" level, and the light emitting diode 11 Lights up.

Next, at time t ₆ , the timing signal CP ₀ falls to the “L” level and the output of the third NAND gate 8 returns to the “L” level, but the RS flip-flop 9 remains unchanged. The state is maintained, and the light emitting diode 11 continues to be in a lighting state.

In this embodiment, the timing signal CP
The duty cycle of ₀ has been described as 50%.
The duty cycle value may be an appropriate value within a range in which the pulse monostable multivibrator 2 and the S pulse monostable multivibrator 3 can be monitored by the periods T ₁ and T ₂ . Further, even when the pulse width of the timing signal CP ₀ remains constant and only the cycle changes, it can be detected in exactly the same manner as when the pulse width changes.

[0022]

As described above, the present invention is triggered by a timing signal and a single first pulse generating means having a pulse width larger than the pulse width and smaller than one period width, and triggered by the timing signal. , And comparing the timing signal with these first and second pulse signals to generate a single second pulse having a pulse width smaller than the pulse width of the timing signal. Or it has a judging circuit for judging that its pulse width exceeds the control limit limited by the first or second pulse width, so that the abnormality of the timing signal can be immediately detected. ,
Therefore, there is an effect that the abnormality of the timing signal, that is, the abnormal operation of the microcomputer can be promptly known.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment.

FIG. 2 is a timing chart diagram.

[Explanation of symbols]

1 Microcomputer 2 L pulse monostable multivibrator 3 S pulse monostable multivibrator 4 Inverter 5 Inverter 6 1st NAND gate 7 2nd NAND gate 8 3rd NAND gate 9 RS flip-flop 10 Light emitting diode drive circuit 11 Light emission Diode 12 Power-on initial setting circuit 13 Momentary switch 14 Monostable multivibrator RESET Reset input terminal CP ₀ Timing signal CP ₁ L pulse signal NCP ₁ L pulse inversion signal CP ₂ S pulse signal QR Output of R-S type flip-flop R Input of RS flip-flop S Input of RS flip-flop

Claims (1)

[Claims] 1. A microcomputer which monitors a timing signal having a constant period and a pulse width output from a microcomputer and, when an abnormal state thereof is detected, judges that the operation of the microcomputer is abnormal and outputs a signal. An operation abnormality detection circuit, which is triggered by a timing signal and which generates a single first pulse having a pulse width larger than a pulse width of the timing signal and smaller than a period width; And a means for generating a single second pulse having a pulse width smaller than the pulse width of the timing signal, and the period of the timing signal is changed by inputting the timing signal, the first pulse signal and the second pulse signal. Or the pulse width of the timing signal is larger than the pulse width of the first pulse signal Alternatively, a microcomputer operation abnormality detection circuit having a determination circuit which determines that the operation of the microcomputer is abnormal and outputs a signal when the pulse width becomes smaller than the pulse width of the second pulse signal.