JPH0926838A - Power saving circuit for logic circuit by means of monitoring of power consumption - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the extreme reduction of the driving time of a system by monitoring the change of the total power consumption of the system, measuring a fixed time of power saving to produce a signal in response to the laps of time counted by a timer, and actuating the power saving means of a logic circuit based on the change of the power consumption. SOLUTION: A power consumption monitoring circuit 13 is placed between a system 11 and a battery 15 to monitor the power consumption of the system 11 and produces a start signal to a timer 14 when the power consumption of the system 11 exceeds its upper limit value. Thus the timer 14 is actuated by the start signal, and a power saving signal is produced to the power saving function 12 of a logic circuit when no reset signal is received for a fixed time. Receiving the power saving signal, the function 12 starts to save the power of the logic circuit. As a result, a stable driving time is secured and can be extended for the system 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is battery operated,
The present invention relates to a power saving circuit of a logic circuit in a computer having a function of executing a power saving function of the logic circuit according to an operating frequency and the number of clocks in one execution cycle.

[0002]

2. Description of the Related Art Conventionally, a power saving circuit for a logic circuit of a computer driven by a battery of this type has been performed by the system detecting IDLE (idle) from the logic circuit. When the power consumption is reduced, the power is saved, but when the power consumption of the entire system is high, the operation of suppressing the power is not performed.

Further, although individual power saving such as CPU, IC, memory, input / output device, peripheral device, etc. is carried out, these power saving functions are greatly involved in the setting state of the user, so that peripheral devices etc. The power consumption of the entire system does not have a constant value due to the expansion and operating state of the system, and the power used by the logical warmer does not have a constant value. (See, for example, JP-A-2-120919 and JP-A-3-123919)

In the power saving circuit in the conventional logic circuit, since the system detects the IDLE from the logic circuit to save power, if the IDLE cannot be detected, no power saving is required. If the system is not used and the system is excessively used, the power consumption is great and the battery drive time becomes extremely short, so that there is a problem that a stable drive time cannot be obtained. Further, there is a problem that the current supplied to the logic circuit does not have a constant value.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to make a driving time extremely short by operating a power saving function for a logic circuit depending on the state of power consumption even when the system cannot detect IDLE. Is to prevent the above-mentioned problem, to secure a stable driving time, and to extend the driving time. Therefore, in the power saving circuit of the present invention, a circuit for monitoring the power consumption of the entire system that changes depending on the addition of peripheral devices and the operating state is provided between the battery and the system, and the power consumption exceeds the upper limit value for a certain time or more. The above object is achieved by operating the power saving circuit of the logic circuit to reduce the power consumption in the case where it continues, and when it is below the lower limit and continues for a certain time or more.

[0005]

FIG. 1 is a block diagram showing an embodiment of the present invention. The system 11 is supplied with power from the battery 15 to operate, and has a power saving function 12 of a logic circuit. The power consumption monitoring circuit 13 is provided between the system 11 and the battery 15, monitors the power consumption of the system 11, and when the power consumption exceeds the upper limit value, the timer 14 performs S
When the TART signal is generated and the value falls below the upper limit value, the RESET signal is generated for the timer 14. Further, when the power consumption of the system 11 falls below the lower limit value, the timer 1
4, a START signal is generated, and when it exceeds the lower limit value, a RESET signal is generated (FIG. 2). Changes in the power consumption include, for example, the addition of peripheral devices and changes in the operating state, which are largely dependent on the user's setting, and it is difficult for the system to grasp the power consumption in advance. The power consumption monitoring circuit 13 is capable of detecting such a change in power.

The timer 14 operates the timer in response to the START signal generated from the power saving function 12 of the logic circuit and the power consumption monitoring circuit 13, and when the RESET signal is not received within a certain time, the power saving function of the logic circuit. Generate a POWER_SAVE signal for 12. When the RESET signal is received within a fixed time, the timer is initialized.

The power saving means 12 of the logic circuit receives the POWER_SAVE signal from the timer 14 to operate the power saving function of the logic circuit to save the power of the logic circuit to reduce the power consumption, and this is the upper limit value. If it is operated above, the operation at the maximum value of the current assigned to the logic circuit at this time is promoted (FIG. 3). The power allocated to the logic circuit depends on the power consumption of peripheral devices and the like, and is constantly changing. Further, if the power saving means 12 of the logic circuit is in a state in which the power saving function cannot be activated, it generates a START signal to the timer 14 to activate the timer again.

[0008]

As described above, the power saving system for the logic circuit by the power consumption monitoring according to the present invention performs the power saving from the state of the power consumption even if the IDLE cannot be detected, so that the driving time is extremely long. It is possible to prevent the driving time from becoming too short, to secure a stable driving time, and to extend the driving time.

Further, since the power saving function is operated even when the power consumption becomes high, there is an effect that the current supplied to the logic circuit can be used at the maximum value at that time.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a graph of one hour of power consumption according to an embodiment of the present invention.

FIG. 3 is a graph showing transition of power consumption in a logic circuit according to an example of the present invention.

[Explanation of symbols]

 11 system 12 power saving means for logic circuit 13 power consumption monitoring circuit 14 timer 15 battery

Claims (1)

[Claims] 1. A computer having a function of performing a power saving function of a logic circuit according to an operating frequency and the number of clocks in one execution cycle, which is driven by a battery, and is provided for a whole system by adding peripheral devices or operating states. A circuit that monitors changes in power consumption and generates a signal according to the state of illumination power, a timer that measures a certain time and generates a signal with the passage of time, and a power saving means for a logic circuit based on changes in power consumption A power saving circuit for a logic circuit by monitoring power consumption characterized by being activated.