JPH0573339B2 - - Google Patents
Info
- Publication number
- JPH0573339B2 JPH0573339B2 JP62272549A JP27254987A JPH0573339B2 JP H0573339 B2 JPH0573339 B2 JP H0573339B2 JP 62272549 A JP62272549 A JP 62272549A JP 27254987 A JP27254987 A JP 27254987A JP H0573339 B2 JPH0573339 B2 JP H0573339B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode pad
- semiconductor device
- base layer
- corrosion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000005260 corrosion Methods 0.000 claims description 37
- 230000007797 corrosion Effects 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 31
- 239000010931 gold Substances 0.000 claims description 29
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 18
- 229910052737 gold Inorganic materials 0.000 claims description 17
- 230000001681 protective effect Effects 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 23
- 239000010410 layer Substances 0.000 description 23
- 238000005530 etching Methods 0.000 description 14
- 239000007789 gas Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 7
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- 239000012528 membrane Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229960002050 hydrofluoric acid Drugs 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009396 hybridization Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の構造に係わり、特に腐
蝕性雰囲気中で使用可能な半導体装置の構造に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device, and particularly to the structure of a semiconductor device that can be used in a corrosive atmosphere.
半導体装置は従来シリコンウエハ上に酸化膜、
Al導体を形成し、この上にCr（またはTi）、Pd、
Auなどを順次積層して電極パツドを形成するこ
とが行われている。
Semiconductor devices traditionally have an oxide film on a silicon wafer.
Form an Al conductor, on which Cr (or Ti), Pd,
Electrode pads are formed by sequentially laminating Au and the like.
しかしながらこのような半導体装置において
は、腐蝕性雰囲気において、電極パツド部が腐食
し、Al導体が断線するという事態が発生するた
め、半導体装置は腐蝕性雰囲気に接触しないよう
封入されて使用される。ところがこのような形で
ハイブリツド化を図るとケースとか封入の構造な
ど高価なものとなり、近年の電子装置の低価格の
要求に応じることができない。
However, in such a semiconductor device, in a corrosive atmosphere, the electrode pad portion corrodes and the Al conductor is disconnected, so the semiconductor device is used in an enclosed state so as not to come into contact with the corrosive atmosphere. However, if this type of hybridization is attempted, the case and enclosure structure will become expensive, making it impossible to meet the recent demand for low-cost electronic devices.
この発明は上記の点に鑑みてなされ、その目的
は半導体装置の構造を耐触性に優れたものとする
ことにより、腐触性雰囲気で使用可能な半導体装
置を提供することにある。 The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor device that can be used in a corrosive atmosphere by making the structure of the semiconductor device excellent in corrosion resistance.
上記の目的はこの発明によれば半導体基板の主
表面に酸化膜、導体、電極パツドを順次形成して
なる半導体装置において、導電性耐蝕膜Ｉ４Ａお
よびその上に積層された金属膜４Ｂ，４Ｃとから
なる電極パツド下地層４と、この下地層の側面お
よび周縁部に形成された導電性耐蝕膜５と、下
地層のうちこの伝導性耐触膜に覆われていない
部分を除く半導体装置全表面に形成された絶縁性
耐蝕膜６とを備えることにより達成される。さら
に電極パツド下地層の表面に前記導電性耐蝕膜
に内接するように金の保護膜を形成することもで
きる。
According to the present invention, the above object is to provide a semiconductor device in which an oxide film, a conductor, and an electrode pad are sequentially formed on the main surface of a semiconductor substrate. An electrode pad base layer 4 consisting of an electrode pad base layer 4, a conductive corrosion-resistant film 5 formed on the side surfaces and periphery of this base layer, and the entire surface of the semiconductor device except for portions of the base layer that are not covered with the conductive corrosion-resistant film. This is achieved by providing an insulating corrosion-resistant film 6 formed on the surface. Furthermore, a gold protective film may be formed on the surface of the electrode pad underlayer so as to be inscribed in the conductive corrosion-resistant film.
電極パツド下地層４はシリコン基板１のコンタ
クトホールの上部にAl導体等に接して形成され
る。 The electrode pad base layer 4 is formed above the contact hole of the silicon substrate 1 in contact with an Al conductor or the like.
電極パツド下地層４はTiN層などの導電性耐
蝕膜４Ａと金属膜４Ｂ，４Ｃとから形成され
る。金属膜としてはPd膜４ＢとAu膜４Ｃの二重
膜あるいはそれぞれの単独膜等が用いられる。導
電性耐蝕膜は腐蝕性ガスを通さない。金属膜が
この膜の上に一時的に形成される導電性耐蝕膜
５のエツチング停止用に用いられる。 The electrode pad base layer 4 is formed of a conductive corrosion-resistant film 4A such as a TiN layer and metal films 4B and 4C. As the metal film, a double film of a Pd film 4B and an Au film 4C or a single film of each is used. Conductive corrosion-resistant membranes do not allow corrosive gases to pass through. A metal film is used to stop the etching of a conductive anti-corrosion film 5 which is temporarily formed on this film.
導電性耐蝕膜５が電極パツド下地層４の周縁
部と側面とに設けられる。この膜は腐蝕性ガスの
電極パツド側面および周縁部からの拡散を防止す
る。この膜は導電性耐蝕膜４Ａと同一の材料を
用いることができる。 A conductive corrosion-resistant film 5 is provided on the periphery and side surfaces of the electrode pad underlayer 4. This membrane prevents corrosive gases from diffusing from the sides and periphery of the electrode pad. This film can be made of the same material as the conductive corrosion-resistant film 4A.
金の保護膜７が電極パツド下地層４の上に導電
性耐蝕膜５に内接するよう設けられる。導電性
耐蝕膜は電極パツド下地層４の周縁部を被覆す
るのでこの被覆部の耐蝕膜側面に内接させる。
金の保護膜７は素子内部を保護するばかりでなく
金線等を接続する電極となるので所定の厚みに形
成される。 A gold protective film 7 is provided on the electrode pad base layer 4 so as to be inscribed in the conductive corrosion-resistant film 5. Since the conductive corrosion-resistant film covers the peripheral edge of the electrode pad base layer 4, it is inscribed in the side surface of the corrosion-resistant film of this coating.
The gold protective film 7 not only protects the inside of the element but also serves as an electrode for connecting gold wires and the like, so it is formed to a predetermined thickness.
絶縁性耐蝕膜６としては例えばSi3N4膜が用い
られる。この膜は金の保護膜７が形成されている
部分を除いて全表面に形成される。 As the insulating corrosion-resistant film 6, for example, a Si 3 N 4 film is used. This film is formed on the entire surface except for the area where the gold protective film 7 is formed.
電極パツドを拡散する腐蝕性ガスは導電性耐蝕
蝕膜とによつて阻止される。電極パツド以外
からの拡散は絶縁性耐蝕膜によつて阻止される。
Corrosive gases diffusing through the electrode pad are blocked by the conductive corrosion-resistant coating. Diffusion from sources other than the electrode pads is blocked by the insulating corrosion-resistant film.
次にこの発明の実施例を図面に基づいて説明す
る。第１図はこの発明の実施例に係わる半導体装
置の構造を示す要部模式断面図である。シリコン
基板１の上に酸化膜２が被着され酸化膜２のない
部分がコンタクトホールとなる。このコンタクト
ホールに接するAl導体３はシリコン基板内に形
成される阻止を相互に接続する配線である。コン
タクトホールの上部でAl導体３と接する電極パ
ツド下地層４はTiN膜４Ａ、Pd膜４Ｂ、Au膜４
Ｃが順次積層された構造である。TiN膜４Ａは
導電性耐蝕膜として腐蝕性ガスに耐え、その拡
散を防止し、下部のAl導体３を保護しかつ電気
信号を伝える。Pd膜４Ｂ、Au膜４Ｃ等の金属膜
はその上部に一旦形成されるTiN膜をエツチン
グで除去する際のエツチング停止の役目を果た
す。TiN膜は電気抵抗がAu膜などより高いので
耐蝕作用を認める範囲で厚さを薄くする必要があ
るが、TiN膜厚を薄く形成しておき、Pd膜やAu
膜を積層することによつてこれが実現される。こ
の実施例ではPd膜とAu膜を併用しているがいづ
れか一方だけでもよい。あるいはCu膜等を用い
ることもできる。
Next, embodiments of the present invention will be described based on the drawings. FIG. 1 is a schematic sectional view of a main part showing the structure of a semiconductor device according to an embodiment of the present invention. An oxide film 2 is deposited on a silicon substrate 1, and the portions without the oxide film 2 become contact holes. The Al conductor 3 in contact with this contact hole is a wiring that interconnects the blocks formed in the silicon substrate. The electrode pad base layer 4 in contact with the Al conductor 3 above the contact hole is made of a TiN film 4A, a Pd film 4B, and an Au film 4.
It has a structure in which C is sequentially laminated. The TiN film 4A serves as a conductive corrosion-resistant film that withstands corrosive gas, prevents its diffusion, protects the lower Al conductor 3, and transmits electrical signals. The metal films such as the Pd film 4B and the Au film 4C serve as an etching stop when the TiN film once formed thereon is removed by etching. Since the electrical resistance of TiN film is higher than that of Au film, etc., it is necessary to make the thickness as thin as possible to ensure corrosion resistance.
This is accomplished by stacking the membranes. In this example, a Pd film and an Au film are used together, but only one of them may be used. Alternatively, a Cu film or the like can also be used.
電極パツド下地層４の周縁部と側面を導電性耐
蝕膜としてのTiN膜５が被覆する。TiN膜５
は電極パツド下地層４の周縁部または側面からの
腐蝕性ガスの拡散を防止する。TiN膜は導電性
なので後述の金の保護膜７とよく結合する。 The peripheral edge and side surfaces of the electrode pad base layer 4 are covered with a TiN film 5 as a conductive corrosion-resistant film. TiN film 5
This prevents corrosive gas from diffusing from the periphery or side surface of the electrode pad underlayer 4. Since the TiN film is electrically conductive, it combines well with the gold protective film 7 described later.
金の保護膜７が電極パツド下地層４に接しかつ
TiN膜５の側面に内接するよう設けられる。金
の保護膜７は電極として機能し、金線が接続され
る。例えば電圧が金の保護膜７、Au膜４Ｃ、Pd
膜４Ｂ、TiN膜４Ａを経由してシリコン基板１
内のトランジスタ等の半導体素子に印加される。 The gold protective film 7 is in contact with the electrode pad base layer 4 and
It is provided so as to be inscribed on the side surface of the TiN film 5. The gold protective film 7 functions as an electrode to which a gold wire is connected. For example, the voltage is gold protective film 7, Au film 4C, Pd
Silicon substrate 1 via film 4B and TiN film 4A
The voltage is applied to semiconductor elements such as transistors inside the circuit.
絶縁性耐蝕膜としてSi3N4膜６が金の保護膜７
を除く素子の全表面を被覆する。これは腐蝕性ガ
スの拡散を防止し、素子内部を保護する。Si3N4
膜６は絶縁性なので電極パツドに所定の電気信号
を送ることができる。 The Si 3 N 4 film 6 serves as an insulating corrosion-resistant film and the gold protective film 7
Cover all surfaces of the device except for This prevents the diffusion of corrosive gases and protects the inside of the element. Si3N4 _
Since the membrane 6 is insulating, it is possible to send a predetermined electrical signal to the electrode pad.
導電性耐蝕膜とにTiN膜を、絶縁性耐蝕
膜にSi3N4膜を選び、上記のような装置構造とす
ると、材料間の整合性が良くなり、材料相互間の
密着性が良くなり素子の信頼性が高まる。 If a TiN film is selected as the conductive corrosion-resistant film and a Si 3 N 4 film is selected as the insulating corrosion-resistant film, and the device structure is configured as described above, the consistency between the materials will be good, and the adhesion between the materials will be improved. The reliability of the device increases.
上述のような構造においては装置表面が金の保
護膜あるいは絶縁性耐蝕膜でおおわれているため
腐蝕性ガスの素子内部への拡散が防止あるいは抑
制され、腐蝕性ガスが金の保護膜を拡散した場合
においても導電性耐蝕膜あるいはによつてそ
の内部への拡散が防止されるので半導体装置を腐
蝕性雰囲気中で使用することができ、電子装置の
コストダウンに寄与することができる。 In the structure described above, the surface of the device is covered with a gold protective film or an insulating corrosion-resistant film, which prevents or suppresses the diffusion of corrosive gases into the element, and prevents corrosive gases from diffusing through the gold protective film. Even in such cases, the conductive corrosion-resistant film prevents diffusion into the interior of the film, so that the semiconductor device can be used in a corrosive atmosphere, contributing to cost reduction of electronic devices.
上記のような半導体装置は次のようにして製造
することができる。第２図は装置製造の工程を示
す断面図である。シリコンウエハの表面が研磨さ
れ酸素を含む雰囲気中で約1000℃で熱処理され、
酸化膜が形成される。酸化膜の表面はレジストが
塗布されたあと電子線ビームが照射され、現像液
を用いて不要部分が取り除かれ所定パターンのレ
ジスト膜が形成される。フツ酸系のエツチング溶
液で酸化膜をエツチングし、第２図のａに示すよ
うなコンタクトホールを有する酸化膜２が得られ
る。このあとレジスト膜はドライエツチングで除
かれる。コンタクトホールは、シリコンが露出す
るので不純物の拡散処理が行われトランジスタの
ような半導体素子が形成される。次に圧力１×
10-5Torr、基板温度200℃に設定して電子ビーム
蒸着によりAl導体３が1μｍ厚に形成される。 The semiconductor device as described above can be manufactured as follows. FIG. 2 is a sectional view showing the process of manufacturing the device. The surface of the silicon wafer is polished and heat treated at approximately 1000℃ in an oxygen-containing atmosphere.
An oxide film is formed. After a resist is applied to the surface of the oxide film, it is irradiated with an electron beam, and unnecessary portions are removed using a developer to form a resist film in a predetermined pattern. The oxide film is etched with a hydrofluoric acid-based etching solution to obtain an oxide film 2 having contact holes as shown in FIG. 2A. After this, the resist film is removed by dry etching. Since silicon is exposed through the contact hole, an impurity diffusion process is performed to form a semiconductor element such as a transistor. Then pressure 1×
The Al conductor 3 is formed to a thickness of 1 μm by electron beam evaporation at a temperature of 10 −5 Torr and a substrate temperature of 200° C.
Al導体３の上には電極パツド下地層４が形成
される。この下地層のうちTiN膜４Ａがアルゴ
ンと窒素の混合雰囲気（N2／Ar＋N2）＝0.6）中
で反応性スパツタによつて半導体装置の全表面に
形成される。基板温度は200℃、パワーは2.5kw、
圧力８mmTorrである。Pd膜４Ｂ、Au膜４Ｃはい
ずれもAr雰囲気中でスパツタ蒸着される。これ
ら三つの膜は一つの槽の中で順次形成される。タ
ーゲツトはそれぞれTi、Pd、Auの各金属であ
る。膜の厚さはそれぞれ0.2μｍ、0.4μｍ、0.1μｍ
である。 An electrode pad base layer 4 is formed on the Al conductor 3. Of this underlayer, a TiN film 4A is formed over the entire surface of the semiconductor device by reactive sputtering in a mixed atmosphere of argon and nitrogen (N 2 /Ar+N 2 =0.6). Board temperature is 200℃, power is 2.5kw,
The pressure was 8 mmTorr. Both the Pd film 4B and the Au film 4C are sputter deposited in an Ar atmosphere. These three films are formed sequentially in one bath. The targets are Ti, Pd, and Au metals, respectively. The thickness of the membrane is 0.2μm, 0.4μm, and 0.1μm, respectively.
It is.
電極パツド下地層４は次に第２図のｂに示すよ
うに所定の形状に加工される。加工はAu膜４Ｃ、
Pd膜４Ｂ、TiN膜４Ａを同一の形状にエツチン
グすることによつて行われる。Au膜４Ｃのエツ
チングはNH4IとI2と水とエタノールを500対75対
2500対375（各重量部）の割合で含むエツチング溶
液が用いられる。0.1μｍを20秒で溶解する。Pd
膜４Ｂは塩酸と硝酸と酢酸を１対２対５（各重量
部）の割合で含むエツチング溶液が用いられる。
TiN膜４Ａは硝酸と酢酸とフツ酸を20対20対１
の割合で含むエツチング溶液が用いられる。30℃
において毎分500Å〜600Åのエツチング速度が得
られる。 The electrode pad base layer 4 is then processed into a predetermined shape as shown in FIG. 2b. Processing is Au film 4C,
This is done by etching the Pd film 4B and TiN film 4A into the same shape. For etching of Au film 4C, use 500:75 ratios of NH 4 I, I 2 , water and ethanol.
An etching solution containing 2500 to 375 parts by weight is used. Dissolves 0.1 μm in 20 seconds. Pd
For the film 4B, an etching solution containing hydrochloric acid, nitric acid, and acetic acid in a ratio of 1:2:5 (each part by weight) is used.
TiN film 4A uses nitric acid, acetic acid, and fluoric acid in a ratio of 20:20:1
An etching solution containing a proportion of . 30℃
Etching rates of 500 Å to 600 Å per minute are obtained.
エツチング加工の施された電極パツド下地層４
の上に第２図のｃに示すようにTiN膜５が形成
される。TiN膜５は前述のTiN膜４Ａと同一の
方法で0.2μｍ厚に半導体装置の全表面に形成され
る。 Etched electrode pad base layer 4
A TiN film 5 is formed thereon as shown in FIG. 2c. The TiN film 5 is formed on the entire surface of the semiconductor device to a thickness of 0.2 μm using the same method as the TiN film 4A described above.
TiN膜５は第２図ｄに示すように電極パツド
下地層４の側面が保護されるようにエツチング加
工が施される。TiN膜５のエツチングは電極パ
ツド下地層４の場合と同様である。 The TiN film 5 is etched so as to protect the side surfaces of the electrode pad underlayer 4, as shown in FIG. 2d. The etching of the TiN film 5 is the same as that of the electrode pad base layer 4.
エツチング加工の行われたTiN膜５の上に半
導体装置の全面にわたつてSi3N4膜６が形成され
る。Si3N4膜６はプラズマCVDの手法で1μｍ厚に
形成される。SiH4が30ml／分、NH3が300ml／
分、Arが60ml／分の流量で混合状態で流される。
基板の温度は380℃、パワーは800Wである。
Si3N4膜６を形成したあと第２図のｅに示すよう
にエツチング加工される。Si3N4膜６のエツチン
グはCF4と５％のO2の混合ガスを用い、ドライエ
ツチングを行う。TiN膜５のエツチングは電極
パツド下地層４の場合と同様である。TiN膜５
をエツチングすると、電極パツド下地層４の最上
層にあるAu膜４Ｃが露出され、そこでエツチン
グが停止する。 A Si 3 N 4 film 6 is formed on the etched TiN film 5 over the entire surface of the semiconductor device. The Si 3 N 4 film 6 is formed to a thickness of 1 μm using a plasma CVD method. SiH 4 is 30ml/min, NH3 is 300ml/min
minutes, Ar is flowed in a mixed state at a flow rate of 60 ml/min.
The temperature of the board is 380℃ and the power is 800W.
After forming the Si 3 N 4 film 6, it is etched as shown in FIG. 2(e). The Si 3 N 4 film 6 is etched by dry etching using a mixed gas of CF 4 and 5% O 2 . The etching of the TiN film 5 is the same as that of the electrode pad base layer 4. TiN film 5
When etching is performed, the Au film 4C on the top layer of the electrode pad base layer 4 is exposed, and the etching is stopped there.
次にメツキ処理により金の保護膜７が0.2μｍ厚
に形成される。金の保護層７は電極として金線が
ワイヤボンデイングされる。 Next, a gold protective film 7 is formed to a thickness of 0.2 μm by plating. A gold wire is wire-bonded to the gold protective layer 7 as an electrode.
この発明によれば半導体基板の主表面に酸化
膜、導体、電極パツドを順次形成してなる半導体
装置において、導電性耐蝕膜およびその上に積
層された金属膜とからなる電極パツト下地層と、
この下地層の側面および周縁部に形成された導電
性耐蝕膜と、前記電極パツド下地層のうちこの
導電性耐蝕膜に覆われていない部分を除く半導
体装置全表面に形成された絶縁性耐蝕膜とを備え
るので、腐蝕性ガスの半導体装置内部への拡散が
防止あるいは抑制される。さらに金の保護膜を電
極パツド下地層の表面に導電耐蝕膜に内接する
ように形成することにより腐蝕性ガスの半導体装
置内部への拡散の防止に一層効果的であるので、
半導体装置を腐蝕性ガス中で使用することが可能
となり電子装置のコストダウンが可能となる。
According to the present invention, in a semiconductor device in which an oxide film, a conductor, and an electrode pad are sequentially formed on the main surface of a semiconductor substrate, an electrode pad base layer consisting of a conductive corrosion-resistant film and a metal film laminated thereon;
A conductive corrosion-resistant film formed on the side surfaces and peripheral edges of the base layer, and an insulating corrosion-resistant film formed on the entire surface of the semiconductor device except for the portions of the electrode pad base layer that are not covered with the conductive corrosion-resistant film. Therefore, diffusion of corrosive gas into the inside of the semiconductor device is prevented or suppressed. Furthermore, by forming a gold protective film on the surface of the electrode pad underlayer so as to be inscribed in the conductive corrosion-resistant film, it is more effective in preventing corrosive gases from diffusing into the semiconductor device.
Semiconductor devices can be used in corrosive gases, making it possible to reduce the cost of electronic devices.
第１図はこの発明の実施例に係わる半導体装置
の要部模式断面図である。第２図はこの発明の実
施例に係わる半導体装置製造の工程を示す断面図
である。
１……シリコン基板、２……酸化膜、３……
Al導体、４……電極パツド下地層、４Ａ……
TiN膜（導電性耐蝕膜）、４Ｂ……Pd膜（金属
膜）、４Ｃ……Au膜（金属膜）、５……TiN膜
（導電性耐蝕膜）、６……Si3N4膜（絶縁性耐蝕
膜）。
FIG. 1 is a schematic sectional view of a main part of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a sectional view showing the process of manufacturing a semiconductor device according to an embodiment of the present invention. 1...Silicon substrate, 2...Oxide film, 3...
Al conductor, 4...electrode pad base layer, 4A...
TiN film (conductive corrosion-resistant film), 4B...Pd film (metal film), 4C...Au film (metal film), 5...TiN film (conductive corrosion-resistant film), 6...Si 3 N 4 film ( (insulating corrosion-resistant film).
Claims (1)
ツドを順次形成してなる半導装置において、導電
性耐蝕膜Ｉおよびその上に積層された金属膜とか
らなる電極パツド下地層と、この下地層の側面お
よび周縁部に形成された導電性耐蝕膜と、前記
下地層のうちこの導電性耐蝕膜に覆われていな
い部分を除く半導体装置全表面に形成された絶縁
性耐蝕膜とを備えることを特徴とする半導体装
置。 ２ 特許請求の範囲第１項記載の半導体装置にお
いて、前記電極パツド下地層の表面に前記導電性
耐蝕膜に内接するように金の保護膜を形成する
ことを特徴とする半導体装置。[Scope of Claims] 1. In a semiconductor device in which an oxide film, a conductor, and an electrode pad are sequentially formed on the main surface of a semiconductor substrate, the electrode pad is made of a conductive corrosion-resistant film I and a metal film laminated thereon. A base layer, a conductive corrosion-resistant film formed on the side surfaces and peripheral edges of the base layer, and an insulating layer formed on the entire surface of the semiconductor device except for portions of the base layer that are not covered with the conductive corrosion-resistant film. A semiconductor device comprising: a corrosion-resistant film. 2. The semiconductor device according to claim 1, wherein a gold protective film is formed on the surface of the electrode pad underlayer so as to be inscribed in the conductive corrosion-resistant film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27254987A JPH01115144A (en) | 1987-10-28 | 1987-10-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27254987A JPH01115144A (en) | 1987-10-28 | 1987-10-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01115144A JPH01115144A (en) | 1989-05-08 |
| JPH0573339B2 true JPH0573339B2 (en) | 1993-10-14 |
Family
ID=17515450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27254987A Granted JPH01115144A (en) | 1987-10-28 | 1987-10-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01115144A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AT409429B (en) * | 1999-07-15 | 2002-08-26 | Sez Semiconduct Equip Zubehoer | METHOD FOR ETCH TREATING SEMICONDUCTOR SUBSTRATES FOR THE EXPLOSION OF A METAL LAYER |
| JP2002289640A (en) * | 2001-03-27 | 2002-10-04 | Hitachi Chem Co Ltd | Wire-bonding connecting electrode structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5563842A (en) * | 1978-11-08 | 1980-05-14 | Nec Corp | Semiconductor device |
-
1987
- 1987-10-28 JP JP27254987A patent/JPH01115144A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5563842A (en) * | 1978-11-08 | 1980-05-14 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01115144A (en) | 1989-05-08 |
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