JPH057293A - Image processing system - Google Patents

Abstract

PURPOSE:To omit a memory for data output on the side of printing engine by performing a variable magnification processing in a subscanning direction while controlling an output corresponding to an arbitrary set magnification. CONSTITUTION:In a subscanning enlargement/reduction circuit 5, an operation mode register and ternary and quaternary counters are stored, and a 4/3 mode is provided which combines the quaternary counter and a repeated output, outputs current line data when the count value is 0 or 1 and repeatedly outputs the current line data when the counte value is 2 or 3, and a 2/3 mode is also provided which combines the ternary counter and a curtailed mode and outputs the current line data when the count value is 0 or 2 and skips the current line data without outputting them when the count value is 1. The curtailed or repeating signal corresponding to the prescribed magnification in the subscanning direction is outputted to a cyclic line buffer control circuit 34 for these modes. Thus, the enlargement/reduction in the subscanning direction can arbitrarily be set in the control circuit 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing system in which dot-expanded image data is subjected to a scaling process (including the same size) in the main scanning direction and the sub-scanning direction while serially outputting to the print engine side. The present invention relates to an image processing method capable of outputting to the print engine side without using a video memory.

[0002]

2. Description of the Related Art Conventionally, in a facsimile or image scanner, for example, a CCD functioning as an image reading unit is used.
The analog signal read by is digitized, and the image data that is dot expanded in the main scanning direction and the sub scanning direction can be transmitted to the receiver side. , In order to achieve consistency in print output size on the receiving side, after enlarging / reducing image data corresponding to the original image in main scanning and sub scanning,
It outputs it to the print engine side.

Further, in an apparatus using a laser printer or other page printer as a print engine on the receiving side, for example, on the transmitting side, in order to improve the reading speed and reduce the reading cost, it is generally about 8 dot (line) / mm. Scanning is performed with a coarse pixel density (normal mode), and the pixel density is changed (for example, 16dot / mm) in order to match the resolution of the printer when this is printed out on the receiver side The image data is configured to be output to the print engine side.

[0004]

When a laser printer is used for an engine as an output device in such a device, for example, the transmission image data is taken in (serial input) based on an operation clock (V clock) on the engine side. Is configured to perform the output (serial output). However, with this configuration, the scaling processing performed in the image processing apparatus thins or interpolates the pixels that form the transmission image data. , Even the above V
Even if the clock is frequency-divided or time-divided, it becomes impossible to print out the image data that has been subjected to the scaling processing with good consistency from the processing device.

Therefore, in the conventional apparatus, the memory for outputting data to the print engine side together with the buffer for the scaling process, more specifically, the memory after the scaling process is performed.
A video memory that can store the value image data is provided, and after the binary image data after the scaling process is temporarily stored in the video memory,
Although the V-clock is used for serial output to the print engine side, such a configuration tends to increase the memory capacity, increase the number of chips, and complicate the circuit configuration. Further, once storing the data that has been subjected to the scaling process in the video memory, the data output is likely to be delayed by that amount.

In view of the above-mentioned drawbacks of the prior art, the present invention is configured so that the image data after the scaling processing can be directly output to the print engine side without being temporarily stored in a video memory or the like, whereby the data can be output to the print engine side. An object is to provide an image processing method that can omit a memory for outputting. Another object of the present invention is to provide an image processing system capable of performing print output to the print engine side with good consistency even when performing thinning or interpolation or other scaling processing of the image data. . Another object of the present invention is to efficiently use the memory area of the scaling buffer without leaving a wasteful memory area even if the scaling processing of the image data is performed. Is to provide an image processing method capable of achieving a memory saving chip.

[0007]

In order to achieve the above technical object, the present invention performs a scaling process for each scanning direction when performing a scaling process on the image data constituting the transmission image and other original images. The first feature is that the scaling processing in the main scanning direction and the scaling processing in the sub-scanning direction of the original image data are sequentially performed via the buffer without performing the above processing simultaneously. That is, more specifically, after storing the image data obtained by scaling the original image data in the main scanning direction in a buffer having a memory area capable of storing image data of a plurality of scanning lines, at the time of reading from the buffer, The first feature is that the scaling processing in the sub-scanning direction is performed while controlling the output corresponding to an arbitrary set magnification.

The second characteristic is that the reading from the buffer is performed based on the operation timing on the print engine side. It should be noted that performing based on the operation timing includes the case where reading is performed in synchronization with the operation clock on the print engine side, but it does not indicate only this, but a read cycle in units of one scanning line is output by the print engine side. It suffices if it is synchronized with, and there is no particular problem even if it is asynchronous in pixel units. As such a configuration, particularly in the present invention, a shift register for smoothing the read data from the buffer is provided on the output side of the buffer, and the shift operation from the shift register is used as an operation clock on the print engine side. Data may be written to the empty area of the shift register asynchronously from the buffer via the bit register, for example, at the same timing and whenever an empty area of a predetermined bit is generated in the register, or vice versa. The configuration is preferable because the processing flexibility is increased. In this case, the buffer may be a cyclic buffer having a memory area capable of storing at least three scanning lines or more of processed data after the scaling processing in the main scanning direction because it is necessary to perform smoothing processing after reading the buffer. Although preferred, it is not limited thereto.

In the case of performing the scaling in the main scanning direction, generally, a reduction circuit for thinning out image data and an enlargement circuit for interpolating (increasing) the bit number of the data are provided, and these are selectively operated. Although it is configured to be switchable, such a configuration not only complicates the circuit configuration, but also makes it difficult to perform accurate scaling in the main scanning direction.

Therefore, according to the present invention, first, the image data corresponding to the original image is uniquely enlarged to m times corresponding to the maximum enlargement ratio, and then the enlarged image data is reduced corresponding to a predetermined reduction ratio. It is configured to do. As a result, the number of bits of the data to be the reference is expanded to m times, and the reduction process is performed with the expanded bit data as the reference, so that accurate scaling (reduction) is possible and the m-fold range is achieved. Since the enlargement processing and the reduction processing can be performed in the same processing, the circuit configuration is simplified. In the scaling process in the sub-scanning direction, the scaling process in the sub-scanning direction can be easily performed by thinning out or overlappingly outputting the image data corresponding to the read pixel stored in the cyclic buffer in correspondence with an arbitrary set scaling factor. It is possible.

[0011]

According to such technical means, the data stored in the buffer is subjected to the scaling processing in the main scanning direction, in other words, the scaling processing in the sub-scanning direction is performed at the time of reading the buffer. Since the thinning and interpolation in the scanning (serial) direction are not performed and the data is output as it is, the read cycle of the buffer for each scanning line can be easily synchronized with the output cycle on the print engine side. It is possible to directly output serially to the print engine side in synchronization with the operating clock.

Further, since the reading of the buffer may be considered in units of one scanning line, in other words, it is not always necessary to synchronize with the operation clock of the print engine side. Therefore, for example, a smoothing processing circuit or the like is provided on the output side of the buffer. There is no problem even if you intervene.

Therefore, according to the present invention, it is possible to perform the print output with good consistency while performing the scaling process and the smoothing process if necessary from the acquisition of the image data without using the above-mentioned video memory. Chip saving of video memory and the like is achieved.

Further, according to the present invention, since the scaling processing in the main scanning direction and the scaling processing in the sub scanning direction are sequentially performed individually, for example, even when a top margin or a left margin is set, one of the magnifications is not complicated in the circuit configuration. Can be easily changed to change the magnification (the magnification in the main scanning direction differs from that in the sub scanning direction). or,
Regarding the scaling processing in the sub-scanning direction, the scaling can be easily performed by simply controlling the output of data read from the buffer.

Since the buffer as described above stores line data, it is often constituted by a shift register. The shift register is I for each pixel line.
Since the chip is a C chip, when the smoothing process is performed on the reading side as described above, I corresponding to the number of reference pixel lines is used.
Requires C chip. Further, since the shift register requires a memory capacity corresponding to the maximum number of pixels subjected to enlargement processing, there is always an unused memory area in a normal use state, which not only leads to efficient use of memory, but also, for example, Even if three shift registers are used, the pixel data that can be stored is limited to the pixel line of interest and its preceding and succeeding pixel lines. For example, due to some circumstances on the output side, the output of the pixel of interest is temporarily suspended. In the case where it is necessary to read, the next-higher-order pixel line cannot be read, and as a result, the reading of the second-higher-order pixel line is made to wait or a fourth register or the like for storing the pixel line is required, This leads to an increase in IC chips and a complicated circuit configuration.

On the other hand, since the present invention uses the cyclic buffer, in other words, it is possible to easily call arbitrary image data by addressing the memory area for each corresponding line, which will be described later. The image signals corresponding to the read pixel and its preceding and next pixels are subjected to the read cycle in which the operation clock is time-divided for the smoothing process as well as the thinning process and the overlapping process for the scaling process in the sub-scanning direction. Based on this, it is possible to output accurately and surely.

Further, since the memory area for each line can be arbitrarily set by the address setting, there is no room for a useless empty area, and if there is an empty area, the next-higher-order pixel data is made to wait. It is possible to store sequentially without using, and as a result it is possible to avoid IC chip saving and complicated circuit configuration, and it is easy to achieve consistency with the discharge side, and print without using a video memory. Direct output to the engine side can be performed more reliably.

[0018]

Embodiments of the present invention will now be illustratively described in detail with reference to the drawings. However, the dimensions, materials, shapes, relative positions and the like of the components described in this embodiment are not intended to limit the scope of the present invention thereto, but are merely examples, unless otherwise specified. Not too much.

FIG. 1 is an overall block diagram showing an image processing apparatus according to an embodiment of the present invention. The structure of the image processing apparatus will be briefly described according to the flow of image data. The interface unit 1 has a parallel input I / F 11 and a serial input. I / F 12 and these are connected to the main scanning enlargement register 15 in a writable manner through a selector 13 that can be selectively switched based on a signal from the MPU I / F 10, for example.

The structure will be briefly described with reference to FIG. 2. Reference numeral 18 represents image data stored in, for example, a system memory 8 described later via a data bus based on a control signal from the DMA control circuit 14. A parallel in / out register that is input in parallel 16 bits at a time, 12 is a serial input in that serially inputs image data obtained by digitizing analog signals read by an image reading unit (not shown) along the main scanning line direction. In the parallel out register, the 16-bit data input to the respective registers 12 and 18 is automatically doubled in the main scanning direction by the logic circuit 13 having a selector function (parallel copying) to obtain 32-bit data. Is input to the shift register 15.

The bit data enlarged in the main scanning direction is serially input from the shift register 15 to the main scanning reduction unit 20. Reference numeral 16 is a data control unit for controlling the parallel copying.

The main scanning reduction unit 20 thins out the 32-bit data unconditionally doubled by the interface unit 1 in a predetermined designated mode to perform a scaling process of 0.25 to 1.0. As a result, the bit data output from the reduction unit 20 can be subjected to a scaling process of 2X (0.25 to 1.0), that is, 0.5 to 2.0 with respect to the original image.

The cyclic line buffer circuit 3 is shown in FIG.
As shown in, a RAM memory 31 having a memory area of 2 KW × 8 bits in which 8-bit data corresponding to one pixel can store the number of pixels corresponding to three main scanning lines, and the processing data is written in the memory. It consists of a memory write unit and a memory read unit that stores data in the scaling processing register in the sub-scanning direction while reading processing data from the memory.
Read / write is possible based on each clock of T3.

More specifically, the read of the RAM memory 31
/ Write is performed in units of 8 bits (1 byte). First, the input data that has been subjected to scaling processing in the main scanning direction is written at the timing of T0, while the output data is immediately before based on the signal from the shift register control circuit 47. Image data (n-
1) is read at the timing of T1, image data corresponding to the corresponding pixel (n) is read at the timing of T2, and further next pixel (n + 1) is read at the timing of T3. Is configured as follows.

In the figure, 34 is a cyclic line buffer control circuit, 35 is a write address designation register for the RAM memory 31, 36 is a read read address designation register, and 37 is a read / write address switching circuit.

Next, the structure of the memory write and read section will be described in detail. As shown in FIG. 4, the memory write section receives the image data from the main scanning reduction section 20 in the shift register 32 and outputs the data. Each time 1 bit (1 pixel) is stored, the data is once transferred to the write buffer 33 and the JKF / F (flip-flop) 38 is set. RA at the next T0 timing when JKF / F38 is set
The pixel data is written in the designated address area of the M memory 31, the JKF / F 38 is reset, and the address of the write address register 35 is incremented by one.

In the RAM memory 31, the pixel data is counted by the counter 39 for each input, and the image data of one line is the number of bits designated by the line pixel number designation register R (R: the number of pixels of one main scanning line). The bit data corresponding to the white pixel is added or truncated until it becomes.

Therefore, the RAM memory 31 always stores the image data of the number of bits corresponding to the number of pixels designated by the designation register 30. On the other hand, the memory read part
As shown in FIG. 5, the read buffer 4 of the RAM memory 31
The discharge of pixel data in 1a is grasped by the empty signal output from JKF / F47, and (n-1) at the timing of T1 to T3.
.. (n + 1) for three lines of pixel data are sequentially read and the address of the read address register 36 is incremented by +1.
The memory address corresponding to each line is (n-1) and (n + 1) from the read address register 36 corresponding to the n line.
An address for the line is created and the address switching circuit 37
The RAM memory 31 side is addressed via the.

The system control circuit 47 includes a 3-bit (2 ³ ) counter 47a which is counted each time the 19-bit shift registers 41 to 43 are shifted, and the J-KF / F 47b.
Each time a free area of 1 byte (8 bits) is generated by the shift operation of the shift registers 41 to 43 based on the operation clock on the print engine side, the pixel data in the RAM memory 31 is read via the read buffer 41a. Will be output.

Then, the data read from the read buffer by the address designation is transferred to the corresponding 19-bit shift registers 41 to 43, respectively. Shift register 41
Numerals 43 to 43 store the current line data and the line data of three lines before and after the current line data in units of 8 bits via the read buffers 41a to 43a. The shift registers 41 to 43 facilitate smoothing processing in the subsequent process. In order to store (8 + 11) -bit image data,
The data stored in is input to the smoothing logic 45 in parallel every 8 + α bits based on an instruction from the control circuit 47, and after performing a predetermined smoothing process in the logic 45,
The smoothed data is output to the output switching circuit 44 side based on the selection signal from the MPUI / F10. On the other hand, address writing in the read address register 36 is performed by outputting each output control signal output from the sub-scanning enlargement / reduction circuit 5 to the cyclic line buffer control circuit 34.

For example, the sub-scanning enlarging / reducing circuit 5 stores an operation mode register (not shown) and a quaternary and ternary counter. For example, when the quaternary counter and repetitive output are combined and the count value is 0 or 1, The current line data is output as it is, and when the count value is 2 or 3, the current line data is repeatedly output in the 4/3 mode, and the ternary counter and the decimation mode are combined. When the count value is 0 or 2, The current line data is output as it is, and when the count value is 1, the current line data is not output, and a 2/3 mode is provided in which skipping is provided.
By outputting a thinning-out or repetitive signal corresponding to a predetermined magnification in the sub-scanning direction to these modes to the cyclic line buffer control circuit 34, the control circuit 34 stores a read address register 35B in which an address corresponding to n lines is stored. , The address to be updated line by line, 1
An address signal that keeps the line skipped address or the current address output immediately before is appropriately generated, and by this, the reduction / enlargement in the sub-scanning direction can be arbitrarily set within the range of 0.5 to 4.0 times.

Further, in the operation mode register (not shown) in the sub-scanning enlargement / reduction circuit 5, a normal mode in which the image data after the scaling processing output from the 19-bit shift registers 41 to 43 in the n line is directly output, Further, an OR mode for outputting image data obtained by ORing the logic gates and a smoothing mode for selecting a signal from the smoothing logic 45 are stored. By outputting a mode selection signal from the register to the output switching circuit 44, normal output, OR output, unit division output Χu than smoothing logic 45, the X _L, video I / F6A appropriately selected output to it can to the print engine side through.

The smoothing logic 45 enlarges the sub-scanning /
A circuit used for smoothing the step of the shaded portion when performing the enlarging process in the reducing circuit 5. The predetermined smoothing process is performed based on the data stored in the shift registers 41 to 43, and the unit divided output Kaiu, outputs an X _L.

If the data after the enlargement or reduction processing is not directly output as it is, for example, only the enlargement / reduction or smoothing processing is performed, and if it is desired to perform the printout at a later date due to a piece of paper, confidential communication, or the like, the output is performed. 16-bit parallel conversion is performed from the switching circuit 44 via the serial signal conversion circuit 7A, and the parallel data is input to the system memory 8 via the parallel output I / F 7B.

Reference numeral 6B is a circuit for setting a top margin and a left margin based on a horizontal synchronizing signal and a vertical synchronizing signal from the engine side of the LBP, and the deviation control signal thereof is supplied to the sub-scanning enlargement / reduction circuit 5 and the smoothing logic circuit 45. Send to. Reference numeral 9 is a line enable signal generation circuit showing one line of the original image data fetched from the serial input I / F, 1
Reference numeral 0 is an MPUI / F generation circuit.

[0036]

As described above, according to the present invention, the image data after the scaling processing can be directly output to the print engine side, whereby the video memory for outputting the data to the print engine side can be omitted. Further, according to the present invention, even if thinning or interpolation of the image data or other scaling processing is performed, the scaling processing and the print output can be performed with good consistency from the acquisition of the image data.

Further, according to the present invention, even if the scaling process of the image data is performed, the memory region of the scaling buffer can be efficiently used without leaving a wasteful memory region, thereby saving A memory chip can be achieved. Further, according to the present invention, the enlargement magnification in the main scanning direction and the enlargement magnification in the sub-scanning direction can be set independently of each other, thereby enabling the demagnification processing when setting the top margin and the left margin.
It has various remarkable effects.

[Brief description of drawings]

FIG. 1 is an overall block diagram of an image processing apparatus according to an embodiment of the present invention,

FIG. 2 is a detailed block diagram of an interface unit,

FIG. 3 is a detailed block diagram of a cyclic line buffer circuit and a smoothing logic circuit.

FIG. 4 is a detailed block diagram of a memory write unit incorporated in a cyclic line buffer circuit.

FIG. 5 is a detailed block diagram of the output side of the cyclic line buffer circuit.

[Explanation of symbols]

3 Cyclic line buffer circuit 15-20 Main scanning enlargement / reduction circuit 5 Sub-scanning enlargement / reduction circuit 30 RAM memory

Claims (4)

[Claims] 1. An image processing method for serially outputting to a print engine side while performing scaling processing (including the same magnification) on original image data developed in a dot shape in a main scanning direction and a sub scanning direction, at least a main scanning. After storing the image data subjected to the scaling processing in the direction in a buffer having a memory area capable of storing image data of a plurality of scanning lines, the reading from the buffer is performed based on the operation timing on the print engine side, and the buffer is read. Image reading method for performing variable magnification processing in the sub-scanning direction while performing output control corresponding to an arbitrary set magnification when reading 2. A shift register for smoothing read data from the buffer is provided on the output side of the buffer, and the shift operation from the shift register is performed at the same timing as the operation clock on the print engine side. An image scaling method according to claim 1, characterized in that 3. The image scaling processing method according to claim 1, wherein the buffer is a cyclic buffer. 4. The scaling process in the main scanning direction uniquely enlarges the original image data to m times, and then reduces the enlarged image data in correspondence with a predetermined reduction ratio. Image scaling processing method described in 1.