JPH0571133B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention aims to reduce parasitic resistance and parasitic capacitance in a bipolar transistor having a heterojunction (heterojunction) to obtain a device structure suitable for ultra-high-speed operation. This relates to manufacturing technology.

(Prior art and its problems) A bipolar transistor that uses a semiconductor with a wide byde gap for the emitter can achieve both low base resistance and high emitter injection efficiency.
) It has the advantage of being able to reduce the emitter-base junction capacitance. Due to recent advances in heteroepitaxy technology in compound semiconductors, the AlGaAs/GaAs system (international
Electronics Device Meeting [IEDM] Technical Digest, 1981, 629
Page) and InAlAs/InGaAs systems (IEEE Electron Device Letter [Electron Device
[Lett.] Volume 4, 1983, p. 383), a device prototype was made. And so far, the delay time is 29.3 ps and the cutting frequency is 25 GHz (device
Research Conference [DRC] 1984, VA
-1 and VA-2).
Furthermore, those that use a heterojunction between the base and collector have even better characteristics (IEDN Technical Digest, 1983, p. 689).

In order to further improve the characteristics, it is necessary to suppress elements that are not essential to the operation of the device (parasitic elements) as much as possible. Parasitic elements include emitter-base parasitic capacitance, base-collector parasitic capacitance, and emitter-base parasitic resistance. Due to the basic device structure of bipolar transistors, it is difficult to eliminate these parasitic elements, but in order to achieve ultra-high-speed operation, it is necessary to search for structures and processes with fewer parasitic elements, similar to silicon bipolar transistors. .

The manufacturing process of a conventional heterojunction bipolar transistor will be explained using figures.

FIGS. 2A and 2B are diagrams for explaining the manufacturing process of a conventional heterojunction bipolar transistor, and are schematic cross-sectional views of a semiconductor device at each main step. In the figure, 1 is a single-crystal insulating semiconductor or an insulating film substrate, 2 is a collector layer made of a first semiconductor having one conductivity type, and 3 is a second semiconductor having a conductivity type different from that of the collector layer. 4 is an emitter layer made of a third semiconductor which has the same conductivity type as the first semiconductor and has a wider bandgap than the second semiconductor; 5 is a collector layer 2 and the emitter layer 4 is the base layer 2. An ion-implanted region containing impurities at high density so as to have the same conductivity type, 6 a collector electrode forming an ohmic contact with the collector layer 2, 7 a base electrode forming an ohmic contact with the base ion-implanted region 5, and 8 an ion-implanted region containing impurities at high density. An emitter electrode forming an ohmic junction with the emitter electrode 4 is shown. Further, the step of growing the collector layer 2, the base layer 3, and the emitter layer 4 as a single crystal on the substrate 1 involves implanting impurity ions from the surface of the emitter layer 4 to a part of the collector layer 2, including the base layer 3. The step of activating impurities by annealing is an etching step for exposing a part of the collector layer 2, i is the collector layer 2,
This is a step of forming and alloying a collector electrode 6, a base electrode 7, and an emitter electrode 8 on the surfaces of the ion implantation region 5 and the emitter layer 4, respectively.

Substrate 1 is a semi-insulating GaAs substrate, collector layer 2 is n-type Al _0.3 Ga _0.7 As, base layer 3 is p-type GaAs, and emitter layer 4 is n-type Al _0.3.
Problems in the conventional manufacturing process will be explained using Ga _0.7 As and Be as an impurity for forming the ion implantation region 5 to form a p-type semiconductor. In the Be ion implantation process, in order to obtain electrical contact from the surface to the p-type GaAs base layer 3, the surface n-type Al _0.3 Ga _0.7
This is done to convert a part of As into p-type. Since the ion implantation has a "sag" in the depth direction, the ion implantation region 5 generally reaches the collector layer 2. By annealing at 800 to 900° C. after Be ion implantation, the ion implanted region 5 becomes entirely a p-type semiconductor, and an ohmic junction between the p-type Al _0.3 Ga _0.7 As and the p-type GaAs base layer 3 is formed. However, at the same time, the p-type Al _0.3 Ga _0.7 As in the ion-implanted region 5 in the emitter layer
and the n-type Al _0.3 Ga _0.7 As emitter layer 4.
A pn junction is also formed between the p-type Al _0.3 Ga _0.7 As and the n-type Al _0.3 Ga _0.7 As collector layer 2 in the intra-collector layer ion implantation region 5 . These p-n junctions have no relation to the basic operation of the transistor and simply function as parasitic capacitances c _peb (emitter-base parasitic capacitance) and c _pbc (base-collector parasitic capacitance). The values of c _peb and c _pbc are the intrinsic emitter-base capacitance c _ieb and base-collector capacitance in the region related to the basic operation of the transistor.
Since it is about the same as or higher than c _ibc , it is a major factor in slowing down the transistor speed. Also _, n- _type Al _0.3
The n-type impurity concentration of the Ga _0.7 As emitter layer 4 and
Although it is better to increase the impurity (Be) concentration in ion implantation, increasing these impurity concentrations at the same time will lower the reverse breakdown voltage between the emitter and base. Therefore, it is necessary to keep the impurity concentration of either or both low.
It is difficult to make both r _pe and r _pb sufficiently small.

As mentioned above, with conventional manufacturing methods, it is difficult to sufficiently reduce the parasitic capacitances c _pcd , c _pbc and the parasitic resistances r _pe , r _pb , and it is impossible to realize ultrahigh-speed heterojunction bipolar transistors. Nakatsuta.

(Object of the Invention) An object of the present invention is to provide a method of manufacturing a semiconductor device that eliminates the above-mentioned drawbacks of the conventional method of manufacturing a heterojunction bipolar transistor and realizes ultrahigh-speed operation.

(Structure of the Invention) The present invention provides the following features:
In manufacturing a semiconductor device having a heterogeneous semiconductor junction between collectors, after a collector layer, a base layer, and an emitter layer are laminated in this order on a substrate, mesa etching is performed to leave the element area, selectively removing only the exposed portion of the base layer. A semiconductor device characterized by forming a semiconductor layer containing an impurity that has the same conductivity type as the base layer and is single crystal on the surface of the base layer and polycrystalline or amorphous on the surfaces of the emitter and collector layers. This is a manufacturing method.

According to the present invention, it is possible to manufacture a heterojunction bipolar transistor that has extremely small parasitic capacitances c _peb and c _pbc and parasitic resistances r _pe and r _pb and operates at ultra high speed.

(Example) A method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the drawings.

1A to 1D are diagrams for explaining the manufacturing process of a heterojunction bipolar transistor according to the present invention, and are schematic cross-sectional views of a semiconductor device at each main step. In the figure, the same numbers as in FIG. 2 are equivalent to those in FIG. 2 and perform the same functions. 9 is a contact region in which a fourth semiconductor containing impurities having the same conductivity type as the base layer 3 is grown as a single crystal; 10 is an insulating region in which the fourth semiconductor is grown as a polycrystalline or amorphous semiconductor. a is a step of growing a collector layer 2, a base layer 3 and an emitter layer 4 as single crystals on a substrate 1 in the same manner as in FIG. 2; b is a mesa etching step of exposing a part of the base layer 3 and collector layer 2 to the surface; c d is a step of cleaning only the surface of the base layer and growing a fourth semiconductor to form a single crystal connection region 9 and a polycrystalline or amorphous insulating region; d is a step of cleaning part of the collector layer 2 and emitter layer 4; This is a step of forming a collector electrode 6, a base electrode 7, and an emitter electrode 8 on the surfaces of the collector layer 2, connection region 9, and emitter layer 4, respectively, by exposing them to the surface.

Substrate 1 is a semi-insulating GaAs substrate, collector layer 2 is n-type Al _0.3 Ga _0.7 As, base layer 3 is p-type GaAs, and emitter layer 4 is n-type Al _0.3.
Ga _0.7 As, GaAs containing Be impurities as a fourth semiconductor, and a method for growing the fourth semiconductor
b using Molecular Beam Epitaxy (MBE)
Each process of ~d will be explained in detail.

In step b, the operating region of the transistor is left and p
n-type Al _0.3 to expose type GaAs base layer 3 to the side surface
Etch up to the Ga _0.7 As collector layer 2 using a sulfuric acid-based etching solution. The slope of the side surface at this time must be selected so as to allow single crystal growth of Be-containing GaAs in the next step c, and is preferably 45° or less with respect to the substrate 1 when MBE growth is used. A natural oxide film is attached to the surface after etching. In step c, first, only that part of the natural oxide film on the surface of the p-type GaAs base layer 3 is removed. This can be achieved by introducing this semiconductor device into an MBE device and heating it to about 630° C. while irradiating it with an As beam.
The reason for this is that the natural oxide film of GaAs evaporates at about 630°C, but the natural oxide film of Al _0.3 Ga _0.7 As does not evaporate. In this state, Be-containing GaAs
When grown by MBE, it becomes p-type with no native oxide film.
A single crystal of p-type GaAs grows on the surface of the GaAs base layer 3. On the other hand, n
Polycrystalline, high-resistance GaAs is formed on the surfaces of the collector layer 2 and emitter layer 4 of type Al _0.3 Ga _0.7 As. Therefore, a ground region 9 made of p-type GaAs with low resistance and forming an ohmic junction with base layer 3 and an insulating region 10 made of polycrystalline GaAs with high resistance are selectively formed. In step d, a portion of the insulating region 10 above the collector layer 2 and emitter layer 4 is removed by etching, and a collector electrode 6, a base electrode 7, and an emitter electrode 8 are formed and alloyed to complete a heterojunction bipolar transistor. The collector electrode 6 and emitter electrode 8 are made of AuGe/
Au, base electrode 7 is made of AuZn/An, etc., and the alloy is heated at 450°C for about 2 minutes.
A good ohmic contact can be formed.

According to the manufacturing method according to the present invention explained above,
Since a parasitic pn junction is not possible, the emitter-base and base-collector parasitic capacitance c _peb ,
c _pbc is almost negligible. In addition, the emitter layer 4
and the connection region 9 are insulated by the insulating region 10, so even if the respective impurity concentrations are increased, the dielectric strength voltage does not decrease, and it is possible to lower both the parasitic emitter resistance _rpe and the base resistance _rpb . can. Therefore, according to the present invention, a heterojunction bipolar transistor with few parasitic elements and capable of ultra-high speed operation can be obtained. Comparing the delay time between a heterojunction bipolar transistor according to the present invention and one fabricated by a conventional manufacturing method having the same layer structure, the delay time of the heterojunction bipolar transistor according to the present invention is approximately 100% lower than that of a conventional one having the same emitter area (25 μm ² ). Half delay time (15ps)
was gotten.

The present invention not only increases the operating speed, but also has the following advantages. One is that passivation of the device's operating area can be automatically performed. The operating area is completely protected from the outside by the connecting area 9 and the insulating area 10 in step c. Second, since there is no high-temperature heat treatment process such as annealing after ion implantation, redistribution of impurities in the emitter, base, and collector layers can be suppressed. Third, even if light is emitted due to carrier recombination within the operating region, this light is absorbed by the insulating region 10, so even if this device is integrated, there will be no light interaction between the devices. be.

In the embodiments of the present invention described above, AlGaAs/GaAs is used as the semiconductor material, but
InAlAs/InGaAs series InP/InAlAd series −
It is clear that it can be applied to other semiconductor material systems, including compound semiconductors. For selective cleaning of the surface of the base layer, a method may be used in which a film is formed on the surface by chemical treatment such as nitriding or curing instead of the surface oxide film, and then this film is selectively removed. Although heat treatment is shown as a method for selectively removing the surface oxide film, hydrogen plasma treatment, chemical etching, or sputtering may also be used. Furthermore, step a and step c
In addition to the MBE method, the semiconductor layer of
MOCVD (Metal Organic Chemical Vapor)
Obviously, other growth techniques may also be used, such as deposition, vapor phase growth, and liquid phase growth. The composition changes in the emitter layer, base layer, and collector layer may be within a range that allows selective cleaning of the surface in step c, and the doping amount may be changed in any manner. Although an insulating substrate is used as the substrate, a semiconductor having the same conductivity type as the collector layer may be used. In this case, the collector electrode can be formed on the back surface of the substrate.

(Effects of the Invention) In summary, by the method of manufacturing a semiconductor device of the present invention, parasitic capacitance and parasitic resistance can be significantly reduced, and an ultrahigh-speed heterojunction bipolar transistor can be obtained.

[Brief explanation of the drawing]

1A to 1D are schematic cross-sectional views of each main process for explaining the method of manufacturing a semiconductor device of the present invention, and FIGS. 2A to 2D are schematic cross-sectional views of each main process for explaining the prior art. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Collector layer, 3...Base layer, 4...Emitter layer, 5...Ion implantation region,
6...Collector electrode, 7...Base electrode, 8...
Emitter electrode, 9...connection area, 10...insulation area.

Claims (1)

[Claims] 1. In manufacturing a semiconductor device having dissimilar semiconductor junctions between an emitter and a base and between a base and a collector, after a collector layer, a base layer, and an emitter layer are laminated in this order on a substrate, mesa etching is performed to leave an element area and the base layer is By selectively cleaning only the exposed portions, a semiconductor layer containing impurities is formed that has the same conductivity type as the base layer, which is single crystal on the surface of the base layer and polycrystalline or amorphous on the surfaces of the emitter and collector layers. 1. A method of manufacturing a semiconductor device, characterized by forming a semiconductor device.