JPH0570157B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a display panel drive circuit suitable for use in liquid crystal display devices and the like. [Background of the Invention] In a display device such as a liquid crystal display device, a plurality of row electrodes and a plurality of column electrodes are arranged perpendicularly to each other on a display panel, and a pixel is formed at each intersection of the row electrode and column electrode. Display section (in liquid crystal display devices,
A liquid crystal display cell) is provided. For this,
The pixel display sections are arranged in a matrix. Each row electrode is connected to a row electrode drive circuit, and each electrode is connected to a column electrode drive circuit, and the row electrode drive circuit sequentially supplies one pulse (i.e., a scanning signal) to each row electrode, and each electrode is connected to a column electrode drive circuit. The electrode drive circuit samples a signal representing data to be displayed (ie, a data signal) every unit period and distributes it to each column electrode. The column electrode drive circuit supplies a data signal to the column electrode every time the row electrode drive circuit supplies a scan signal to the row electrode, and the row electrode to which the scan signal is supplied and the column to which the data signal is supplied at the same time. A data signal is supplied to the image display at the intersection with the electrode. In this way, data signals are supplied to the image display section line by line, and desired data is displayed. By the way, in such a display device, each time the row electrode drive circuit outputs one scanning signal, the column electrode drive circuit operates for a predetermined period (hereinafter referred to as a horizontal period).
The data signal of is sampled by the number of column electrodes,
Since these sampled data signals must be distributed to each column electrode, the column electrode drive circuit is required to operate faster than the row electrode drive circuit. In order to perform such high-speed operation,
Generally, the column electrode drive circuit is formed of a shift register, and the shift register also forms sampling pulses of data signals. A conceivable arrangement of the display panel drive circuits including such row electrode drive circuits and column electrode drive circuits is to integrate them into the display panel. However, in order to prevent the display panel from becoming bulky, it is preferable to form the shift register etc. with a thin film, but when the transistor is formed with a thin film, its operation speed is slow, and the operation speed of the shift register is also slow. I can't get the circuit. For this reason, the column electrode drive circuit must necessarily be provided separately from the display panel. However, if the column electrode drive circuit is provided separately from the display panel, column electrodes must be provided between them.
There are too many connection lines. Therefore, it is necessary to reduce the number of connection lines, and various methods have been proposed in the past.One example is to provide a switch matrix circuit in the column electrode drive circuit, and to apply this switch matrix circuit to the display panel. A system was proposed in which the number of connecting wires was reduced by installing them in one piece (Japanese Patent Application Laid-Open No. 1983-1999-1).
Publication No. 99394). The proposed display panel drive circuit will be explained below with reference to FIGS. 7 and 8. First, FIG. 7 is a circuit diagram showing an example of a switch matrix circuit in the column electrode drive circuit of the drive circuit, in which A ₁ to A _o are signal lines, B ₁ to _{B n} are control lines, and S ₁ to S _no is a switching transistor, H ₁ ~
H _no is the column electrode. In the same figure, m control lines B ₁ , B ₂ ,..., B _n
and n signal lines A ₁ , ..., A _o-1 , A _o are arranged in a matrix, and these control lines B ₁ , B ₂ ,
…, B _n and the signal lines A ₁ , …, A _o-1 , A _o are provided with switching transistors S ₁ , S ₂ , …, S _no , and each switching transistor S ₁ ,
Column electrodes H _{1 ,} H ₂ , ..., H _no are connected to each column electrode S 2 , ..., S _no . The signal lines A ₁ , ..., A _o-1 , A _o are connected to a data signal source (not shown), and the control lines B ₁ , B ₂ , ..., B _n are connected to a shift register (not shown). . The data signal source divides (samples) the data signal into n parts and outputs them in parallel every predetermined period (i.e., period of 1/m of the above-mentioned horizontal period), and these divided data signals are sent to each signal line.
Supplied to A ₁ , …, A _o-1 , A _o . Further, the shift register sequentially outputs control signals to control lines B ₁ , B ₂ , . . . , B _n . Therefore, when a control signal is now supplied to the control line B ₁ , the respective data signals from the signal lines A ₁ , ..., A _o-1 , A _o are sent to the respective switching transistors.
Column electrodes H ₁ ,…, H _o-1 , through S ₁ ,…, S _o-1 , S _o
The scanning _signal is supplied to n image display sections among the image display sections (not shown) along the row electrodes (not shown) to which the scanning signal is supplied. Next, when a control signal is supplied to the control unit B ₂ , the respective data signals from the signal lines A ₁ , ..., A _o-1 , A _o are
Switching transistors S _o+1 ,..., S _2o-1 , respectively
S _2o is further supplied to the next n image display sections along the row electrodes via column electrodes H _o+1 , . . . , H _2o-1 , H _2o . Thereafter, in the same manner, each time a control signal is sequentially supplied, each data signal from the signal lines A ₁ , ..., A _o-1 , A _o is transmitted to each of n image display sections along the same row electrode. When the control signal is supplied to the control line B _n , the data signal is supplied to the last n image displays along the same row electrode, and all image displays along one row electrode receive the data signal. Writing is complete. This operation is performed for each image display section of each row, and all images displayed on the display panel are written. Such a switch matrix circuit is provided integrally with the display panel, and the data signal source and shift register are provided separately from the display panel. For this reason, the number of connection lines connecting the display panel and the external circuit is the number n of signal lines A ₁ , ..., A _o-1 , A _o connecting the switch matrix circuit and the data signal source.
and the number m of control lines B ₁ , B ₂ , . . . , B _n connecting the switch matrix circuit and the shift register (n+m). In contrast, the column electrode
The number of H ₁ , H ₂ , ..., H _no is (n×m). Here, when m and n2, mnm+n, and the number of column electrodes (that is, the number of image display parts per row) is sufficiently large, so the number of connection lines between the display panel and the external circuit is It can be less than the number of column electrodes. In this case, assuming that the number of column electrodes is fixed, the number of connection lines is the minimum when the number of signal lines and control lines is the square root of the number of column electrodes, and the number of connection lines is the number of column electrodes. 2 of the square root of
It can be reduced to about twice as much. However, when the number of column electrodes is about 500, the connection wires are
The number of connection lines is about 46 (n=m=23), which is still a large number. FIG. 8 shows a so-called composite switch matrix circuit in which the switch matrix circuits shown in FIG. 7 _are individually connected in cascade, and each switch matrix circuit M ₁ , M ₂ , . _,1 ,
B _1,2 ; B _2,1 , B _2,2 ;...; B _,1 , B _,2 . For this purpose, any switch matrix circuit M _i (where i=1, 2,...,)
For each input signal line to which a data signal is supplied from the switch matrix circuit M _i+1 in the previous stage, two output signal lines are provided to supply the data signal to the switch matrix circuit M _i-1 in the next stage. Column electrode H ₁ for each output signal line of the switch matrix circuit M _i of the stage,
H ₂ ,... are connected. Therefore, in such a composite switch matrix circuit, the number of connection lines between the display panel and the external circuit is the control lines B _1,1 , B _1,2 , B _2,1 , B _2,2 , ...,
The sum (n+2) of the number 2 of B _,1 , B _,2 and the number n of signal lines A ₁ , ..., A _o , and the signal lines A ₁ ,
Since two column electrodes can be connected for every ..., A _o , the total number of column electrodes that can be driven is (n×2). Generally, each switch matrix circuit M ₁ ,
When M ₂ ,...,M each have m control lines, the number of connection lines is (n + m x), and the total number of driveable column electrodes is (n x m), but when m = 2, there is no connection. The lines will be the least. Now, as in the case of Fig. 7, the number of column electrodes is
Assuming about 500 pieces, n=4,=7 (or
n = 2, = 8), and the connecting wire is 18
The number of connection lines can be significantly reduced compared to the number of column electrodes. However, when seven stages (=7) or eight stages (=8) of switch matrix circuits are connected in cascade, the data signal must necessarily pass through seven or eight switching transistors S in this composite switch matrix circuit. , the total on-resistance of these switching transistors becomes very large, and as a result, the level of the data signal for driving the image display section must be increased, which increases the power consumption of the drive circuit. There are drawbacks. [Object of the invention] The object of the present invention is to eliminate the drawbacks of the above-mentioned prior art,
It is possible to significantly reduce the number of connection wires between the part provided integrally with the display panel and the part provided separately from the display panel, as well as the number of switches through which data signals pass. An object of the present invention is to provide a drive circuit for a display panel. [Summary of the Invention] To achieve this object, the present invention forms combinations of m to k control lines, associates one column electrode with each combination, and The feature is that n signal lines are associated with each combination, so that (n× _n C _k ) column electrodes can be provided with (n+m) connection lines. (Note that _n C _k is the total number of combinations when arbitrary k items are selected and combined from m items.) [Embodiments of the Invention] Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a main part configuration diagram showing a switch matrix circuit portion of an embodiment of a display panel drive circuit according to the present invention, in which A ₁ is a signal line, B ₁ , B ₂ , B ₃ ,
_B4 is a control line, _H1 , _H2 , _H3 , _H4 , _H5 , _H6 are column electrodes, and S is a switching transistor. In this example, to simplify the explanation, there is only one signal line A ₁ and control lines B ₁ , B ₂ , B ₃ , B ₄
There are four books. These four control lines B ₁ , B ₂ ,
When selecting and combining any two from B ₃ and B ₄ , the combinations are control lines B ₁ and B ₂ , B ₁ and B ₃ ,
There are six combinations: B ₁ and B ₄ , B ₂ and B ₃ , B ₂ and B ₄ , and B ₃ and B ₄ , and one column electrode is associated with each combination. That is, the column electrode H1 is connected to the signal line _A1 via two series-connected switching transistors S, which are controlled on and off by control signals supplied to the control lines _{B1 and B2 ,} respectively. , control lines B ₁ , B ₂
The column electrode H2 is connected to the signal line _A1 through two series-connected switching transistors S, _{each of} which is controlled on and off by a control signal supplied to the The column electrodes H ₃ , H ₄ ,
H ₅ and H ₆ are connected to signal line A ₁ . Therefore, the data signal from the signal line A ₁ is transmitted when the control signal is simultaneously supplied to the control lines B ₁ and B ₂ and the two switching transistors S are turned on (such operation is performed when the control lines B ₁ and B ₂ are selected). (hereinafter the same) is supplied to the column electrode H ₁ , and the control lines B ₁ , B ₂
When selected, it is supplied to column electrode _H2 , and below,
Control lines B ₁ and B ₃ , B ₁ and B ₄ , B ₂ and B ₃ , B ₂ and B ₄ , B ₃
and B ₄ respectively, the column electrodes H ₃ , H ₄ ,
Supplied to H ₅ and H ₆ . In this case, the control signals supplied to the control lines B ₁ , B ₂ , B ₃ , and B ₄ have the waveforms shown in FIG. Assuming that the signal line A ₁ is turned off at , the data signal from the signal line A 1 is distributed to the column electrodes H ₁ , H ₂ , H ₃ , . . . , H ₆ in this order, as shown in FIG. Here, when this switch matrix circuit is provided integrally with the display panel, the number of connection lines between this display panel and the external circuit is (4+1), and
The number of column electrodes is equal to the number of combinations of control lines, which is 1× ₄ C ₂ =6 from the law of combinations. Also, the data signal is always connected to the column electrode _H1 via two series-connected switching transistors.
~ _H6 supplied. When the number of signal lines is n, all combinations of the control lines described above are made to correspond to each signal line. As a result, if the number of control lines is 4, the number of connection lines is (n+4), and the maximum number of column electrodes that can be driven is n.
× ₄ C ₂ pieces. Furthermore, the number of control lines is m,
If any k control lines (k is an integer greater than or equal to 2) are combined, then according to the law of combinations, the number of combinations is _nCk , and the number of connection lines is (n+m), and the driving The maximum number of possible column electrodes is (n× _n C _k ), which can usually be larger than the number n×m of column electrodes in the conventional example shown in FIG. In this case, the number of switching transistors connected in series from the signal line to the column electrode is k. Note that the smaller k is, the smaller the number of switching transistors connected in series is. Figure 3 shows a more general version of the switch matrix circuit shown in Figure 1, with n signal lines and m control lines.
This figure shows an embodiment of a display panel drive circuit according to the present invention in which any two of these control lines are selected (k=2), and includes:
1 is a switch matrix circuit, 2 is a row electrode drive circuit, 3 is a pixel display section, 4 is a display panel, 5 is a frequency divider, 6 is a serial/parallel converter, 7 is a memory, A ₁ to A _o are signal lines, B ₁ to _{B n} are control lines, F ₁ to _{F n} and G ₁ to G _n are latch circuits, H ₁ to H _o and _n C ₂ are column electrodes, and V ₁ to V _p are row electrodes. In the same figure, row electrodes V ₁ to V _p and column electrodes H ₁ to H _o , _n C ₂ are arranged perpendicularly to each other on the display panel indicated by the dashed line, and pixels are displayed at the intersections of these row electrodes, respectively. Section 3 is provided. The row electrode drive circuit 2 consists of a shift register, and sequentially transfers the vertical scanning start signal V _start in synchronization with the clock pulse φ _V , and with this transfer, the row electrodes V ₁ , V ₂ , V ₃ ,
…, V _p are sequentially supplied with scanning signals. The column electrode drive circuit consists of a shift register composed of latch circuits F ₁ to _{F n} , a shift register composed of latch circuits G ₁ to _{G n} , and a switch matrix circuit 1. Operates in synchronization with _φC . The serial-to-parallel converter 6 and the memory 7 constitute a data signal source, and the serial-to-parallel converter 6 divides the data signal Data into n parts every predetermined period of the horizontal period and outputs them in parallel based on the clock pulse _φH . The memory 7 stores n divided data signals from the serial/parallel converter 6 for each clock pulse φ _C from the frequency divider ₅ , and
The signals are held for a period of time and output to the respective signal lines A ₁ , ..., A _o . Frequency divider 5 divides the frequency of clock pulse φ _H by n and outputs clock pulse φ _C. Therefore, the period of the clock pulse φ _C is equal to that of the serial/parallel converter 6.
is equal to the predetermined period in which the data signal Data is divided into n parts. The row electrode drive circuit 2 and the switch matrix circuit 1 of the column electrode drive circuit are integrally provided on the display panel 4. The switch matrix circuit 1 is connected to the memory 7 by signal lines A ₁ to A _o , and
It is connected to latch circuits F ₁ -F _n and latch circuits G ₁ -G _n by control lines B ₁ -B _n . For this,
The number of connection lines between the display panel 4 and the external circuit is (n+m). Moreover, in the switch matrix circuit 1,
The signal lines A ₁ , ..., A _o are connected to the column electrode H ₁ through two switching transistors S connected in series, respectively.
The _{two series} -connected switching transistors S are turned on _and off by control signals from different control lines, respectively. To explain this configuration in more detail, the first n column electrodes H ₁ , H ₂ , ..., _Ho are connected to control lines, respectively.
are turned on and off by the control signals supplied to B ₁ and B ₂ , respectively.
The signal lines A ₁ , A ₂ , ..., are connected through two series-connected switching transistors S that are turned off.
A _o and the next n column electrodes H _o+1 , H _o+2 ,
..., H _2o are connected to signal lines A ₁ and A via two series-connected switching transistors S, which are controlled on and off by control signals supplied to control lines B ₁ and B ₃ , respectively. ₂ ,…, connected to A _o , below,
The combinations of two control lines are made different for every n column electrodes. Therefore, when selecting and combining any two control lines from m control lines, the number of combinations is _n C ₂ , and therefore, driving is possible when using n signal lines. The maximum number of column electrodes is n× _n
It becomes C ₂ . This number _n C ₂ of column electrodes can be larger than the number n×m of column electrodes shown in FIG. Further, the number of switching transistors connected in series is two. Next, the operation of the column electrode drive circuit shown in FIG. 3 will be described using FIG. 4 showing signal waveforms at various parts in FIG. 3. In addition, latch circuits F ₁ to F _n and latch circuits
G ₁ -G _n are so-called edge trigger type latch circuits, which take in data at the rising edge of the clock pulse "0" to "1". When the horizontal scanning start signal Hstart is input in synchronization with the clock pulse φ _C from the frequency divider 5, the latch circuits F ₁ and G ₁ are set, and the other latch circuits F ₂
~ _Fn , _G2 ~ _Gn are reset. For this,
Q outputs F ₁ (Q) and G ₁ (Q) of latch circuits F ₁ and G ₁ become “1”, and Q outputs of other latch circuits become “0”.
becomes. These F ₁ (Q) and G ₁ (Q) are supplied as control signals to the control lines B ₁ and B ₂ , respectively, and as a result, the data signal on the signal line A ₁ is transferred to the column electrode H ₁ and the data signal on the signal line A _2. The data signal is supplied to the column electrode H ₂ , and the data signal of the signal line A _o is supplied to the column electrode H _o , respectively. At this time,
Assuming that a scanning signal is supplied to the row electrode V ₁ ,
A data signal is supplied to each pixel display section 3 at the intersection of the row electrode V ₁ and the column electrodes H ₁ , H ₂ , . . . , _Ho . At the rising edge of the first clock pulse _φc after the horizontal scanning start signal Hstart (at this time, memory 7
(in which the next n data signals are stored) The latch circuit F ₂ takes in "1" F ₁ (Q), and at the same time, the latch circuit F ₁ takes in "0" data. In other words, data “1” is the latch circuit F ₁
is shifted to latch circuit _F2 . For this,
The Q output F ₂ (Q) of the latch circuit F ₂ becomes “1”,
The Q outputs of other latch circuits F ₁ , F ₃ , ..., F _n are "0"
It is. This F ₂ (Q) is connected to the control line B ₃ as a control signal.
As a result, the Q output of latch circuit _G1
Since G ₁ (Q) is held at "1" and a control signal is supplied to the control line B ₁ , the data signal on the signal line A ₁ is transferred to the column electrode H o+1, and the data signal on the signal line A ₂ is transferred to the column electrode H _o+1. The signal is supplied to the column electrode H _o+2 , and the data signal of the signal line A _o is supplied to the column electrode H _2o , respectively. Similarly, data of "1" is transmitted to the _latch circuits F ₃ , F ₄ ,
_The control lines are _{shifted in} the order _of . Then, after the Q output F n _{-1 (Q) of the latch circuit F n- 1} becomes "1", when the clock pulse φ _C is supplied, the Q output G ₁ (Q) of the latch circuit G ₁ becomes "1". 1", the latch circuit _F2 takes in Fn _-1 (Q) of "1" at the rising edge of the clock pulse _φC . At the same time, the latch circuit F _n also takes in F _n-1 (Q), but the Q output F _n (Q) of this latch circuit F _n
becomes the clock pulse of the latch circuits _G1 to _Gn ,
As a result, the latch circuit G ₂ is "1" at the rising edge of F _n (Q), and the Q output G ₁ (Q) of the latch circuit G ₁ is
Also, the latch circuit _G1 takes in "0" data. Therefore, the Q output G ₂ (Q) of the latch circuit G ₂ becomes “1”, and the other latch circuits
G ₁ , G ₃ , ..., G _n become "0". Therefore, the Q output G ₂ (Q) of the latch circuit G ₂ is supplied to the control line B ₂ as a control signal. On the other hand, data "1" is shifted in the order of latch circuits F ₂ , F ₃ , . . . at every rising edge of clock pulse φ _C .
As a result, the control lines are selected in the order of B ₂ and B ₃ , B ₂ and B ₄ , . . . , and at the same time, the number of column electrodes to which data signals are further supplied is shifted one by one. Then, the data "1" is shifted to the latch circuit F _n-1 , and then when the clock pulse φ _C is supplied, the data "1" is shifted to the latch circuit F n-1.
is shifted from G ₂ to latch circuit G ₃ , and then
Data "1" is shifted in the order of latch circuits F ₃ , F ₄ , . . . . In this way, “1” in the latch circuits F ₁ to F _n
Data shift and latch circuit “1” at G ₁ to G _n
By shifting the data, the combination of control lines selected from among the control lines B ₁ to B _n changes, thereby shifting the number of column electrodes to which data signals are supplied by n lines. Then, the data of “1” is the final stage latch circuit.
When the data of "1" is shifted to the final stage latch circuit _Fn , the supply of data signals to all the pixel display sections 3 of one row is completed _, and then the row electrode drive circuit 2 supplies a scanning signal to the row electrode _V2 , and a horizontal scanning start signal Hstart is input, and the above series of operations is performed again to supply data to the pixel display section 3 of the next row. Similarly, the above operation is repeated every time a scanning signal is supplied to _the row electrodes V ₃ , V ₄ , . Once completed, the vertical scanning start signal Vstaet is supplied to the row electrode drive circuit 2 again, and the above operation is repeated. FIG. 5 is a block diagram of main parts showing another embodiment of the display panel drive circuit according to the present invention. In this embodiment, the number of switching transistors connected in series is three, and the operation is similar to the embodiment shown in FIG. 3, with m control lines and m signal lines. n numbers (in the figure, n=
2), the maximum number of column electrodes that can be driven is n×
_n C ₃ , and compared to the conventional example shown in FIG. 7, there is a possibility that the number of column electrodes can be increased if the number of connection lines is the same. Generally, when the number of switching transistors connected in series is k, it can be easily inferred that the maximum number of column electrodes that can be driven is n× _n C _k . Here, from the combinational relationship, _n C _k = _n C _nk
Therefore, it is not only meaningless to set the number k of switching transistors connected in series to more than half the number of control lines m/2, but also because the total on-resistance of the switching transistors connected in series is It's getting bigger and I don't like it. Therefore,
Set k to 2km/2. Also, from this, the distance is 4 m. FIG. 6 shows a comparison between the above embodiment and the prior art regarding the relationship between the maximum number of driveable column electrodes and the number of connection lines. 12 is based on the prior art shown in FIG.
Line 13 corresponds to the conventional technique shown in FIG. 8 when the number of switching transistors connected in series is two, line 14 corresponds to the embodiment shown in FIG. 3, and line 15 corresponds to the example shown in FIG. Each of them relates to the embodiments shown. As is clear from FIG. 6, assuming that the maximum number of driveable column electrodes, that is, the maximum number of column electrodes are equal, the embodiment shown in FIG. If the number of row electrodes can be reduced and the maximum number of row electrodes is 300 or less,
Furthermore, the number of connection lines can be reduced compared to the conventional technique shown in FIG. In the conventional technology shown in Fig. 8, even if the maximum number of column electrodes is 300 or less,
Even if the number exceeds 300, the number of switching transistors connected in series will be greater than in the embodiment shown in Fig. 3, but the maximum number of column electrodes is set to 2, as in the embodiment shown in Fig. 3. In this case, as is clear from a comparison of lines 13 and 14, the number of connected lines is smaller in the embodiment shown in FIG. Further, in the embodiment shown in FIG. 5 in which the number of switching transistors connected in series is three, the total on-resistance becomes slightly larger, but the number of connection lines is further reduced. The following table shows the number of connection lines, the number of switching transistors connected in series, and examples of each of the above-mentioned prior art and each of the above-mentioned embodiments when the maximum number of column electrodes is about 500.

〔Effect of the invention〕

As explained above, according to the present invention, both the number of connection lines between the display panel and external circuits and the number of switching transistors through which data signals are supplied to column electrodes can be reduced. An excellent effect can be obtained in that the column electrodes can be driven.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts showing an embodiment of a display panel drive circuit according to the present invention, FIG. 2 is a waveform diagram showing signals of each part of FIG. 1, and FIG. FIG. 4 is a waveform diagram showing the signals of each part of FIG. 3; FIG. 5 is a main part configuration diagram showing another embodiment of the display panel drive circuit according to the present invention; FIG. The figure is an explanatory diagram showing the relationship between the maximum number of column electrodes and the number of connection lines, and FIGS. 7 and 8 are main part configuration diagrams showing examples of conventional display panel drive circuits, respectively. A ₁ ~ _{A o} ... Signal line, B ₁ ~ _{B n} ... Control line, S...
...Switching transistor, H ₁ ~ H _o , _n C ₂ ...
Column electrode, _V1 to _Vp ...Row electrode, 1...Switch matrix circuit, 2...Row electrode drive circuit, 3...Pixel display section, 4...Display panel.

Claims (1)

[Claims] 1 On a display panel in which a plurality of row electrodes and a plurality of column electrodes are arranged perpendicularly to each other, and a pixel display section is provided at each intersection of the row electrode and the column electrode, n ( However, m data signals (however, m
4) In a display panel drive circuit provided with a switch matrix circuit that selectively supplies a predetermined column electrode under the control of a control signal supplied through However, if any one of the signal lines is
and connects different control lines to the k switches to enable separate on/off control; A display panel drive circuit characterized in that the control lines connected to each of the switches are configured to have different combinations.