JPH056905A - Field-effect semiconductor device - Google Patents

Abstract

PURPOSE:To achieve that electrons passing directly under a gate electrode in the operation of an element reduce a noise generated when they are passed through a channel layer doped with impurities at a high concentration and to sharply enhance a noise factor. CONSTITUTION:The following are provided on a semiconductor substrate 10: a buffer layer 4 composed of a first semiconductor an undoped channel layer 3 composed of a second semiconductor whose electron affinity is larger than that of the first semiconductor; a channel layer 2 composed of a third semiconductor whose electron affinity is larger than that of the first semiconductor; a fourth semiconductor layer 1 whose electron affinity is smaller than that of the second and third semiconductors; and a cap layer 5 composed of a fifth semiconductor. A field-effect semiconductor device is formed by forming the following: one pair of electrodes 6, 7 connected to the cap layer 5; and a gate electrode 8 arranged and installed on the fourth semiconductor layer 1 inside the electrodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect semiconductor device.

[0002]

2. Description of the Related Art As the demand for satellite broadcasting receiving systems has increased, attention has been focused on the performance factories of ultra-low noise field-effect transistors, which are an important part of this system. To improve the performance of these transistors, shortening the gate length and increasing the transconductance are essential conditions. Therefore, a field effect transistor in which the channel layer is heavily doped with impurities has been proposed.

FIG. 3 is a sectional view showing the structure of a conventional field effect transistor of this type.

In FIG. 3, 10 is a semi-insulating GaAs substrate, 4 is a buffer layer formed on the substrate 10 and also serves as a barrier layer made of a GaAs semiconductor, and 2 is an n-type impurity provided on the buffer layer 4. Is a heavily doped n-type InGaAs semiconductor channel layer, 1 is an n-type AlGaAs semiconductor layer provided on the channel layer 2, 5
Is a cap layer made of an n-type GaAs semiconductor provided on the n-type AlGaAs semiconductor layer 1.

Reference numeral 6 is a source electrode connected to one cap layer 5, 7 is a drain electrode connected to the other cap layer 5, and 8 is an n-type AlG between the source electrode 6 and the drain electrode 7.
It is a gate electrode that is in Schottky connection with the aAs semiconductor layer 1.

[0006]

However, in a field effect transistor such as the field effect transistor shown in FIG. 3, which uses a channel layer doped with a high concentration of impurities, the gate length is shortened and the transconductance is reduced. Even if you try to increase
There is a problem that the noise figure during high frequency operation is hardly reduced.

This is because in the field effect transistor, when the device operates, the electrons passing directly under the gate electrode 8 pass through the channel layer 2 in which impurities are doped at a high concentration to generate noise. Is believed to be.

An object of the present invention is to solve the above-mentioned problems and to significantly improve the noise figure.

[0009]

According to the present invention, a buffer layer made of a first semiconductor, an AND channel layer made of a second semiconductor having an electron affinity higher than that of the first semiconductor are provided on a semiconductor substrate. A channel layer made of a third semiconductor having an electron affinity higher than that of the first semiconductor, a fourth semiconductor layer having an electron affinity lower than those of the second and third semiconductors, and a cap layer made of a fifth semiconductor, A pair of electrodes connected to the cap layer and a gate electrode arranged in the fourth semiconductor layer in the electrodes are provided.

[0010]

According to the present invention, when the device is in operation, the electrons passing directly under the gate electrode pass through the channel layer of the AND, so that the generation of noise is suppressed.

[0011]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a schematic view of a conductor band structure immediately below a gate electrode of the present invention.

The same components as those in FIG. 3 are designated by the same reference numerals.

As shown in FIG. 1, 10 is a semi-insulating Ga.
The As substrate 4 is a buffer layer which also serves as a barrier layer made of a GaAs semiconductor.

Reference numeral 3 is a channel layer, which is a feature of the present invention, and is made of an In-deep InGaAs semiconductor having an electron affinity higher than that of the GaAs semiconductor of the buffer layer 4, and is provided on the buffer layer 4.

Reference numeral 2 denotes a channel layer formed of an n-type AlGaAs semiconductor layer in which an n-type impurity having a higher electron affinity than the GaAs semiconductor of the buffer layer 4 is doped at a high concentration, and is provided on the channel layer 3.

An n-type AlGaAs semiconductor layer 1 having a smaller electron affinity than the channel layers 2 and 3 is provided on the channel layer 2, and a cap layer 5 made of an n-type GaAs layer is provided on the n-type AlGaAs 1. Further, the source electrode 6 connected to the one cap layer 5, the drain electrode 7 connected to the other cap layer 5, the source electrode 6 and the drain electrode 7
Gate electrodes 8 that are in Schottky connection with the n-type AlGaAs semiconductor layer 1 between are provided respectively, and the field effect transistor according to the present invention is formed.

As described above, the feature of the present invention resides in that the channel layer 3 made of In-doped InGaAs is inserted between the buffer layer 4 and the channel layer 2. The conductor band structure immediately below the gate electrode 8 of the field-effect transistor thus formed is as shown in FIG. Here, the numerical values in the figure are approximate values obtained by calculation.

A first concrete example of the present invention will be described.

N-type GaAs forming the cap layer 5
The n-type impurity concentration of the semiconductor layer is set to n = 3 × 10 ¹⁸ cm ⁻³ , and the film thickness is set to 800 Å.

Further, to set the n-type impurity concentration of the n-type AlGaAs semiconductor layer 1 to ^{n = 1 × 10 18 cm -3} , the film thickness and 300 Å.

The channel layer 2 is made of n-type In _x Ga _1-x As.
(X is an In composition parameter), and the impurity concentration thereof is set to n = 2.5 × 10 ¹⁸ cm ⁻³ .

The channel layer 3 is made of In-doped In _x Ga.
_1-x As (x is an In composition parameter).

The channel layer 2 having an In composition parameter x of 0.15 and a film thickness of 50 Å is defined as a group A, and I
A group B having an n composition parameter x of 0.15 and a film thickness of 100 Å is a group B, and an In composition parameter x = 0.20 and a film thickness of 50 Å is a group C.

The composition of the In composition parameter x of the channel layer 3 is the same as that of the above-described group of the channel layer 2, and the film thickness D of the In-doped In _x Ga _1-x As is 0, 20Å, 50.
The semiconductor layers of the above sample were grown by the MBE method while changing the thicknesses of Å, 100 Å, 120 Å, and 150 Å to prepare field effect transistors having a gate length of 0.2 μm.
Each of the field effect transistors is set to 12 GHz (Vds
= 2V, Ids = 10 mA) minimum noise figure NFmi
The results of comparing n are shown in Table 1.

[0025]

[Table 1]

From Table 1, the conventional structure shown in FIG. 3 (D = 0
Å), NFmin is around 1.0.

On the other hand, the structure of the present invention, that is,
It can be seen that the performance is significantly improved in the case where the AND channel layer 3 is inserted between the buffer layer 4 and the channel layer 2.

Further, in the first specific example, since the performance deteriorates again when the film thickness of the channel layer 3 exceeds 100 Å, the film thickness of the channel layer 3 is preferably 100 Å or less.

Next, a second specific example of the present invention, which is superior in performance to the first example, will be described.

N-type GaAs forming the cap layer 5
The n-type impurity concentration of the semiconductor layer is set to n = 3 × 10 ¹⁸ cm ⁻³ , and the film thickness is set to 800 Å.

Further, to set the n-type impurity concentration of the n-type AlGaAs semiconductor layer 1 to ^{n = 1 × 10 18 cm -3} , the film thickness and 300 Å.

The channel layer 2 is an n-type In_xGa_1-xAs
(X is an In composition parameter). And Cha
In composition parameter x of the channel layer 2 is 0.15, n-type impurity
N = 2.5 × 10¹⁸cm^-3, Channel layer 2 and
The total film thickness of 3 was set to 150 Å and the group D was used.
The composition parameter x is 0.20, and the n-type impurity concentration is n = 2.
5 x 10¹⁸cm^-3, The total thickness of the channel layers 2 and 3 is 1
50 Å is set as the E group, and the In composition parameter x is
0.15, n-type impurity concentration n = 4 × 10¹⁸cm ^-3, J
The total film thickness of the channel layers 2 and 3 is set to 150 Å and F
In composition parameter x is 0.15, n-type impurity
Concentration n = 2.5 × 10¹⁸cm^-3, Channel layers 2 and 3
The group G having a total film thickness of 100 Å is defined as G group.

The channel layer 3 is made of In-doped In _x Ga.
_1-x As (x is an In composition parameter).

The composition of the In composition parameter x of the channel layer 3 is the same as that of the above-mentioned group of the channel layer 2 and n
The film thickness D ′ of the type In _x Ga _1-x As is 10Å, 20Å, 30
The sample was changed to Å, 40 Å, 50 Å, 70 Å, and each semiconductor layer was grown by the MBE method to prepare a field effect transistor having a gate length of 0.2 μm. Each of the field effect transistors is set to 12 GHz (Vds = 2
Table 2 shows the result of comparison of the minimum noise figure NFmin at V and Ids = 10 mA.

[0035]

[Table 2]

From Table 2, in addition to the fact that the structure of the present invention, that is, the structure in which the AND channel layer 3 is inserted between the buffer layer 4 and the channel layer 2, the performance is significantly improved. It can also be seen that this second specific example has better performance than that of the first specific example.

Further, in the second specific example, when the film thickness of the channel layer 2 exceeds 30 Å, the performance deteriorates again. Therefore, the film thickness of the channel layer 2 is preferably 30 Å or less.

[0038]

As described above, according to the present invention,
Generation of noise immediately below the gate electrode can be suppressed, and the noise figure can be significantly improved.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention.

FIG. 2 is a schematic diagram of a conductor band structure immediately below a gate electrode of the present invention.

FIG. 3 is a cross-sectional view of a conventional field effect transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... n-type AlGaAs semiconductor layer 2 ... channel layer 3 ... channel layer 4 ... buffer layer 5 ... cap layer 6 ... source electrode 7 ... drain electrode 8 ... gate Electrode 10 ... Semi-insulating GaAs substrate

Claims (1)

Claim: What is claimed is: 1. A buffer layer made of a first semiconductor, an AND channel layer made of a second semiconductor having an electron affinity higher than that of the first semiconductor, and a buffer layer made of the first semiconductor on the semiconductor substrate. A channel layer made of a third semiconductor having an electron affinity higher than that of the first semiconductor, a fourth semiconductor layer having an electron affinity lower than those of the second and third semiconductors, and a cap layer made of a fifth semiconductor; A field effect semiconductor device comprising a pair of electrodes connected to a layer, and a gate electrode arranged in the fourth semiconductor layer in the electrode.