JPH0568859B2 - - Google Patents
Info
- Publication number
- JPH0568859B2 JPH0568859B2 JP23422183A JP23422183A JPH0568859B2 JP H0568859 B2 JPH0568859 B2 JP H0568859B2 JP 23422183 A JP23422183 A JP 23422183A JP 23422183 A JP23422183 A JP 23422183A JP H0568859 B2 JPH0568859 B2 JP H0568859B2
- Authority
- JP
- Japan
- Prior art keywords
- fins
- semiconductor device
- housing
- thermal conductor
- cooling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000001816 cooling Methods 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 24
- 239000002470 thermal conductor Substances 0.000 claims description 22
- 239000004020 conductor Substances 0.000 description 17
- 239000007789 gas Substances 0.000 description 7
- 239000001307 helium Substances 0.000 description 6
- 229910052734 helium Inorganic materials 0.000 description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 6
- 238000006073 displacement reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4338—Pistons, e.g. spring-loaded members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体素子、集積回路チツプあるい
はマイクロパツケージなどの半導体デバイスなど
から発生する熱を除去するための冷却装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a cooling device for removing heat generated from a semiconductor device such as a semiconductor element, an integrated circuit chip, or a micropackage.
大型電子計算機では処理速度の速いことが要求
されるため、近年、半導体素子を大規模に集積し
た回路チツプが開発されている。また、その集積
回路チツプを互いに接続する電気配線をできるだ
め短かくするため、マイクロパツケージに多数の
集積回路チツプを実装する方法が開発されてい
る。この、マイクロパツケージに実装された多数
の集積回路チツプを冷却する冷却装置に関し、第
１図に示すような冷却装置が提案されている。
Since large electronic computers are required to have high processing speed, circuit chips in which semiconductor elements are integrated on a large scale have been developed in recent years. Furthermore, in order to make the electrical wiring connecting the integrated circuit chips to each other as short as possible, methods have been developed for mounting a large number of integrated circuit chips on a micropackage. Regarding a cooling device for cooling a large number of integrated circuit chips mounted on a micropackage, a cooling device as shown in FIG. 1 has been proposed.
大規模集積回路（以下LSIと略記）チツプ１
は、多数の導電層及び絶縁層からなる多層配線基
板２（以下基板と称す）上に非常に小さな半田ボ
ール３とFree Chip−Face Down Bondingとに
よつて実装され、基板２の裏面の多数のピンに電
気接続されている。多数のLSIチツプ２を覆うよ
うにハウジング５が基板２に装着されている。ハ
ウジング５内には多数のシリンダ６が開けられ、
シリンダ６の中にはLSIチツプ１の背面から熱を
導くピストン７と、ピストン７に押圧力を加える
バネ８が挿入されている。基板２とハウジング５
とで囲まれた密閉空間７には、ヘリウムガスが満
たされている。LSIチツプ２からの発生熱は、ピ
ストン７とLSIチツプ２との接触部に介存するヘ
リウムガス層を介してピストン７に伝えられる。
そして、ピストン７から更にピストン７とシリン
ダ６との隙間に介在するヘリウムガス層を伝わ
り、ハウジング５に導かれ、最終的に、ハウジン
グ５の上部に設けられた冷水または冷却空気の流
通する冷却器１０により除去される。 Large-scale integrated circuit (hereinafter abbreviated as LSI) chip 1
is mounted on a multilayer wiring board 2 (hereinafter referred to as the board) consisting of many conductive layers and insulating layers using very small solder balls 3 and Free Chip-Face Down Bonding. electrically connected to the pin. A housing 5 is attached to the board 2 so as to cover a large number of LSI chips 2. A number of cylinders 6 are opened in the housing 5,
A piston 7 that guides heat from the back surface of the LSI chip 1 and a spring 8 that applies a pressing force to the piston 7 are inserted into the cylinder 6. Board 2 and housing 5
A closed space 7 surrounded by is filled with helium gas. The heat generated from the LSI chip 2 is transmitted to the piston 7 via the helium gas layer present at the contact area between the piston 7 and the LSI chip 2.
From the piston 7, the gas is further transmitted through the helium gas layer interposed in the gap between the piston 7 and the cylinder 6, and is led to the housing 5, and finally to a cooler provided at the upper part of the housing 5 through which cold water or cooling air flows. removed by 10.
しかし、このような従来技術には次のような問
題点がある。 However, such conventional technology has the following problems.
ヘリウムガスの熱伝導率は気体の中では大きい
方であるが、ピストンあるいはシリンダなど金属
体に比べ非常に小さい。したがつて、ヘリウム層
の熱抵抗を小さくするためには、ピストン７とシ
リンダ６との隙間を小さくする必要がある。この
ため、ピストン７あるいはシリンダ６は、高い加
工精度が要求される。 Although the thermal conductivity of helium gas is higher among gases, it is much lower than that of metal objects such as pistons or cylinders. Therefore, in order to reduce the thermal resistance of the helium layer, it is necessary to reduce the gap between the piston 7 and the cylinder 6. For this reason, the piston 7 or cylinder 6 is required to have high processing accuracy.
第２図の冷却構造は、第１図の冷却構造に比べ
熱伝導板１３と平行溝１２の側壁との間のかさな
り面積を大きくすることができる。しかし、各熱
伝導板が全く独立にバラバラに可動であるため、
その分解、組立に複雑な作業を必要とする。 The cooling structure shown in FIG. 2 can increase the bulk area between the heat conductive plate 13 and the side wall of the parallel groove 12 compared to the cooling structure shown in FIG. 1. However, since each heat conduction plate can be moved completely independently,
Its disassembly and assembly require complicated work.
本発明の目的は、基板の反り、半導体チツプ接
続時の変位、冷却構造組立時の変形、冷却構造の
熱変形など種々の変位を吸収する能力を有し、か
つ、コンパクトで高い冷却性能を有する半導体素
子及び集積回路の冷却装置を提供することであ
る。
It is an object of the present invention to have the ability to absorb various types of displacement such as warping of substrates, displacement when connecting semiconductor chips, deformation when assembling the cooling structure, and thermal deformation of the cooling structure, and to have a compact and high cooling performance. An object of the present invention is to provide a cooling device for semiconductor devices and integrated circuits.
本発明の第１の特徴は、回路基板上に実装され
た半導体デバイスの発生熱をハウジングに伝えて
冷却するようにした半導体デバイスの冷却装置に
おいて、前記半導体デバイスの表面に設けられた
ベース部と、このベース部に一体に設けられた複
数の第１フインとを有する第１の熱伝導体と、前
記第１フインと係合する複数の第２フインを前記
第１熱伝導体側に有し、かつ前記ハウジング側に
は前記第２フインと実質的に直交するように設け
られた複数の第３フインを有する第２の熱伝導体
と、前記ハウジングに設けられ、前記第２の熱伝
導体の第３フインと係合する第４フインとを備え
ていることにある。
A first feature of the present invention is a cooling device for a semiconductor device configured to cool the semiconductor device by transmitting the heat generated by the semiconductor device mounted on the circuit board to the housing. , a first thermal conductor having a plurality of first fins integrally provided on the base portion, and a plurality of second fins that engage with the first fins on the first thermal conductor side, and a second thermal conductor having a plurality of third fins provided on the housing side so as to be substantially orthogonal to the second fins; The present invention includes a fourth fin that engages with the third fin.
本発明の第２の特徴は、回路基板上に実装され
た半導体デバイスの発生熱をハウジングに伝えて
冷却するようにした半導体デバイスの冷却装置に
おいて、前記半導体デバイスの表面に設けられた
ベース部とこのベース部に一体に設けられた複数
のフインとを有する熱伝導体と、前記熱伝導体の
フインとかみ合うように前記ハウジング側に設け
られたフインと、半導体デバイス側の前記熱伝導
体のフインと前記ハウジング側のフインとの間に
介在され、前記両フインを互いに面接触させるよ
うに付勢する弾性部材とを有することにある。 A second feature of the present invention is a cooling device for a semiconductor device configured to cool the semiconductor device by transmitting heat generated by the semiconductor device mounted on a circuit board to a housing. A thermal conductor having a plurality of fins integrally provided on the base portion, fins provided on the housing side so as to engage with the fins of the thermal conductor, and fins of the thermal conductor on the semiconductor device side. and an elastic member interposed between the fins on the housing side and urging the fins to come into surface contact with each other.
以下、本発明の一実施例を第３図、第４図によ
つて説明する。
An embodiment of the present invention will be described below with reference to FIGS. 3 and 4.
図において、銅あるいはアルミニユウムのよう
な熱伝導性の良好な材料により作られたハウジン
グ１５の内面には、多数のプレート状のフイン１
６が互いに平行に設けられている。LSIチツプ１
の背面の伝熱面積より大きな投影面積を有する熱
伝導体ａ１７及び熱伝導体ｂ１８にも、前記フイ
ン１６と同ピツチでフイン１９，２０，２１が多
数設けられている。ハウジング１５のフイン１６
と熱伝導体ａ１７のフイン１９及び熱伝導体ａ１
７のもう一方のフイン２０と熱伝導体ｂ１８のフ
イン２１とは互いに押しつけられその片面が面接
触した状態で嵌め合わされている。また、熱伝導
体ｂ１８とLSIチツプ１とも押し付けられ面接触
している。上記フイン相互及び熱伝導体とLSIチ
ツプの圧接触構造を図４に示す。ハウジング１５
と熱伝導体ａ１７とはフイン１６及び１９を斜め
に横断するバネ２２により連結されており、それ
ぞれのフイン１６及び１９は該バネ２２のバネ力
の水平方向成分によつて互いにその片面が面接触
するように押し付けられている。一方、熱伝導体
ａ１７と熱伝導体ｂ１８とは、フイン２０及び２
１を斜めに横断するバネ２３により連結されてお
り、それぞれのフイン２０及び２１は該バネ２３
のバネ力の水平方向成分によつて互いにその片面
が面接触するように押し付けられている。また、
熱伝導体ｂ１８とLSIチツプ１とは上記バネ２２
及び２３のバネ力の垂直方向成分によつて押し付
けられ面接触している。 In the figure, a housing 15 made of a material with good thermal conductivity such as copper or aluminum has a large number of plate-like fins 1 on its inner surface.
6 are provided parallel to each other. LSI chip 1
A large number of fins 19, 20, and 21 are provided at the same pitch as the fins 16 on the heat conductor a17 and the heat conductor b18, which have a larger projected area than the heat transfer area of the back surface. Fin 16 of housing 15
and the fins 19 of the heat conductor a17 and the heat conductor a1
The other fin 20 of the heat conductor b18 and the fin 21 of the heat conductor b18 are pressed together and fitted with one side of the fins in surface contact. Further, the heat conductor b18 and the LSI chip 1 are also pressed and in surface contact. FIG. 4 shows the structure of pressure contact between the fins and between the heat conductor and the LSI chip. Housing 15
and the thermal conductor a17 are connected by a spring 22 that diagonally crosses the fins 16 and 19, and one side of each fin 16 and 19 is brought into surface contact with each other by the horizontal component of the spring force of the spring 22. being forced to do so. On the other hand, the heat conductor a17 and the heat conductor b18 are the fins 20 and 2.
The fins 20 and 21 are connected by a spring 23 diagonally across the fins 20 and 21.
are pressed against each other by the horizontal component of the spring force so that one side of them is in surface contact. Also,
Thermal conductor b18 and LSI chip 1 are connected to the above spring 22.
and 23 are pressed by the vertical component of the spring force and are in surface contact.
LSIチツプ１で発生した熱は熱伝導体ｂ１８底
面に伝えられ、その熱順次熱伝導体ｂ１８のフイ
ン２１→熱伝導体ａ１７のフイン２０→熱電導体
ａ１７のフイン１９→ハウジング１５のフイン１
６へとそれぞれ固体壁の面接触によつて伝えられ
る。そして、それぞれの接触面間の接触熱抵抗
は、それぞれの面の仕上げ面精度、面間に介在す
るガス或には液体の熱伝導率によつて一義的に決
まり、組立精度、運転状態などにはよらない。ま
た、ごく一般的な加工方法を用いてもフインの仕
上げ面精度はμｍのオーダであり、20〜30μｍの
ヘリウム層を介して熱を伝える従来例図１、図２
に比べその熱抵抗は非常に小さい。また、熱電導
体ａ１７は方向２５及び２６に、熱伝導体ｂ１８
は方向２７及び２８に自由に動くことができるた
め、LSIチツプ１の高さのバラツキ、水平度のバ
ラツキにかかわらず、LSIチツプ１と熱伝導体ｂ
１８とは常に面で接触することができる。したが
つて、その接触熱抵抗を小さくできる。 Heat generated in the LSI chip 1 is transferred to the bottom surface of the heat conductor b18, and the heat is sequentially fin 21 of the heat conductor b18 → fin 20 of the heat conductor a17 → fin 19 of the heat conductor a17 → fin 1 of the housing 15
6 by means of surface contact with solid walls. The contact thermal resistance between each contact surface is uniquely determined by the finished surface accuracy of each surface and the thermal conductivity of the gas or liquid interposed between the surfaces, and is also dependent on assembly accuracy, operating conditions, etc. It doesn't fly. Furthermore, even if a very common processing method is used, the finished surface accuracy of the fins is on the order of μm, and conventional examples of heat transfer through a helium layer of 20 to 30 μm are shown in Figures 1 and 2.
Its thermal resistance is very small compared to . Further, the thermal conductor a17 is arranged in directions 25 and 26, and the thermal conductor b18
can move freely in directions 27 and 28, so regardless of variations in the height and horizontality of LSI chip 1, LSI chip 1 and thermal conductor b
18 can always be in surface contact. Therefore, the contact thermal resistance can be reduced.
第５図に他の実施例を示す。 FIG. 5 shows another embodiment.
熱伝導体ａ１７とハウジング１５とは互いに曲
率の等しい円筒面でかみ合わされており、方向２
６に自由に動くことができる。一方、熱伝導体の
１７と熱伝導体ｂ２１、熱伝導体ｂ２１とLSIチ
ツプ１との接続は第４図に示す実施例の場合と同
様である。本実施例の場合において、LSIチツプ
１で発した熱は全て、固体面の接触によりハウジ
ング１５に伝えられるため、その熱抵抗は非常に
小さく、したがつて、コンパクトな冷却構造とす
ることができる。 The heat conductor a17 and the housing 15 are engaged with each other through cylindrical surfaces with equal curvature, and are aligned in direction 2.
6 can move freely. On the other hand, the connections between the thermal conductor 17 and the thermal conductor b21 and between the thermal conductor b21 and the LSI chip 1 are the same as in the embodiment shown in FIG. In the case of this embodiment, all the heat generated by the LSI chip 1 is transferred to the housing 15 through contact with the solid surface, so its thermal resistance is extremely small, and a compact cooling structure can therefore be achieved. .
以上、本発明の一実施例第３図、第５図におい
てフイン板数として三枚の場合を示したが、この
枚数にとらわれることなく、LSIチツプの発熱量
に応じてフイン枚数を決定すればよい。また、そ
れぞれのフイン同士及び熱伝導体とLSIチツプと
を圧接触させる構造として、バネを斜めに取り付
ける構造を説明したが、水平方向用のバね、垂直
方向用のバネと二種類のバネを用いてそれぞれの
方向の押し付け力を得てもよい。 As mentioned above, the case where the number of fin plates is three is shown in FIG. 3 and FIG. good. In addition, we have explained a structure in which springs are attached diagonally to bring the fins into pressure contact with each other and the heat conductor and the LSI chip, but two types of springs are used: horizontal springs and vertical springs. may be used to obtain pressing force in each direction.
上記第２の熱伝導体を有する本発明によれば、
基板の反り、半導体デバイス接続時の変位、冷却
構造組立時の変形、冷却構造の熱変形など種々の
変位を吸収して熱伝導体を半導体デバイスの表面
に接触させることができ、熱抵抗を低減できると
いう効果がある。
According to the present invention having the second thermal conductor,
The thermal conductor can be brought into contact with the surface of the semiconductor device by absorbing various displacements such as board warpage, displacement when connecting semiconductor devices, deformation when assembling the cooling structure, and thermal deformation of the cooling structure, reducing thermal resistance. There is an effect that it can be done.
また、フインを互いに面接触させるための弾性
部材を備えた本発明によれば、フインどうしを面
接触させることにより、フイン間の熱抵抗を小さ
くすることができる効果がある。 Further, according to the present invention, which includes an elastic member for bringing the fins into surface contact with each other, the thermal resistance between the fins can be reduced by bringing the fins into surface contact with each other.
第１図、第２図は従来の半導体チツプの冷却装
置の縦断面図、第３図は本発明の一実施例を示す
一部断面斜視図、第４図は、第３図の実施例に示
す冷却構造の主要部の斜視断面図、第５図は、本
発明の他の一実施例の主要部の断面図。
１……LSIチツプ、２……基板、３……半田ボ
ール、５，１１，１５……ハウジング、７……ピ
ストン、８，２２，２３……バネ、１２……溝、
１３……熱伝導板、１６，１７，２０，２１……
フイン、１７，１８……熱伝導体。
1 and 2 are vertical sectional views of a conventional semiconductor chip cooling device, FIG. 3 is a partially sectional perspective view showing an embodiment of the present invention, and FIG. 4 is a view of the embodiment shown in FIG. FIG. 5 is a perspective sectional view of the main part of the cooling structure shown, and FIG. 5 is a sectional view of the main part of another embodiment of the present invention. 1... LSI chip, 2... Board, 3... Solder ball, 5, 11, 15... Housing, 7... Piston, 8, 22, 23... Spring, 12... Groove,
13... Heat conduction plate, 16, 17, 20, 21...
Finn, 17, 18...Heat conductor.
Claims (1)
生熱をハウジングに伝えて冷却するようにした半
導体デバイスの冷却装置において、前記半導体デ
バイスの表面に設けられたベース部と、このベー
ス部に一体に設けられた複数の第１フインとを有
する第１の熱伝導体と、前記第１フインと係合す
る複数の第２フインを前記第１熱伝導体側に有
し、かつ前記ハウジング側には前記第２フインと
実質的に直交するように設けられた複数の第３フ
インを有する第２の熱伝導体と、前記ハウジング
に設けられ、前記第２の熱伝導体の第３フインと
係合する第４フインとを備えていることを特徴と
する半導体デバイスの冷却装置。 ２ 回路基板上に実装された半導体デバイスの発
生熱をハウジングに伝えて冷却するようにした半
導体デバイスの冷却装置において、前記半導体デ
バイスの表面に設けられたベース部とこのベース
部に一体に設けられた複数のフインとを有する熱
伝導体と、前記熱伝導体のフインとかみ合うよう
に前記ハウジング側に設けられたフインと、半導
体デバイス側の前記熱伝導体のフインと前記ハウ
ジング側のフインとの間に介在され、前記両フイ
ンを互いに面接触させるように付勢する弾性部材
とを有する半導体デバイスの冷却装置。[Scope of Claims] 1. A cooling device for a semiconductor device configured to transfer heat generated by a semiconductor device mounted on a circuit board to a housing for cooling, comprising: a base portion provided on a surface of the semiconductor device; a first thermal conductor having a plurality of first fins integrally provided on a base portion; a plurality of second fins that engage with the first fins on the first thermal conductor side; a second thermal conductor having a plurality of third fins provided on the housing side so as to be substantially perpendicular to the second fins; A cooling device for a semiconductor device, comprising a fourth fin that engages with the fin. 2. In a cooling device for a semiconductor device configured to transfer heat generated by a semiconductor device mounted on a circuit board to a housing for cooling, a base portion provided on the surface of the semiconductor device and a base portion provided integrally with the base portion are provided. a thermal conductor having a plurality of fins, fins provided on the housing side so as to engage with the fins of the thermal conductor, and fins of the thermal conductor on the semiconductor device side and fins on the housing side. A cooling device for a semiconductor device, comprising an elastic member interposed between the fins and urging the fins to come into surface contact with each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23422183A JPS60126851A (en) | 1983-12-14 | 1983-12-14 | Cooling device for semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23422183A JPS60126851A (en) | 1983-12-14 | 1983-12-14 | Cooling device for semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60126851A JPS60126851A (en) | 1985-07-06 |
| JPH0568859B2 true JPH0568859B2 (en) | 1993-09-29 |
Family
ID=16967594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23422183A Granted JPS60126851A (en) | 1983-12-14 | 1983-12-14 | Cooling device for semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60126851A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5052481A (en) * | 1988-05-26 | 1991-10-01 | International Business Machines Corporation | High conduction cooling module having internal fins and compliant interfaces for vlsi chip technology |
| JP5177906B2 (en) * | 2010-01-28 | 2013-04-10 | Ｎｅｃアクセステクニカ株式会社 | Heat sink mechanism for electrical equipment |
-
1983
- 1983-12-14 JP JP23422183A patent/JPS60126851A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60126851A (en) | 1985-07-06 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |