JPH0573061B2 - - Google Patents
Info
- Publication number
- JPH0573061B2 JPH0573061B2 JP13171785A JP13171785A JPH0573061B2 JP H0573061 B2 JPH0573061 B2 JP H0573061B2 JP 13171785 A JP13171785 A JP 13171785A JP 13171785 A JP13171785 A JP 13171785A JP H0573061 B2 JPH0573061 B2 JP H0573061B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- holes
- thermally conductive
- large number
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 84
- 238000001816 cooling Methods 0.000 claims description 30
- 239000002470 thermal conductor Substances 0.000 claims description 19
- 239000012530 fluid Substances 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 229910052790 beryllium Inorganic materials 0.000 claims description 2
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 11
- 238000011109 contamination Methods 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- 239000002826 coolant Substances 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011148 porous material Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000110 cooling liquid Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229910001338 liquidmetal Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4338—Pistons, e.g. spring-loaded members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体デバイスの冷却装置に係り、
特に、半導体チツプあるいは半導体パツケージか
ら発生する熱を除去するのに好適な半導体デバイ
スの冷却装置に関するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a cooling device for a semiconductor device.
In particular, the present invention relates to a semiconductor device cooling apparatus suitable for removing heat generated from a semiconductor chip or a semiconductor package.
まず、従来の半導体デバイスの冷却装置を第５
図および第６図を参照して説明する。
First, the conventional semiconductor device cooling system was
This will be explained with reference to the figures and FIG.
第５図は、一般的な半導体チツプの冷却装置の
略示構成図、第６図は、従来の半導体パツケージ
の冷却構成を示す構成図である。 FIG. 5 is a schematic block diagram of a general semiconductor chip cooling device, and FIG. 6 is a block diagram showing a conventional semiconductor package cooling structure.
従来の基本的な半導体チツプの冷却装置は、第
５図に示すように、半導体チツプ１は、多数の導
体層および絶縁層からばる基板２の上に微小な半
田ボール３を介してフエイスダウンボンデイング
加工により面間の接合がなされ、基板２の裏面の
多数のピン４に電気接続されている。半導体チツ
プ１の背面には熱伝導体１２が接触している。 In the conventional basic semiconductor chip cooling device, as shown in FIG. The surfaces are joined by processing and electrically connected to a large number of pins 4 on the back surface of the substrate 2. A thermal conductor 12 is in contact with the back surface of the semiconductor chip 1.
半導体チツプ１で発生した熱は、半導体チツプ
１の背面に接触している前記熱伝導体１２に伝え
られ、熱伝導体１２の周囲に配置される各種の冷
却媒体（図示せず）によつて外部に放散されるよ
うに構成されていた。 The heat generated in the semiconductor chip 1 is transferred to the heat conductor 12 that is in contact with the back surface of the semiconductor chip 1, and is transferred to the heat conductor 12 by various cooling media (not shown) arranged around the heat conductor 12. It was configured to be dissipated to the outside.
このように、半導体チツプ１に熱伝導体１２を
接合する構成のものは、次に述べる点で冷却構造
に制約を受けていた。 As described above, the configuration in which the thermal conductor 12 is bonded to the semiconductor chip 1 is limited by the cooling structure in the following points.
(1) 基板２に実装された各半導体チツプ１の高
さ、傾きはそれぞれ異なつている。(1) The height and inclination of each semiconductor chip 1 mounted on the substrate 2 are different.
(2) 半田ボール３は非常に小さいものであるた
め、半導体チツプ１には大きな荷重を加えるこ
とができない。(2) Since the solder balls 3 are very small, they cannot apply a large load to the semiconductor chip 1.
このような制約条件に加えて、基板２は多層配
線構造となつているため、一般に製造時に、基板
２に反りが発生するので、熱伝導体１２には可撓
性が要求される。また、半導体チツプ１、熱伝導
体１２、基板２、熱伝導体１２を支持する部材
（図示せず）などの構成部材は、半導体チツプ１
の発熱によつて温度分布が生じる。このため、半
導体チツプ１に対し各構成部材から熱応力が加わ
る。 In addition to these constraints, the thermal conductor 12 is required to have flexibility, since the substrate 2 has a multilayer wiring structure and therefore warps will generally occur in the substrate 2 during manufacturing. Further, the semiconductor chip 1, the thermal conductor 12, the substrate 2, the component supporting the thermal conductor 12 (not shown), and other structural members are the semiconductor chip 1.
Temperature distribution occurs due to heat generation. Therefore, thermal stress is applied to the semiconductor chip 1 from each component.
以上の諸条件を緩和させるため、熱伝導体１２
に可撓性を持たせ、かつ熱伝導体１２は半導体チ
ツプ１面に対して低荷重で接触し、半導体チツプ
１面上をなめらかに滑るようになつている。 In order to alleviate the above conditions, the thermal conductor 12
The thermal conductor 12 is made to have flexibility, and is adapted to contact the surface of the semiconductor chip with a low load and slide smoothly on the surface of the semiconductor chip.
このような構造のもとでは、熱伝導体１２と半
導体チツプ１の面との間に接触熱抵抗が生じ、そ
の値は一般に大きい。この接触熱抵抗を小さくす
るため、接触面は高精度に、かつ、低い面粗さに
仕上げる必要があり、また、少しでも傷が付いた
り、あるいは接触界面間に塵埃などが介在する
と、接触熱抵抗が上昇してしまう欠点があつた。 Under such a structure, contact thermal resistance occurs between the thermal conductor 12 and the surface of the semiconductor chip 1, and its value is generally large. In order to reduce this contact thermal resistance, the contact surface must be finished with high precision and low surface roughness.In addition, if there is even the slightest scratch or dust is present between the contact interface, the contact surface will heat up. The drawback was that the resistance increased.
そこで、上記の制約条件を満足させるものとし
て、特公昭56−2419号公報記載の半導体パツケー
ジが提案されており、その半導体パツケージの冷
却構造の一例を示したものが第６図である。 Therefore, a semiconductor package described in Japanese Patent Publication No. 56-2419 has been proposed as one that satisfies the above-mentioned constraints, and FIG. 6 shows an example of the cooling structure of the semiconductor package.
第６図において、半導体チツプ１は、多数の導
体層および絶縁層からなる基板２の上に微小な半
田ボール３を介してフエイスダウンボンデイング
され、基板２の裏面の多数のピン４に電気接続さ
れている。基板２は下部ケーシング５によつて支
持され、その上から半導体チツプ１を覆うよう
に、キヤツプ６が装着されている。キヤツプ６の
内部には、半導体チツプ１の上方に配置されたシ
リンダ７を有しており、このシリンダ７内にはス
プリング８により半導体チツプの方向にバイアス
されている移動可能なピストン９が設けられてい
る。各ピストン９と各半導体チツプ１との間に
は、多孔性材料のブロツク１０が配置されてお
り、この多孔性材料のブロツク１０は、半導体チ
ツプ１と適合する界面を形成する適当な液体で含
浸されている。半導体チツプ１で発生した熱は、
半導体チツプ１の背面に接触しているブロツク１
０を介してピストン９に伝えられ、ピストン９か
らガス層を介してキヤツプ６に伝えられる。キヤ
ツプ６に伝えられた熱は、最終的にキヤツプ６の
上部に取り付けられた、冷却液１１ａの流通する
冷却器１１によつて除去される。 In FIG. 6, a semiconductor chip 1 is face-down bonded onto a substrate 2 consisting of a large number of conductive layers and insulating layers via minute solder balls 3, and is electrically connected to a large number of pins 4 on the back surface of the substrate 2. ing. The substrate 2 is supported by a lower casing 5, and a cap 6 is attached to cover the semiconductor chip 1 from above. The interior of the cap 6 has a cylinder 7 disposed above the semiconductor chip 1, in which a movable piston 9 biased toward the semiconductor chip by a spring 8 is provided. ing. A block 10 of porous material is arranged between each piston 9 and each semiconductor chip 1, which block 10 of porous material is impregnated with a suitable liquid forming a compatible interface with the semiconductor chip 1. has been done. The heat generated in the semiconductor chip 1 is
Block 1 in contact with the back side of semiconductor chip 1
0 to the piston 9, and from the piston 9 to the cap 6 via the gas layer. The heat transferred to the cap 6 is finally removed by a cooler 11 attached to the top of the cap 6 through which a cooling liquid 11a flows.
しかし、このような冷却構造では、多孔性材料
のブロツク１０に含浸されている液体が、振動ま
たは熱膨張などによつてブロツク１０の内部から
飛び出し、基板２に滞留して汚染の問題を生じう
ることについて配慮されていなかつた。 However, in such a cooling structure, the liquid impregnated into the block 10 made of porous material may fly out from the inside of the block 10 due to vibration or thermal expansion, and may remain in the substrate 2, causing a contamination problem. No consideration was given to this.
本発明は、前述の従来技術の問題点を解決する
ためになされたもので、半導体チツプあるいは半
導体パツケージから発生する熱を冷却媒体へ伝導
するについで、熱抵抗が小さく、かつ、汚染や腐
食に対する信頼性の高い半導体デバイスの冷却装
置の提供を、その目的としている。
The present invention has been made in order to solve the problems of the prior art described above, and is capable of conducting heat generated from a semiconductor chip or a semiconductor package to a cooling medium, while having a low thermal resistance and being resistant to contamination and corrosion. Its purpose is to provide a highly reliable cooling device for semiconductor devices.
本発明に係る半導体の冷却装置の構成は、半導
体チツプあるいは半導体パツケージの背面に、当
該半導体チツプあるいは半導体パツケージからの
発生熱を除去する熱伝導体を設けてなる半導体の
冷却装置において、前記半導体チツプあるいは半
導体パツケージと前記熱伝導体との間に、その両
者に接触して介在すべき高熱伝導性のシートを設
け、当該高熱伝導性のシートに、熱伝導性流体を
充填すべき多数の微細な貫通穴と、これら貫通穴
を互いに連通し合う多数の連通溝と、前記多数の
貫通穴の穴群を包囲み、かつ前記多数の連通溝と
連通する周囲溝とを備えたものである。
The structure of the semiconductor cooling device according to the present invention is such that a semiconductor cooling device is provided with a heat conductor on the back side of the semiconductor chip or the semiconductor package for removing heat generated from the semiconductor chip or the semiconductor package. Alternatively, a highly thermally conductive sheet is provided between the semiconductor package and the thermal conductor, and the highly thermally conductive sheet is filled with a large number of fine particles filled with thermally conductive fluid. The device includes a through hole, a large number of communication grooves that communicate the through holes with each other, and a peripheral groove that surrounds the group of the large number of through holes and communicates with the large number of communication grooves.
なお付記すると、本発明は、半導体チツプある
いは半導体パツケージと柔軟性を有する熱伝導体
との間に、熱伝導性に富み、多数の微細な貫通穴
を有するシートをはさみ、その微細な貫通穴に熱
伝導性流体を充填することにより、半導体と熱伝
導体との熱抵抗を小さくするものである。加え
て、前記シートには、各微細な貫通穴を互いに連
通する多数の連通溝が設けられ、前記貫通穴群を
囲むように設けられた液溜の溝と連通している。
このため、前記シートに充填される熱伝導性流体
がシートの外部に飛び出さず、汚染や腐食に対し
信頼性の高いものである。 As an additional note, the present invention involves sandwiching a sheet with high thermal conductivity and having many fine through holes between a semiconductor chip or a semiconductor package and a flexible thermal conductor, and inserting a sheet into the fine through holes. Filling with a thermally conductive fluid reduces the thermal resistance between the semiconductor and the thermal conductor. In addition, the sheet is provided with a large number of communication grooves that communicate the fine through holes with each other, and communicate with grooves of a liquid reservoir provided so as to surround the group of through holes.
Therefore, the thermally conductive fluid filled in the sheet does not splash out of the sheet, making it highly reliable against contamination and corrosion.
以下、本発明の各実施例を第１図ないし第４図
を参照して説明する。
Embodiments of the present invention will be described below with reference to FIGS. 1 to 4.
まず、第１図は、本発明の一実施例に係る半導
体チツプの冷却装置の断面図、第２図は、その高
熱伝導性のシート部の斜視図である。第１図中、
第５図と同一符号のものは従来の基本構成と同等
部分であるから、その説明を省略する。 First, FIG. 1 is a sectional view of a semiconductor chip cooling device according to an embodiment of the present invention, and FIG. 2 is a perspective view of a highly thermally conductive sheet portion thereof. In Figure 1,
Components with the same reference numerals as those in FIG. 5 are the same parts as the conventional basic configuration, so the explanation thereof will be omitted.
第１，２図において、１３は、半導体チツプ１
と柔軟性を有する構造の熱伝導体１２との間に、
その両者に接触してはさみ込まれた高熱伝導性の
シートである。このシート１３は、電気絶縁性に
富み、高熱伝導性の特性を有する、ベリリウムを
含有したシリコンカーバイド合金で形成されてい
る。 In FIGS. 1 and 2, 13 is a semiconductor chip 1
and a thermal conductor 12 having a flexible structure,
A highly thermally conductive sheet is sandwiched between the two. This sheet 13 is made of a beryllium-containing silicon carbide alloy that has excellent electrical insulation and high thermal conductivity.
１４は、シート１３に設けられた多数の微細な
貫通穴で、これら貫通穴１４は、半導体チツプ１
の背面に対向して垂直状に穿孔された円孔であ
る。 Reference numeral 14 denotes a large number of fine through holes provided in the sheet 13, and these through holes 14 are connected to the semiconductor chip 1.
This is a circular hole that is perpendicularly drilled opposite the back surface of the.
１６は、前記多数の微細な貫通穴１４を互いに
連通し合う多数の連通溝、１７は、前記多数の貫
通穴１５の穴群を四周からとり囲むように位置
し、かつ、前記多数の連通溝１６と連通する液溜
め溝となる周囲溝である。 Numeral 16 indicates a plurality of communication grooves that communicate the plurality of fine through-holes 14 with each other, and numeral 17 indicates a plurality of communication grooves that are located so as to surround the hole group of the plurality of through-holes 15 from all four circumferences; This is a peripheral groove that serves as a liquid reservoir groove communicating with 16.
前記多数の貫通穴１４には、熱伝導性流体１８
が充填されている。熱伝導体流体１８は、例え
ば、グリス、液体金属などが用いられるもので、
半導体チツプ１と熱伝導体１２を互いに密着させ
たとき、半導体チツプ１と熱伝導体１２との間の
熱抵抗を低減させるものである。 The large number of through holes 14 are filled with thermally conductive fluid 18.
is filled. The heat conductor fluid 18 is, for example, grease, liquid metal, etc.
When the semiconductor chip 1 and the thermal conductor 12 are brought into close contact with each other, the thermal resistance between the semiconductor chip 1 and the thermal conductor 12 is reduced.
多数の貫通穴１４の穴群は、半導体チツプ１の
背面の外周より内側の小さい面積の範囲に位置す
るように設けられ、貫通穴１４から溢れ出す熱伝
導性流体１８が、半導体チツプ１の外に飛散しな
いように構成されている。 A group of a large number of through holes 14 are provided so as to be located in a small area inside the outer periphery of the back surface of the semiconductor chip 1, so that the thermally conductive fluid 18 overflowing from the through holes 14 flows outside the semiconductor chip 1. It is constructed in such a way that it does not scatter.
また、前記シート１３は、熱伝導体１２から外
れないようにずれ止め用の縁部１９がシート１３
の四周に形成されている。 Further, the sheet 13 is provided with an edge 19 for preventing slippage so that the sheet 13 does not come off the heat conductor 12.
It is formed around the four circumferences of.
次に、このように構成された半導体チツプの冷
却装置の作用および効果を説明する。 Next, the operation and effects of the semiconductor chip cooling device configured as described above will be explained.
半導体チツプ１で発生した熱は、半導体チツプ
１の背面に接続されている高熱伝導性のシート１
３、熱伝導性流体１８を介して熱伝導体１２に伝
えられ、熱伝導体１２に設けられた冷却媒体（図
示せず）によつて外部に放散される。 The heat generated in the semiconductor chip 1 is transferred to a highly thermally conductive sheet 1 connected to the back side of the semiconductor chip 1.
3. The heat is transferred to the heat conductor 12 via the heat conductive fluid 18 and radiated to the outside by a cooling medium (not shown) provided in the heat conductor 12.
なお、冷却媒体としては、ヒート・シンクすな
わち冷却素子、例えば冷却フイン、冷却板など
や、第６図に示した冷却器１１などがある。 Note that the cooling medium includes a heat sink, that is, a cooling element, such as a cooling fin, a cooling plate, etc., and a cooler 11 shown in FIG. 6.
半導体チツプ１の高さのばらつき、傾きおよび
基板２の反りは、柔軟性のある熱伝導体１２で吸
収される。 Variations in the height of the semiconductor chip 1, inclination, and warpage of the substrate 2 are absorbed by the flexible thermal conductor 12.
半導体チツプ１で発生する熱によつて多数の貫
通穴１４内の熱伝導性流体１８が膨張する場合、
熱伝導性流体１８は、連通溝１６を通つて周囲溝
１７に至る。 When the thermally conductive fluid 18 in the many through holes 14 expands due to the heat generated in the semiconductor chip 1,
Thermally conductive fluid 18 passes through communication groove 16 to peripheral groove 17 .
また、熱伝導性流体１８が動きうる空間の周囲
は密閉されているため、振動や熱膨張などによつ
て熱伝導流体１８がシート１３の外部に飛び出る
心配がない。 Further, since the periphery of the space in which the thermally conductive fluid 18 can move is sealed, there is no fear that the thermally conductive fluid 18 will jump out of the sheet 13 due to vibrations, thermal expansion, or the like.
本実施例によれば、多数の微細な貫通穴１４に
熱伝導性流体１８を充填した高熱伝導性のシート
１３を半導体チツプ１と熱伝導体１２との間に設
けることにより、半導体チツプ１と熱伝導体１２
との間の熱抵抗を小さくすることができる。ま
た、前記多数の貫通穴１４と連通する液溜りを前
記シーノ１３に設けることにより、熱伝導性流体
１８はシート１３の外部に出ることがないので、
半導体チツプ１の汚染や腐食に対する信頼性が高
くなつた。 According to this embodiment, by providing a highly thermally conductive sheet 13 with a large number of fine through holes 14 filled with thermally conductive fluid 18 between the semiconductor chip 1 and the heat conductor 12, the semiconductor chip 1 and Thermal conductor 12
It is possible to reduce the thermal resistance between the Furthermore, by providing a liquid reservoir in the seam 13 that communicates with the large number of through holes 14, the thermally conductive fluid 18 does not come out of the sheet 13.
The reliability of the semiconductor chip 1 against contamination and corrosion is improved.
次に、本発明の他の実施例を第３図を参照して
説明する。 Next, another embodiment of the present invention will be described with reference to FIG.
第３図は、本発明の他の実施例に係る半導体チ
ツプの冷却装置に供されるシートの断面図で、図
中、第１図と同一符号のものは、第１図の実施例
と同等部分であるから、その説明を省略する。 FIG. 3 is a sectional view of a sheet used in a semiconductor chip cooling device according to another embodiment of the present invention. In the figure, the same reference numerals as those in FIG. Since this is only a partial explanation, its explanation will be omitted.
第３図の実施例で、先の第１図の実施例と相違
するところは、高熱伝導性のシート１３Ａに設け
た多数の微細な貫通穴１５がテーパー状に形成さ
れていることである。 The embodiment shown in FIG. 3 differs from the previous embodiment shown in FIG. 1 in that a large number of fine through holes 15 provided in a highly thermally conductive sheet 13A are formed in a tapered shape.
第３図の実施例によれば、先の第１図の実施例
と同様の効果が期待できる。 According to the embodiment shown in FIG. 3, the same effects as the previous embodiment shown in FIG. 1 can be expected.
次に、本発明のさらに他の実施例を第４図を参
照して説明する。 Next, still another embodiment of the present invention will be described with reference to FIG.
ここに第４図は、本発明のさらに他の実施例に
係る半導体チツプの冷却装置に供されるシートの
斜視図であり、図中、第２図と同一符号のもの
は、先の第１，２図の実施例と同等部分であるか
ら、その説明を省略する。 Here, FIG. 4 is a perspective view of a sheet provided for a semiconductor chip cooling device according to still another embodiment of the present invention, and in the figure, the same reference numerals as in FIG. , 2 are the same parts as in the embodiment shown in FIGS. 2 and 2, so their explanation will be omitted.
第４図の実施例で、先の第２図の実施例と相違
するところは、高熱伝導性のシート１３Ｂが熱伝
導体１２から外れないようにするずれ止め手段と
して、縁部ではなく、係止用突起２０を設けたこ
とである。 The embodiment shown in FIG. 4 differs from the previous embodiment shown in FIG. This is because the stop protrusion 20 is provided.
第４図の実施例によれば、先の第１，２図の実
施例と同様の効果が期待できる。 According to the embodiment shown in FIG. 4, the same effects as those of the previous embodiments shown in FIGS. 1 and 2 can be expected.
なお、ずれ止め手段は、前述の各実施例のもの
に限らず、シートが熱伝導体１２から外れなけれ
ばどのような形状のものでもよい。 Note that the anti-slip means is not limited to those of the embodiments described above, and may be of any shape as long as the sheet does not come off the heat conductor 12.
また、前述の各実施例は、半導体チツプと熱伝
導体との間に介在させる高熱伝導性のシートにつ
いて説明したが、本発明は、半導体チツプのみに
適用されるものではなく、前記高熱伝導性のシー
トは、半導体パツケージから発生する熱の外部放
散にも適用できるものである。 Furthermore, although each of the above embodiments describes a highly thermally conductive sheet interposed between a semiconductor chip and a thermal conductor, the present invention is not applied only to semiconductor chips; The sheet can also be applied to external dissipation of heat generated from semiconductor packages.
〔発明の効果〕
以上述べたように、本実施例によれば、半導体
チツプあるいは半導体パツケージから発生する熱
を冷却媒体へ伝導するについて、熱抵抗が小さ
く、かつ、汚染や腐触に対する信頼性の高い半導
体デバイスの冷却装置を提供することができる。[Effects of the Invention] As described above, according to this embodiment, the heat generated from the semiconductor chip or the semiconductor package is conducted to the cooling medium with low thermal resistance and with high reliability against contamination and corrosion. A cooling device for semiconductor devices with high efficiency can be provided.
第１図は、本発明の一実施例に係る半導体チツ
プの冷却装置の断面図、第２図は、その高熱伝導
性のシート部の斜視図、第３図は、本発明の他の
実施例に係る半導体チツプの冷却装置に供される
シートの断面図、第４図は、本発明のさらに他の
実施例に係る半導体チツプの冷却装置に供される
シートの斜視図、第５図は、一般的な半導体チツ
プの冷却装置の略示構成図、第６図は、従来の半
導体パツケージの冷却機構を示す構成図である。
１……半導体チツプ、２……基板、１２……熱
伝導体、１３，１３Ａ，１３Ｂ……シート、１
４，１５……貫通穴、１６……連通溝、１７……
周囲溝、１８……熱伝導性流体、１９……縁部、
２０……係止用突起。
FIG. 1 is a sectional view of a semiconductor chip cooling device according to an embodiment of the present invention, FIG. 2 is a perspective view of a highly thermally conductive sheet portion thereof, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a cross-sectional view of a sheet used in a semiconductor chip cooling device according to still another embodiment of the present invention, and FIG. FIG. 6 is a schematic block diagram of a general semiconductor chip cooling device. FIG. 6 is a block diagram showing a conventional semiconductor package cooling mechanism. 1... Semiconductor chip, 2... Substrate, 12... Thermal conductor, 13, 13A, 13B... Sheet, 1
4, 15...Through hole, 16...Communication groove, 17...
peripheral groove, 18... thermally conductive fluid, 19... edge,
20...Latching protrusion.
Claims (1)
面に、当該半導体チツプあるいは半導体パツケー
ジからの発生熱を除去する熱伝導体を設けてなる
半導体デバイスの冷却装置において、前記半導体
チツプあるいは半導体パツケージと前記熱伝導体
との間に、その両者に接触して介在すべき高熱伝
導性のシートを設け、当該高熱伝導性のシート
に、熱伝導性流体を充填すべき多数の微細な貫通
穴と、これら貫通穴を互いに連通し合う多数の連
通溝と、前記多数の貫通穴の穴群をとり囲み、か
つ前記多数の連通溝と連通する周囲溝とを備えた
ことを特徴とする半導体デバイスの冷却装置。 ２ 特許請求の範囲第１項記載のものにおいて、
多数の貫通穴の穴群が位置する範囲を、半導体チ
ツプあるいは半導体パツケージの背面より小さく
構成したものである半導体デバイスの冷却装置。 ３ 特許請求の範囲第１項記載のものにおいて、
多数の貫通穴は、半導体チツプあるいは半導体パ
ツケージの背面に対向して垂直状に、あるいはテ
ーパー状に穿設されたものである半導体デバイス
の冷却装置。 ４ 特許請求の範囲第１項記載のものにおいて、
高熱伝導性のシートは、ベリリウムを含有したシ
リコンカーバイド合金で形成されたものである半
導体デバイスの冷却装置。[Scope of Claims] 1. A cooling device for a semiconductor device in which a heat conductor is provided on the back side of a semiconductor chip or a semiconductor package to remove heat generated from the semiconductor chip or the semiconductor package. A highly thermally conductive sheet is provided between the thermal conductor and interposed in contact with both, and the highly thermally conductive sheet is provided with a large number of minute through holes that are filled with a thermally conductive fluid; Cooling of a semiconductor device characterized by comprising a large number of communication grooves that communicate with each other through the through holes, and a peripheral groove that surrounds a group of the large number of through holes and communicates with the large number of communication grooves. Device. 2. In what is stated in claim 1,
A cooling device for a semiconductor device in which the range in which a group of through holes are located is smaller than the back surface of a semiconductor chip or semiconductor package. 3 In what is stated in claim 1,
A cooling device for a semiconductor device in which a large number of through holes are formed vertically or tapered facing the back surface of a semiconductor chip or semiconductor package. 4 In what is stated in claim 1,
The highly thermally conductive sheet is made of a silicon carbide alloy containing beryllium for cooling devices of semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13171785A JPS61290743A (en) | 1985-06-19 | 1985-06-19 | Cooling apparatus for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13171785A JPS61290743A (en) | 1985-06-19 | 1985-06-19 | Cooling apparatus for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61290743A JPS61290743A (en) | 1986-12-20 |
| JPH0573061B2 true JPH0573061B2 (en) | 1993-10-13 |
Family
ID=15064552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13171785A Granted JPS61290743A (en) | 1985-06-19 | 1985-06-19 | Cooling apparatus for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61290743A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2441089B1 (en) * | 2009-06-10 | 2013-04-24 | Robert Bosch GmbH | Cooling arrangement and method for assembling the cooling arrangement |
| US8957316B2 (en) * | 2010-09-10 | 2015-02-17 | Honeywell International Inc. | Electrical component assembly for thermal transfer |
| DE102011005669A1 (en) * | 2011-03-17 | 2012-09-20 | Robert Bosch Gmbh | Heat-conducting film for cooling and fixing electronic components |
-
1985
- 1985-06-19 JP JP13171785A patent/JPS61290743A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61290743A (en) | 1986-12-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2926537B2 (en) | Multi-chip module cooling system | |
| US5052481A (en) | High conduction cooling module having internal fins and compliant interfaces for vlsi chip technology | |
| US4442450A (en) | Cooling element for solder bonded semiconductor devices | |
| KR900003828B1 (en) | Semiconductor device and manufacturing method thereof | |
| CA1187208A (en) | Thermal conduction element for semiconductor devices | |
| JP3241639B2 (en) | Multi-chip module cooling structure and method of manufacturing the same | |
| US4639829A (en) | Thermal conduction disc-chip cooling enhancement means | |
| US5367193A (en) | Low cost, thermally efficient, and surface mountable semiconductor package for a high applied power VLSI die | |
| US5515912A (en) | Cooling apparatus of electronic devices | |
| JP5898919B2 (en) | Semiconductor device | |
| JPH0578183B2 (en) | ||
| JPH0786471A (en) | Semiconductor module | |
| JPS59217345A (en) | Heat sink assembly | |
| JPS6132819B2 (en) | ||
| EP0167033B1 (en) | Apparatus for conduction cooling | |
| JPH05160312A (en) | Module for electronic package | |
| US5206713A (en) | Mounting silicon chips | |
| JPH0573061B2 (en) | ||
| JPH04291750A (en) | Head radiating fin and semiconductor integrated circuit device | |
| US6573538B2 (en) | Semiconductor device with internal heat dissipation | |
| US11282762B2 (en) | Heat sink design for flip chip ball grid array | |
| JPS60257156A (en) | Heat conductive cooling module device | |
| JP3395409B2 (en) | Semiconductor module | |
| JPS61147554A (en) | Hybrid ic module | |
| JPH03105955A (en) | Heat-dissipating structure body of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |