JP2506885B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2506885B2
JP2506885B2 JP63012381A JP1238188A JP2506885B2 JP 2506885 B2 JP2506885 B2 JP 2506885B2 JP 63012381 A JP63012381 A JP 63012381A JP 1238188 A JP1238188 A JP 1238188A JP 2506885 B2 JP2506885 B2 JP 2506885B2
Authority
JP
Japan
Prior art keywords
housing
heat
heat conducting
semiconductor
conducting member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63012381A
Other languages
Japanese (ja)
Other versions
JPH01187840A (en
Inventor
弘則 児玉
一二 山田
太佐男 曽我
忠彦 三吉
崇弘 大黒
二三幸 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP63012381A priority Critical patent/JP2506885B2/en
Publication of JPH01187840A publication Critical patent/JPH01187840A/en
Application granted granted Critical
Publication of JP2506885B2 publication Critical patent/JP2506885B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体素子あるいは集積回路チップから発生
する熱を効率良く除去できる半導体装置に係り、特に半
導体素子あるいは集積回路間の電気的絶縁を保ち、且つ
高い冷却性能を維持するに好適な半導体装置に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of efficiently removing heat generated from a semiconductor element or an integrated circuit chip, and more particularly to maintaining electrical insulation between the semiconductor element or the integrated circuit. And a semiconductor device suitable for maintaining high cooling performance.

[従来の技術] 大型電子計算機の演算速度の高速化の要求に対応する
ため、近年益々半導体素子は大規模に集積化される傾向
にある。また、さらにその高集積化した回路チップ間を
接続する電気配線での信号遅延を出来るだけ少なくする
ために、マイクロパッケージに多数の集積回路チップを
実装し、配線長を短くする方法が種々開発されている。
[Prior Art] In recent years, semiconductor devices tend to be more and more integrated on a large scale in order to meet the demand for high-speed operation of large-scale electronic computers. Further, in order to reduce the signal delay in the electric wiring connecting between the highly integrated circuit chips as much as possible, various methods have been developed for mounting a large number of integrated circuit chips in a micropackage and shortening the wiring length. ing.

しかしながら、このような半導体素子の大規模集積
化、実装密度の向上に伴って当然集積回路チップからの
発熱量及び発熱密度が増大し、これらの熱を除去するた
めの冷却構造が必要となってきている。また、この冷却
構造には、基板の反り、半導体チップ接続時の変位、冷
却構造組み立て時の変形、冷却構造の熱変形など製造及
び使用時の種々の変位を吸収する機能も要求される。
However, with such large-scale integration of semiconductor elements and improvement in packaging density, the heat generation amount and heat generation density from the integrated circuit chip naturally increase, and a cooling structure for removing these heats becomes necessary. ing. Further, this cooling structure is also required to have a function of absorbing various displacements during manufacturing and use such as warpage of the substrate, displacement during connection of semiconductor chips, deformation during assembly of the cooling structure, and thermal deformation of the cooling structure.

従来、特に大型計算機システムの冷却構造に関して、
第3図に示すような冷却装置が提案されている。大規模
集積回路(以下LSIと略記)チップ1は、多数の導電層
及び絶縁層からなる多層配線基板2(以下基板と略記)
上に、はんだ3によってフリップ・チップ接続され、基
板2内の前記導電層を介して基板2の裏面に設けられた
多数のピン4に電気接続されている。更に基板2には多
数のLSIチップ1を覆うようにハウジング5が装着され
ている。ハウジング5内には多数のシリンダ6が形成さ
れ、シリンダ6の中にはLSIチップ1の背面から熱を導
く熱伝導部材としてのピストン7と、ピストン7に押圧
力を加えるバネ8が挿入されている。基板2とハウジン
グ5とで囲まれた密閉空間9には、ヘリウムガスが満た
されている。LSIチップ1からの発生熱は、ピストン7
の球面状先端とLSIチップ1の背面との接触部に介在す
るヘリウムガス層を介してピストン7に伝えられ、ピス
トン7から更にピストン7とシリンダ6との隙間に介在
するヘリウムガス層を伝わり、ハウジング5に導かれ
る。そして、最終的に、ハウジング5の上部に設けられ
た冷水又は冷却空気の流通する冷却器10により除去され
る。
Conventionally, especially regarding the cooling structure of large computer systems,
A cooling device as shown in FIG. 3 has been proposed. A large-scale integrated circuit (hereinafter abbreviated as LSI) chip 1 is a multi-layer wiring substrate 2 (hereinafter abbreviated as a substrate) including a number of conductive layers and insulating layers.
It is flip-chip connected by solder 3 and electrically connected to a large number of pins 4 provided on the back surface of the substrate 2 through the conductive layer in the substrate 2. Further, a housing 5 is mounted on the substrate 2 so as to cover many LSI chips 1. A large number of cylinders 6 are formed in the housing 5, and a piston 7 as a heat conducting member for guiding heat from the back surface of the LSI chip 1 and a spring 8 for applying a pressing force to the piston 7 are inserted in the cylinder 6. There is. The enclosed space 9 surrounded by the substrate 2 and the housing 5 is filled with helium gas. The heat generated from the LSI chip 1 is generated by the piston 7
Is transmitted to the piston 7 through the helium gas layer that is present at the contact portion between the spherical tip of the and the back surface of the LSI chip 1, and is further transmitted from the piston 7 to the helium gas layer that is present in the gap between the piston 7 and the cylinder 6. Guided to the housing 5. Then, finally, it is removed by the cooler 10 provided in the upper part of the housing 5 through which cold water or cooling air flows.

しかし、このような従来技術には次のような問題点が
ある。ヘリウムガスの熱伝導率は、気体の中では大きい
方であるが、ピストン7あるいはシリンダ6などの金属
体に比べ非常に小さい。従って、ヘリウム層の熱抵抗を
小さく抑えるためにはピストン7とシリンダ6との隙間
を小さくする必要がある。このためピストン7あるいは
シリンダ6には高い加工精度が要求され、加工精度が低
ければ、ピストン7の動きが阻害されたり、LSIチップ
1の温度が大きくばらついたりする恐れがある。
However, such a conventional technique has the following problems. The thermal conductivity of helium gas is the largest in the gas, but it is much smaller than that of a metal body such as the piston 7 or the cylinder 6. Therefore, in order to keep the thermal resistance of the helium layer small, it is necessary to reduce the gap between the piston 7 and the cylinder 6. Therefore, the piston 7 or the cylinder 6 is required to have a high processing accuracy, and if the processing accuracy is low, the movement of the piston 7 may be hindered or the temperature of the LSI chip 1 may greatly vary.

上記の欠点を改善するために、例えば第4図に示すよ
うな冷却構造体が、米国特許第4263965号に開示されて
いる。第3図の冷却構造に対して第4図の冷却構造は、
LSIチップ1に対向するハウジング11内に多数の平行溝1
2を設け、各平行溝12内に、各々薄い長方形の熱伝導板1
3と熱伝導板13に押圧力を加える板バネ14が挿入されて
いる。第4図の冷却構造は、第3図の冷却構造に比べ熱
伝導板13と平行溝12の側壁との熱交換する伝熱面積を大
きくとれ、また熱伝導板13とLSIチップ1との接触状態
を熱伝導板13の板幅分の面接触に改善されている。
In order to remedy the above drawbacks, a cooling structure such as that shown in FIG. 4 is disclosed in US Pat. No. 4,263,965. The cooling structure shown in FIG. 4 is different from the cooling structure shown in FIG.
Many parallel grooves 1 in the housing 11 facing the LSI chip 1
2 is provided, and each thin rectangular heat conduction plate 1 is provided in each parallel groove 12.
A leaf spring 14 that applies a pressing force to the heat conducting plate 3 and the heat conducting plate 13 is inserted. The cooling structure of FIG. 4 has a larger heat transfer area for heat exchange between the heat conducting plate 13 and the side walls of the parallel grooves 12 than the cooling structure of FIG. 3, and the contact between the heat conducting plate 13 and the LSI chip 1 is large. The state is improved to surface contact corresponding to the width of the heat conduction plate 13.

しかし、第4図の冷却構造においても、下記のような
問題点が残される。即ち、多数の熱伝導板13が各々切り
離され独立し、平行溝12の中に挿入されているので、各
熱伝導板13間相互の熱交換がほとんど行なわれない。と
ころがLSIチップ1の集積回路は、多数の電気回路から
構成されているため、一般に一様に発熱することは極め
て希である。またLSIチップ1内の発熱分布も、時間と
共に変動する。従って、例えばLSIチップ1の端のみで
発熱している場合には、発熱部分に近い熱伝導板13しか
熱を奪い去ることができず、遠くの熱伝導板13からは、
LSIチップ1内を介して伝わってきた熱しか持ち去るこ
とが出来ない。すなわち、多数の熱伝導板13をLSIチッ
プ1の上においても、各熱伝導板13間の熱移動がほとん
ど行なわれないため、全熱伝導板の熱輸送効率が低下し
てしまう。また、熱伝導板13の設置面積がLSIチップ1
の幅によって制限されるため、冷却性向上には制限があ
る。
However, the cooling structure of FIG. 4 also has the following problems. That is, since a large number of heat conducting plates 13 are separated and independent of each other and are inserted into the parallel grooves 12, heat exchange between the respective heat conducting plates 13 is hardly performed. However, since the integrated circuit of the LSI chip 1 is composed of a large number of electric circuits, it is extremely rare that heat is generated uniformly. The heat generation distribution in the LSI chip 1 also changes with time. Therefore, for example, when heat is generated only at the edge of the LSI chip 1, only the heat conducting plate 13 near the heat generating portion can take away the heat, and the heat conducting plate 13 far away from the heat conducting plate 13.
Only the heat transmitted through the LSI chip 1 can be carried away. That is, even if a large number of heat conduction plates 13 are arranged on the LSI chip 1, heat transfer between the heat conduction plates 13 is hardly performed, so that the heat transport efficiency of all the heat conduction plates is reduced. In addition, the installation area of the heat conduction plate 13 is the LSI chip 1
There is a limit to the improvement of the cooling property because it is limited by the width of.

以上のような問題点を解決する方法として、特開昭60
−126853号公報において第5図に示すような冷却構造体
が開示されている。第5図に示した冷却構造体において
は、半導体チップ1の表面積すなわち放熱面積より大き
な底面積を有する熱伝導部材17に一体に複数の第1フィ
ン18を設け、この第1フィンと、ハウジング15の内面側
に設けられた複数の第2フィン16とを、互いに微小間隙
19を保ってはめ合わせ、更に前記熱伝導部材17とハウジ
ング15の間に介装されたバネ20によって熱伝導部材17の
底面を半導体チップ1の表面に押しつけるように構成さ
れている。バネ20は、フィン16の隙間23内に挿入され、
ハウジング15に設けられた穴21と熱伝導部材17のベース
中央に設けられた穴22とで固定されている。ハウジング
15と基板2とで囲まれた密閉空間24には、熱伝導率の良
好な気体、例えばヘリウムガスあるいは水素ガスなどが
充満されている。従ってLSIチップ1で発生した熱は、L
SIチップ1と全面接触する熱伝導部材17のベース部に一
旦伝えられ、ベース内で一様に拡散された後、熱伝導部
材17の各フィン18に伝わり、そして、各々微小間隙19の
ヘリウムガス層からハウジング15のフィン16へと伝わ
り、最終的にハウジング15上部に取付けられている冷却
器により持ち去られる。熱伝導部材17のフィン18は、ベ
ースと一体に形成されているので、たとえLSIチップ1
内の発熱分布が不均一であっても、発生する熱はベース
内で均一に拡散させることが出来る。従って、熱伝導部
材17の各フィン18の熱輸送効率を最大限に高めることが
出来る。
As a method for solving the above problems, Japanese Patent Laid-Open No.
-126853 discloses a cooling structure as shown in FIG. In the cooling structure shown in FIG. 5, a plurality of first fins 18 are integrally provided on a heat conducting member 17 having a bottom area larger than the surface area of the semiconductor chip 1, that is, the heat radiation area. A plurality of second fins 16 provided on the inner surface side of the
The heat conducting member 17 and the housing 15 are fitted together, and a spring 20 interposed between the heat conducting member 17 and the housing 15 presses the bottom surface of the heat conducting member 17 against the surface of the semiconductor chip 1. The spring 20 is inserted into the gap 23 of the fin 16,
The hole 21 provided in the housing 15 and the hole 22 provided in the center of the base of the heat conducting member 17 are fixed. housing
A closed space 24 surrounded by 15 and the substrate 2 is filled with a gas having a good thermal conductivity, such as helium gas or hydrogen gas. Therefore, the heat generated in the LSI chip 1 is L
The helium gas is once transferred to the base part of the heat conducting member 17 which is in full contact with the SI chip 1, is diffused uniformly in the base, is then transferred to each fin 18 of the heat conducting member 17, and is a helium gas in each minute gap 19. It travels from the layers to the fins 16 of the housing 15 and is eventually carried away by the cooler mounted on top of the housing 15. Since the fins 18 of the heat conducting member 17 are formed integrally with the base, the LSI chip 1
Even if the internal heat generation distribution is not uniform, the generated heat can be diffused uniformly in the base. Therefore, the heat transfer efficiency of each fin 18 of the heat conducting member 17 can be maximized.

[発明が解決しようとする課題] 以上のような第3図、第4図又は第5図のいずれの場
合においても、熱伝導部材及びハウジングの材質は、高
い熱伝導性を有することが必要不可欠であり、一般的に
は銅あるいはアルミニウムといった金属が用いられる。
しかしながら、LSIチップ1の背面は、特別の電気絶縁
処理を施さない限り電気伝導性であるため、これに銅あ
るいはアルミニウム製の熱伝導部材を押し付けると、各
LSIチップが互いにショートしてしまうという問題があ
る。前記特開昭60−126853号公報においては、熱伝導部
材あるいはハウジングの材質を、電気絶縁性に富み、高
い熱伝導性を有するSiC材とする方法が開示されている
が、この方法には材料コスト及びSiCが難加工性である
ことによる加工コストの面での問題が残されている。
[Problems to be Solved by the Invention] In any case of FIG. 3, FIG. 4 or FIG. 5 as described above, it is essential that the materials of the heat conducting member and the housing have high heat conductivity. In general, a metal such as copper or aluminum is used.
However, since the back surface of the LSI chip 1 is electrically conductive unless special electrical insulation processing is performed, pressing a heat-conducting member made of copper or aluminum on the back surface causes
There is a problem that LSI chips are short-circuited to each other. In JP-A-60-126853, there is disclosed a method in which the material of the heat conducting member or the housing is a SiC material having high electrical insulation and high heat conductivity. There are problems in terms of cost and processing cost due to the difficulty of processing SiC.

本発明の目的は、半導体素子または集積回路チップ間
の電気的絶縁を確保し、且つ高い冷却性能を有する半導
体装置を安価に提供することにある。
An object of the present invention is to inexpensively provide a semiconductor device which ensures electrical insulation between semiconductor elements or integrated circuit chips and has high cooling performance.

[課題を解決するための手段] 本発明は、回路基板上に搭載された複数個の半導体チ
ップと、該半導体チップに対向する熱伝導性金属製のハ
ウジングと、各半導体チップから発生した熱を該ハウジ
ングに伝えるために各半導体チップの表面とハウジング
との間にそれらと接触するように夫々配置された複数個
の熱伝導性金属製の熱伝導部材と、該熱伝導部材を半導
体チップの表面に押圧する弾性部材とを備えた半導体装
置において、前記熱伝導部材とハウジングとの接触面の
少なくとも一方に薄い電気絶縁層を形成したことを特徴
とする。
[Means for Solving the Problem] The present invention provides a plurality of semiconductor chips mounted on a circuit board, a housing made of a heat conductive metal facing the semiconductor chips, and heat generated from each semiconductor chip. A plurality of heat conductive members made of heat conductive metal, each of which is arranged between the surface of each semiconductor chip and the housing so as to be in contact with the surface of the semiconductor chip for transmitting to the housing; In a semiconductor device having an elastic member that presses against, a thin electrically insulating layer is formed on at least one of contact surfaces of the heat conducting member and the housing.

[作用] 本発明の如上の構成において、前記薄い電気絶縁層
は、各熱伝導部材からハウジングへの熱伝達に関しては
殆んど熱抵抗を与えず、これら両者間の電気的絶縁は十
分に果す。よって半導体チップに対する冷却効果を確保
しながら、各チップが互に電気的にショートすることを
防止できる。
[Operation] In the above-described structure of the present invention, the thin electric insulation layer provides almost no heat resistance with respect to heat transfer from each heat conduction member to the housing, and the electric insulation between them is sufficiently achieved. . Therefore, it is possible to prevent the chips from electrically short-circuiting each other while ensuring the cooling effect on the semiconductor chips.

[実 施 例] 本発明における前記熱伝導部材およびハウジングは、
銅またはアルミニウムの如き熱伝導性が良好な、且つ加
工性の良い金属材料で作られる。また前記のような微細
なフィンの表面に前記の薄い電気絶縁層を比較的簡単に
形成する方法としては、プラズマ溶射、CVD、グロー放
電などを利用した金属表面の窒化または酸化処理や、前
記熱伝導部材のフィン又はハウジングのフィンの材料を
アルミニウムとして、その表面を電解溶液中で陽極酸化
する方法などを用いることができる。
[Example] The heat conducting member and the housing in the present invention are
It is made of a metal material having good thermal conductivity and good workability, such as copper or aluminum. Further, as a method of relatively easily forming the thin electric insulation layer on the surface of the fine fin as described above, plasma spraying, CVD, nitridation or oxidation treatment of the metal surface using glow discharge, or the thermal treatment The fin of the conductive member or the fin of the housing may be made of aluminum and the surface thereof may be anodized in an electrolytic solution.

これらフィン表面に形成される電気絶縁層はフィンを
構成する金属より一般に熱伝導率が小さい。従って、電
気絶縁層を設けたことによる熱抵抗の増加をできるだけ
小さく抑えるためには、電気絶縁層の厚さを、必要な電
気絶縁の確保できる範囲で、できるだけ薄くすることが
望ましい。例えばアルミニウムの熱伝導部材を用いて、
その表面に通常の陽極酸化皮膜を設けた場合には、その
膜厚は0.1〜10μm、好ましくは0.1〜5μm以下が好適
である。また、ノンポーラス・タイプの硬質皮膜を形成
した場合いには、その膜の耐電圧が高いので膜圧を更に
小さくでき、1〜3000Å、好ましくは1〜300Åとする
ことが望ましい。
The electrical insulating layer formed on the surface of these fins generally has a lower thermal conductivity than the metal forming the fins. Therefore, in order to suppress the increase in thermal resistance due to the provision of the electrical insulation layer as small as possible, it is desirable to make the thickness of the electrical insulation layer as thin as possible within a range in which necessary electrical insulation can be secured. For example, using a heat conducting member of aluminum,
When a usual anodic oxide film is provided on the surface, the film thickness is 0.1 to 10 μm, preferably 0.1 to 5 μm or less. When a non-porous type hard film is formed, the withstand voltage of the film is high so that the film pressure can be further reduced, and it is desirable that the film pressure is 1 to 3000 Å, preferably 1 to 300 Å.

さらに、熱抵抗をなるべく少くするためには、熱伝導
部材の、半導体チップに接触する面を除いたフィンの表
面にのみ薄い電気絶縁層を形成することが望ましい。熱
伝導部材の、半導体チップに接触する面にも電気絶縁層
を形成した場合には、熱的に見ると該絶縁層の熱抵抗が
半導体チップと熱伝導部材金属の間に直列に加わるた
め、この部分の熱抵抗の影響が無視できないのに対し
て、フィンの表面のみに電気絶縁層を形成した場合に
は、該絶縁層の熱抵抗が前記熱伝導部材とハウジングの
間でフィンの数に応じて並列に加えられるため全体の熱
抵抗に対する影響は小さく、ほとんど無視できるように
なる。同様に、ハウジングの内面に設けたフィンの表面
のみに電気絶縁層を形成した場合にも同じ効果が得られ
る。本発明では本質的に前記熱伝導部材のフィン又は、
ハウジングのフィンの互いに接触する可能性のある部分
にのみ電気絶縁層が形成されていればよく、電気絶縁層
形成の作業性、コスト等を考えて最適の方法が選べる。
Further, in order to reduce the thermal resistance as much as possible, it is desirable to form a thin electrically insulating layer only on the surface of the fin of the heat conducting member excluding the surface in contact with the semiconductor chip. When an electrically insulating layer is also formed on the surface of the heat conducting member that contacts the semiconductor chip, the thermal resistance of the insulating layer is added in series between the semiconductor chip and the heat conducting member metal when viewed thermally, While the influence of the thermal resistance of this portion cannot be ignored, when the electrical insulating layer is formed only on the surface of the fin, the thermal resistance of the insulating layer is different from the number of fins between the heat conducting member and the housing. Accordingly, since it is added in parallel, the influence on the overall thermal resistance is small and can be almost ignored. Similarly, the same effect can be obtained when the electrically insulating layer is formed only on the surface of the fin provided on the inner surface of the housing. In the present invention, the fin of the heat conducting member or
It suffices that the electric insulating layer is formed only on the portions of the housing fins that may come into contact with each other, and the optimum method can be selected in consideration of workability, cost, etc. of forming the electric insulating layer.

さらに半導体チップの背面及びこれと接触する熱伝導
部材のベース底面の表面粗さを小さくすることによって
熱抵抗を一層下げることができる。
Further, the thermal resistance can be further reduced by reducing the surface roughness of the back surface of the semiconductor chip and the bottom surface of the base of the heat conducting member that is in contact with the back surface.

このようにして、半導体装置の熱伝導部材及びハウジ
ングに安価で、加工も簡単な金属を用いて、かつ熱抵抗
を増加させることなく、LSIチップ間の電気絶縁を確保
できるものである。
In this way, it is possible to secure electrical insulation between LSI chips by using inexpensive and easily processed metal for the heat conducting member and housing of the semiconductor device and without increasing thermal resistance.

以下、本発明の一実施例を第1図及び第2図により詳
細に説明する。これらの図において、銅あるいはアルミ
ニウムのような熱伝導性の良好な金属により作られたハ
ウジング15の内面には、多数のプレート状のフィン16が
互いに平行に設けられている。LSIチップ1の背面の伝
熱面積より大きな面積を有するアルミニウム製の熱伝導
部材17のベースの上にも、前記フィン16と同ピッチでプ
レート状の多数のフィン18が該ベースと一体に設けられ
ている。第2図に示すように、このフィン18の表面に
は、耐食性、絶縁性が極めて良好な硬質皮膜(例えばAl
2O3の膜)25が形成されている。この硬質皮膜25は、pH
を8に調整した3%酒石散アンモニウム溶液中、化成電
圧200V、室温で陽極酸化して形成し、膜圧は約100Åで
あった。また、この酸化皮膜の耐電圧は約1000Vで、LSI
チップ間の絶縁に要する耐電圧約100Vを充分満足する事
が分かった。また、この熱伝導部材17のベース面は、表
面粗さが約0.1μmに仕上げてある。
An embodiment of the present invention will be described in detail below with reference to FIGS. 1 and 2. In these figures, a large number of plate-shaped fins 16 are provided in parallel with each other on the inner surface of the housing 15 made of a metal having good heat conductivity such as copper or aluminum. A large number of plate-shaped fins 18 having the same pitch as the fins 16 are integrally provided on the base of a heat conducting member 17 made of aluminum having a larger area than the heat transfer area on the back surface of the LSI chip 1. ing. As shown in FIG. 2, on the surface of the fin 18, a hard coating (for example, Al
2 O 3 film) 25 is formed. This hard film 25 has a pH
Was adjusted to 8 and anodized in a 3% ammonium tartar powder solution at room temperature and a voltage of about 100Å. The withstand voltage of this oxide film is about 1000V,
It was found that the withstand voltage of about 100V required for insulation between chips was sufficiently satisfied. The base surface of the heat conducting member 17 has a surface roughness of about 0.1 μm.

ハウジング15のフィン16と熱伝導部材17のベース上の
フィン18とは互いに微小間隙19を保ってはめ合わされて
いる。熱伝導部材17のベースは、LSIチップ1の接続用
のはんだボール3に影響を及ぼさないようにバネ定数が
柔らかいバネ20によってLSIチップ1に押し付けられ、L
SIチップ1の背面と互いに面接触している。バネ20は、
フィン16の隙間23内に挿入され、ハウジング15に設けら
れた穴21と熱伝導部材17のベース中央に設けられた穴22
とで固定されている。ハウジング15と基板2とで囲まれ
た密閉空間24には、熱伝導率の良好なヘリウムガスが充
満されている。なお、微小間隙19内にだけ熱伝導グリー
スなどの高熱伝導性の液体を充填しても良い。
The fins 16 of the housing 15 and the fins 18 on the base of the heat conducting member 17 are fitted to each other with a minute gap 19 therebetween. The base of the heat conducting member 17 is pressed against the LSI chip 1 by a spring 20 having a soft spring constant so as not to affect the solder balls 3 for connecting the LSI chip 1,
It is in surface contact with the back surface of the SI chip 1. Spring 20
The hole 21 inserted in the gap 23 of the fin 16 and provided in the housing 15 and the hole 22 provided in the center of the base of the heat conducting member 17
It is fixed at and. The closed space 24 surrounded by the housing 15 and the substrate 2 is filled with helium gas having a good thermal conductivity. It should be noted that only the minute gap 19 may be filled with a highly heat-conductive liquid such as heat-conducting grease.

本実施例では上記のように構成したので、LSIチップ
1で発生した熱は、LSIチップ1と全面接触するアルミ
ニウム製の熱伝導部材17のベースに一旦伝えられ、該ベ
ース内で一様に拡散された後、熱伝導部材17の各フイン
18に伝わり、その後、各々のフィン18の両面に形成され
た絶縁層25及び微小間隙19に存在するヘリウムガス層を
通してハウジング15のフィン16へと伝わり、最終的にハ
ウジング15上部に取付けられている冷却器26に流れる冷
却液により持ち去られる。
Since the present embodiment is configured as described above, the heat generated in the LSI chip 1 is once transferred to the base of the aluminum heat conductive member 17 which is in full contact with the LSI chip 1, and is uniformly diffused in the base. Then, each fin of the heat conducting member 17 is
18 and then to the fins 16 of the housing 15 through the insulating layer 25 formed on both sides of each fin 18 and the helium gas layer existing in the minute gaps 19, and finally attached to the upper part of the housing 15. It is carried away by the cooling liquid flowing to the cooler 26.

本実施例により構成した半導体装置の全熱抵抗は、前
記フィン18の表面に絶縁層25を形成していない場合とほ
とんど差が無く、またLSIチップ間の電気絶縁も充分保
たれていることが分かった。
The total thermal resistance of the semiconductor device configured according to this example is almost the same as that when the insulating layer 25 is not formed on the surface of the fin 18, and the electrical insulation between the LSI chips is sufficiently maintained. Do you get it.

次に、本発明の他の実施例を説明する。前記実施例に
おいてフィン18を設けたアルミニウム製の熱伝導部材17
を、LSIチップに接触するベース面を下にして台に乗
せ、窒素プラズマ中で表面窒素処理してフィン18の表面
のみに電気絶縁膜25としての窒素アルミニウム(AlN)
の層を約100Å設けた。これを用いて、他は上記実施例
と同様にした冷却構造体を構成した。この場合にも、熱
抵抗は前記フィン18の表面に絶縁層を形成していない場
合とほとんど差が無く、またLSIチップ間の電気絶縁も
充分保たれていることが分かった。
Next, another embodiment of the present invention will be described. The heat conducting member 17 made of aluminum provided with the fins 18 in the above embodiment.
Is placed on a table with the base surface in contact with the LSI chip facing downward, and surface nitrogen treatment is performed in nitrogen plasma to form aluminum aluminum (AlN) as the electric insulating film 25 only on the surface of the fin 18.
About 100Å layers of Using this, a cooling structure similar to the above-described example was constructed. Also in this case, it was found that the thermal resistance was almost the same as that when the insulating layer was not formed on the surface of the fin 18, and the electrical insulation between the LSI chips was sufficiently maintained.

また、第6図にはフィン16を含めたハウジング内面に
電気絶縁膜25を形成した実施例を示した。
Further, FIG. 6 shows an embodiment in which the electric insulating film 25 is formed on the inner surface of the housing including the fins 16.

[発明の効果] 本発明によれば、半導体装置の熱伝導部材及びハウジ
ングを安価で、加工も簡単な金属で構成することがで
き、且つ全熱抵抗を殆んど増大させることなく、LSIチ
ップ間の電気的絶縁を確保できるので、安価に高い冷却
性能を持った半導体装置を実現できる。
[Advantages of the Invention] According to the present invention, the heat conduction member and the housing of the semiconductor device can be made of a metal which is inexpensive and easy to process, and the total thermal resistance is hardly increased. Since electrical insulation between them can be secured, a semiconductor device having high cooling performance can be realized at low cost.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の半導体装置の一実施例を示す縦断面
図、第2図は第1図における熱伝導部材の一部断面とし
た斜視図、第3図、第4図は従来の半導体チップの冷却
装置の縦断面図、第5図は、従来の半導体チップの冷却
装置の一部断面とした斜視図、第6図は本発明の半導体
装置の他の一実施例を示す縦断面図である。 1……LSIチップ、2……基板 3……はんだバンプ、4……ピン 5,11,15……ハウジング 6……シリンダ、7……ピストン 8,20……バネ、9,24……密閉空間 10,26……冷却器、12……溝 13……熱伝導板、14……板バネ 16,18……フィン、17……熱伝導部材 19……微小間隙、21,22……穴 25……電気絶縁層
FIG. 1 is a longitudinal sectional view showing an embodiment of a semiconductor device of the present invention, FIG. 2 is a perspective view showing a partial cross section of a heat conducting member in FIG. 1, and FIGS. 3 and 4 are conventional semiconductors. FIG. 5 is a vertical cross-sectional view of a cooling device for a chip, FIG. 5 is a partial cross-sectional perspective view of a conventional cooling device for a semiconductor chip, and FIG. 6 is a vertical cross-sectional view showing another embodiment of the semiconductor device of the present invention. Is. 1 ... LSI chip, 2 ... substrate 3 ... solder bump, 4 ... pin 5,11,15 ... housing 6 ... cylinder, 7 ... piston 8,20 ... spring, 9,24 ... hermetically sealed Space 10,26 …… Cooler, 12 …… Groove 13 …… Heat conduction plate, 14 …… Flat spring 16,18 …… Fin, 17 …… Heat conduction member 19 …… Small gap, 21,22 …… Hole 25: Electrical insulation layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 三吉 忠彦 茨城県日立市久慈町4026番地 株式会社 日立製作所日立研究所内 (72)発明者 大黒 崇弘 茨城県土浦市神立町502番地 株式会社 日立製作所機械研究所内 (72)発明者 小林 二三幸 神奈川県秦野市堀山下1番地 株式会社 日立製作所神奈川工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tadahiko Miyoshi 4026 Kujimachi, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi Ltd. In-house (72) Inventor Fumiyuki Kobayashi 1 Horiyamashita, Hadano City, Kanagawa Prefecture Hitachi, Ltd. Kanagawa Plant

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】回路基板上に搭載された複数個の半導体チ
ップと、該半導体チップに対向する熱伝導性金属製のハ
ウジングと、各半導体チップから発生した熱を該ハウジ
ングに伝えるために各半導体チップの表面とハウジング
との間にそれらと接触するように夫々配置された複数個
の熱伝導性金属製の熱伝導部材と、該熱伝導部材を半導
体チップの表面に押圧する弾性部材とを備えた半導体装
置において、前記熱伝導部材とハウジングとの接触面の
少なくとも一方に薄い電気絶縁層を形成したことを特徴
とする半導体装置。
1. A plurality of semiconductor chips mounted on a circuit board, a housing made of a heat conductive metal facing the semiconductor chips, and each semiconductor for transmitting heat generated from each semiconductor chip to the housing. A plurality of heat conductive metal heat conductive members, which are respectively arranged between the surface of the chip and the housing so as to contact them, and an elastic member for pressing the heat conductive members against the surface of the semiconductor chip. In the semiconductor device, a thin electric insulating layer is formed on at least one of the contact surfaces of the heat conducting member and the housing.
【請求項2】前記各熱伝導性部材は、各半導体チップの
表面に接し且つ該表面よりも大きい底面積を有するベー
スと該ベース上に一体に形成された複数のフィンとから
なり、前記ハウジングは該熱伝導部材のフィンに対して
互に挿入関係にあるフィンを有し、前記熱伝導部材のフ
ィンの表面又はハウジングのフィンの表面の少くともど
ちらか一方に薄い電気絶縁層を形成した特許請求の範囲
第1項記載の半導体装置。
2. The heat conductive member comprises a base that is in contact with the surface of each semiconductor chip and has a bottom area larger than the surface, and a plurality of fins that are integrally formed on the base. Patent for forming a thin electrically insulating layer on at least one of the surface of the fin of the heat conducting member or the surface of the fin of the housing The semiconductor device according to claim 1.
【請求項3】前記熱伝導部材またはハウジングがアルミ
ニウムで構成され、前記電気絶縁層として陽極酸化膜ま
たは窒化膜を形成したことを特徴とする特許請求の範囲
第1項又は第2項記載の半導体装置。
3. The semiconductor according to claim 1, wherein the heat conducting member or the housing is made of aluminum, and an anodic oxide film or a nitride film is formed as the electrically insulating layer. apparatus.
JP63012381A 1988-01-22 1988-01-22 Semiconductor device Expired - Lifetime JP2506885B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63012381A JP2506885B2 (en) 1988-01-22 1988-01-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63012381A JP2506885B2 (en) 1988-01-22 1988-01-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH01187840A JPH01187840A (en) 1989-07-27
JP2506885B2 true JP2506885B2 (en) 1996-06-12

Family

ID=11803693

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Country Link
JP (1) JP2506885B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2675173B2 (en) * 1990-03-02 1997-11-12 株式会社日立製作所 Electronic device cooling system
US5014117A (en) * 1990-03-30 1991-05-07 International Business Machines Corporation High conduction flexible fin cooling module
US20060087816A1 (en) * 2004-09-21 2006-04-27 Ingo Ewes Heat-transfer devices
JP5556531B2 (en) * 2010-09-17 2014-07-23 株式会社デンソー Electronic module mounting structure
JP2018141614A (en) * 2017-02-28 2018-09-13 三菱マテリアル株式会社 Heat exchange member

Also Published As

Publication number Publication date
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