JPH0568747B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data acquisition device composed of a plurality of units, and in particular to the simultaneity of data measured by each unit and the temporal correspondence with external events. Regarding improvement.

[Prior Art] Conventionally, computer systems (including systems using microprocessors) have been used to sample measurement data at a certain timing by multiple units under the control of a central processing unit (hereinafter referred to as CPU). , a data acquisition device composed of a plurality of units that stores data in a memory is well known.

FIG. 6 is a block diagram showing an example of a conventional data acquisition device of this type. In the figure, 1, 2,
3 is a measurement input/output card (this is called a unit). Here, a case where the number of units is 3 is illustrated. 4 is a dedicated synchronization bus for synchronizing units, and multiple units are connected in a zigzag manner so that they are lined up on one bus. The order in which they are connected is irrelevant to the operation.

Synchronous bus 4 has three signal lines (TRG, BUSY,
EOP). All units on the synchronous bus are electrically equal, but in a measurement sequence one unit becomes the master and the others become slaves.

The operation in such a configuration will be explained next with reference to the time chart of FIG. First, a TRG signal is given to each slave unit to start measurement. When the master is activated after the preprocessing of the slave is completed, a series of measurement sequences is started after the preprocessing of the master is completed.

When the master activates the TRG line,
Slave units connected on the bus are
Start measurement at the same time as activating the BUSY line. Deactivate the BUSY line from the slave unit after measurement. When all slaves become inactive, the BUSY line becomes H level, and the master makes the TRG line active after taking the next measurement.

In this way, all slave units perform a series of measurements in synchronization with the output of the master's TRG line.

The EOP line is a line that sends a signal to end a series of measurements, and this line can be activated by any unit, regardless of master or slave. If there is a unit that satisfies the conditions for completing a series of measurements, this EOP line becomes active at the timing when BUSY goes to H level. When this line becomes active,
All units connected on the bus complete the measurement sequence.

[Problems to be Solved by the Invention] However, in this synchronous bus type data acquisition device, the master as described above instructs the slave to start measurement using TRG after measurement, and operates according to the slowest unit. It is difficult to measure at high speed and at constant time intervals, and it is difficult to make temporal correspondence with external events (CPU
Although this is possible, it is not accurate because the operating time is long and not constant. The same applies to the start and end of measurement. ) I had a problem.

The object of the present invention has been made in view of the above points, and is to provide a data acquisition device that can perform measurements between multiple units simultaneously at high speed and that can accurately and easily correlate external events and measured data at that time. Our goal is to provide the following.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a data acquisition device comprising a plurality of measurement units, wherein the measurement unit is configured to perform measurements given from a measurement object. A signal input circuit that takes in data, a driver/receiver that indicates the input/output operation period, receives signals from the outside or inside, and sends them to the outside, and controls the input/output operations of each unit for the specified number of channels. A driver/driver that receives the signal to be executed from the outside or inside and sends it to the outside.
a receiver; a driver/receiver for receiving a signal corresponding to an external event from the outside or inside and sending it to the outside; and an input/output control circuit for outputting a signal to control input/output of each of the driver/receivers. , an internal signal generation circuit that generates a signal indicating the input/output operation period, a signal that causes each unit to perform input/output operation only on the specified channel, and a signal corresponding to an event, and a signal corresponding to an external event. When active, the measurement data from the signal input circuit is sent out with a mark corresponding to the external event added, and when the signal corresponding to the external event is inactive, the measurement data from the signal input circuit is sent out as is. a data synthesis circuit; a memory that stores the output data of this data synthesis circuit; and an interface that exchanges signals in order to provide the data in this memory to the CPU and to provide instructions from the CPU to the input/output control circuit. and timing control for simultaneously supplying in parallel a signal indicating the input/output operation period to each unit, a signal that causes each unit to perform input/output operation only on a specified channel, and a signal corresponding to an event. - Consists of a bus, one of the multiple measurement units is the master, the other measurement units are slaves, and the master sends signals indicating the input/output operation period and signals for performing input/output operations to all slaves. A signal corresponding to an external event is applied simultaneously so that the measurement sequence in each measurement unit can be started at the same time, and a mark corresponding to the external event can be added to the data of all measurement units at the same time. It is characterized by

[Function] In the present invention, one unit out of a plurality of units functions as a master and the other units function as slaves, so that the measurement sequences in each unit are started at the same time, and all measurements are performed in the data synthesis circuit. It is now possible to associate external events with data.

[Examples] Examples of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram illustrating a main part of an embodiment of a data acquisition device according to the present invention. In the figure,
Reference numeral 10 denotes a measurement target, which has multi-channel measurement points. 20 is a diagram illustrating the main parts of the data acquisition device.
21 to 24 are data acquisition units, and bus 2
5 in parallel. 26 is a CPU, which is also connected to the bus 25.

A timing control bus 27 is used to transmit a signal for controlling the timing of data collection, and is connected to each unit in an automatic manner.

In this embodiment, the unit 21 is the master,
22 to 24 are slaves, and each unit operates independently. The master unit 21 sends an R/E (run/end) signal indicating the data input/output operation period to the slave units 22 to 24, and an SMPL signal that causes each unit to perform input/output operations for a specified number of samples. (sampling pulse) signal and a MARK signal corresponding to an external event to the slave units 22 to 24.

In order to operate the unit 24 independently, input from the timing control bus 27 and output to the bus are prohibited. Note that the details will be described later.

Furthermore, the units 21 to 24 each have a dedicated connector for input and output from the bus 27, facilitating parallel connection.

The signal to be measured from the measurement target 10 is connected to each unit through N1, N2, N3, ..., Ni channels,
Achieves multi-channel data acquisition in total.

FIG. 2 is an embodiment diagram showing details of the configuration of each unit. Reference numerals 211, 212, and 213 are drivers and receivers for R/E, SMPL, and MARK signals, respectively, and all have the same configuration.
The details are shown in FIG.

R/E, SMPL, MARK input from outside
The signal is connected to terminator T. Internally generated signals (internally generated R/E, SMPL,
For INT mode using MARK),
The INT/ signal is at H level, and the internally generated signal is selected as the internal signal. In EXT mode,
The INT/ signal becomes L level, and the external signal is selected as the internal signal.

Also, if it becomes a master that outputs externally,
This is done by setting OE (output enable) to H level.

214 in FIG. 2 is an internal signal generation circuit;
Generates the internally generated signals R/E, SMPL, and MARK signals.

215 is an input/output control circuit, OE and INT/
Outputs EXT to each driver/receiver. In addition,
Separate OE and
It is also possible to give INT/.

216 is a signal input circuit that converts the signal to be measured (for example, converts an analog signal to digital) and sends the result to the data synthesis circuit 217.

The data synthesis circuit 217 includes the signal input circuit 216
The measurement data (DATA) given from the driver/receiver 213 and the mark (MARK) given from the driver/receiver 213 are combined as shown in FIG. Note that data acquisition for channels 0 to 2 is performed synchronously and in parallel, but in FIG. 4, for convenience, data acquisition is shown as being performed continuously in chronological order.

218 is a memory, and 219 is a bus interface. The contents of memory 218 are read by CPU 26 via bus 25 via bus interface 219, and control instructions from the CPU are transferred to bus 25.
The signal is applied to the input/output control circuit 215 via the interface 219. The input/output control circuit is
Generates OE and INT/signals according to CPU instructions.

The operation in such a configuration will be explained next.
FIG. 5 is a flowchart for explaining the operation. This flow will be explained below.

Determine input/output operations.

Unit 21 checks R/E input from inside or outside. When R/E is at H level, it is in the operating period and the process moves to the next step. When R/E is at the L level, the operation is complete and the sequence ends.

If it is determined in the above step that the operation period is in progress,
Wait for SMPL signal to be input.

When the SMPL signal is active, go to step; when it is inactive, go to step.

If the SMPL signal is determined to be active in the above step, scanning is started. This scan operation is performed by the signal input circuit 21 of each unit.
6 refers to the operation of measuring and converting the data to be measured.

In each unit, it is determined whether or not to add MARK to the data acquired in the above step.

When the MARK signal is active, the data obtained at the step is sent to the step, and when the MARK signal is inactive, the data obtained at the step is sent directly to the memory 21.
Store in 8.

When it is detected in the step that the MARK signal is active, the data synthesis circuit 217 in each unit adds the MARK signal (usually a 1-bit signal, but it may be a multi-bit signal) to the data obtained in the step. may also be added. The combined data is stored in each unit's own memory 218.

When one scan is completed, it is checked whether it is still in the RUN state. If it is in the RUN state, return to step and perform the same operation. This sequence ends when the END state is determined.

As described above, multi-channel data to be measured is measured simultaneously, and a MARK signal is added to the data at the time when an external event occurs, and each data is stored in the memory.

[Effects of the Invention] As explained in detail above, according to the present invention,
By connecting a plurality of measurement units in parallel via a timing control bus, input/output operation time and data acquisition are performed at the same timing without any time delay between each measurement unit. In other words, they can be synchronized.

Furthermore, since all data can be correlated with external events using the MARK signal, the present invention is particularly effective in cases where high speed and simultaneity are required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of an embodiment of a data acquisition device according to the present invention, FIG. 2 is a block diagram showing details of the unit, FIG. 3 is a diagram showing an embodiment of the driver/receiver, and FIG. FIG. 5 is a timing chart for explaining the operation, FIG. 5 is a flowchart for explaining the operation, FIG. 6 is a main part configuration diagram showing an example of a conventional data acquisition device, and FIG. 7 is a diagram of the device shown in FIG. 6. This is a time chart showing the operation. 10...Measurement object, 20...Data acquisition device,
21-24... Data measurement unit, 25... Bus, 26... CPU, 27... Timing control bus, 211, 212, 213... Driver/receiver, 214... Internal signal generation circuit, 215... Input/output control circuit, 216... Signal input circuit, 217... Data synthesis circuit, 218...
...Memory, 219...Bus interface.

Claims (1)

[Scope of Claims] 1. A data acquisition device composed of a plurality of measurement units, wherein the measurement unit has a signal input circuit that takes in measurement data provided from a measurement target, and a signal input circuit that receives a signal indicating an input/output operation period from an external device. Alternatively, a driver/receiver that receives signals from inside and sends them to the outside, and a driver/receiver that receives signals from the outside or inside that cause input/output operations of each measurement unit for the specified number of channels, and sends them to the outside. A driver/receiver for transmitting signals, a driver/receiver for receiving signals corresponding to external events from the outside or inside and transmitting them to the outside, and signals for controlling input/output of each of the driver/receivers. an internal signal generation circuit that generates an input/output control circuit that outputs, a signal that indicates an input/output operation period, a signal that causes each measurement unit to perform input/output operation only on a specified channel, and a signal that corresponds to an event; When the signal corresponding to the external event is active, the measurement data from the signal input circuit is sent with a mark corresponding to the external event added, and when the signal corresponding to the external event is inactive, the measurement data is sent from the signal input circuit. a data synthesis circuit that sends out the measured data as is; a memory that stores the output data of this data synthesis circuit; and a memory that provides data in this memory to the CPU and instructions from the CPU to the input/output control circuit. An interface that sends and receives signals, a signal that indicates the input/output operation period for each measurement unit, a signal that causes each measurement unit to perform input/output operation only on the specified channel, and a signal that corresponds to an event are simultaneously sent in parallel. It consists of a timing control bus for supplying signals to all slaves, with one measurement unit being the master and the other measurement units being slaves, and the master sending signals indicating the input/output operation period to all slaves. A signal to perform input/output operations and a signal corresponding to an external event are applied at the same time so that the measurement sequence in each measurement unit starts at the same time, and a signal corresponding to an external event is applied to the data of all measurement units. A data acquisition device characterized in that marks can be added at the same time.