JPH056859U - LED display device - Google Patents
LED display deviceInfo
- Publication number
- JPH056859U JPH056859U JP053795U JP5379591U JPH056859U JP H056859 U JPH056859 U JP H056859U JP 053795 U JP053795 U JP 053795U JP 5379591 U JP5379591 U JP 5379591U JP H056859 U JPH056859 U JP H056859U
- Authority
- JP
- Japan
- Prior art keywords
- led chips
- display device
- led
- view
- lead terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
(57)【要約】
【目的】 低電流駆動が可能で高輝度化が図れるＬＥＤ
表示装置を得る。
【構成】 １つの発光部に、同一発光波長でそれぞれ極
性の異なる少なくとも２個のＬＥＤチップ１ａ，１ｂを
各リード端子３ａ，３ｂに配列し、ＬＥＤチップ１ａ，
１ｂ間は金線２により直列接続する。
(57) [Abstract] [Purpose] LED that can be driven with low current and achieve high brightness
Get the display. [Structure] At least two LED chips 1a and 1b having the same emission wavelength and different polarities are arranged in each of the lead terminals 3a and 3b in one light emitting portion.
1b is connected in series by a gold wire 2.
Description
【０００１】[0001]
本考案はＬＥＤ表示装置に関するものである。 The present invention relates to an LED display device.
【０００２】[0002]
従来のＬＥＤ表示装置は、一般的に１つの発光部に対して、１個のＬＥＤチッ プが設けられる。すなわち、図４に示すように、１つの発光部に対して１個のＬ ＥＤチップ１をリード端子３ａに配置し、金線２により他方のリード端子３ｂに 接続して構成される。 In the conventional LED display device, one LED chip is generally provided for one light emitting unit. That is, as shown in FIG. 4, one LED chip 1 is arranged for one light emitting portion in the lead terminal 3a and is connected to the other lead terminal 3b by the gold wire 2.
【０００３】 高輝度化に対しては、図５〜図７のように１つの発光部に対して複数のＬＥＤ チップを用いることが提案されている。To increase the brightness, it has been proposed to use a plurality of LED chips for one light emitting section as shown in FIGS.
【０００４】 図５、図６は２個のＬＥＤチップ１ａ，１ｂを並列接続して使用する場合であ り、リード端子３ａにこれらチップ１ａ，１ｂを配置するとともに、金線２ａ， ２ｂでそれぞれ他方のリード端子３ｂ，３ｃ（図５ではリード端子３ｂを共通に 使用）と接続される。FIG. 5 and FIG. 6 show a case where two LED chips 1a and 1b are connected in parallel and used, and these chips 1a and 1b are arranged on the lead terminal 3a and gold wires 2a and 2b are used respectively. It is connected to the other lead terminals 3b and 3c (the lead terminal 3b is commonly used in FIG. 5).
【０００５】 図７は２個のＬＥＤチップ１ａ，１ｂを直列接続したものである。この場合、 リード端子３ａ，３ｂに各ＬＥＤチップ１ａ，１ｂを配置し、ＬＥＤチップ１ａ とリード端子３ｂ間及びＬＥＤチップ２ａとリード端子３ｃ間を金線２ａ，２ｂ により直列接続する。FIG. 7 shows two LED chips 1a and 1b connected in series. In this case, the LED chips 1a and 1b are arranged on the lead terminals 3a and 3b, and the LED chip 1a and the lead terminal 3b and the LED chip 2a and the lead terminal 3c are connected in series by gold wires 2a and 2b.
【０００６】[0006]
ところで、図５、図６のように並列接続の場合、１チップの場合と同じ電流を 供給するには２倍の電流が必要となる。又、ＬＥＤチップ１ａ，１ｂの間隔が狭 くなり、このためＬＥＤチップ１ａ，１ｂをリード端子３ａにダイボンドするＡ ｇペーストがチップ間ではい上り、各ＬＥＤチップ１ａ，１ｂのＰＮ接合部を短 絡する恐れがあった。 By the way, in the case of parallel connection as shown in FIGS. 5 and 6, a double current is required to supply the same current as in the case of one chip. In addition, the interval between the LED chips 1a and 1b becomes narrower, so the Ag paste that die-bonds the LED chips 1a and 1b to the lead terminals 3a rises between the chips, and the PN junction portion of each LED chip 1a and 1b becomes short. There was a risk of getting involved.
【０００７】 直列接続の場合は、図７のように少なくとも３つのリード端子３ａ〜３ｂが必 要となり、リードパターンが複雑、小型化し、小サイズの表示装置には適用でな いという問題がある。In the case of serial connection, at least three lead terminals 3a to 3b are required as shown in FIG. 7, the lead pattern is complicated and miniaturized, and it is not applicable to a small-sized display device. .
【０００８】[0008]
１つの発光部に、同一発光波長でそれぞれ極性の異なる少なくとも２個のＬＥ Ｄチップを各リード端子に配列し、前記ＬＥＤチップ間を金線により直列接続し てなることを特徴とする。 At least two LED chips having the same emission wavelength and different polarities are arranged in each light emitting portion in each lead terminal, and the LED chips are connected in series by a gold wire.
【０００９】[0009]
上記構成により、供給電流は１個のＬＥＤチップの場合と同様であり、低電流 駆動が可能であるとともに、リード端子はそれぞれＬＥＤチップを配置する２つ のリード端子で済み、リードのパターン配線、及び接続構造を簡略化することが できる。又、ＬＥＤチップ間は各別個のリード端子で分離され、小間隔の配置で もＰＮ接合部の短絡の恐れはない。 With the above configuration, the supply current is the same as in the case of one LED chip, low current driving is possible, and the lead terminal is only two lead terminals for arranging the LED chips. Also, the connection structure can be simplified. Further, the LED chips are separated by separate lead terminals, and there is no fear of short-circuiting the PN junction even with a small interval.
【００１０】[0010]
図１〜図３に従って本考案の実施例を説明する。 An embodiment of the present invention will be described with reference to FIGS.
【００１１】 図１において、ＬＥＤチップ１ａ，１ｂは同一波長でそれぞれ極性の異なるも のであり、リード端子３ａ，３ｂにダイボンドされている。金線２はＬＥＤチッ プ１ａ，１ｂ間でこれらを直列接続するものである。In FIG. 1, the LED chips 1a and 1b have the same wavelength but different polarities, and are die-bonded to the lead terminals 3a and 3b. The gold wire 2 connects these LED chips 1a and 1b in series.
【００１２】 なお、リード端子３ａ，３ｂはリードフレームから構成されたものであっても よいし、プリント基板等に設けられる配線パターン等で構成されるものであって もよい。The lead terminals 3a and 3b may be composed of a lead frame, or may be composed of a wiring pattern or the like provided on a printed circuit board or the like.
【００１３】 図２はセグメント型数字表示装置に適用したときの断面図であり、図３は同Ｌ ＥＤチップの配置例を示す平面図である。FIG. 2 is a cross-sectional view when applied to a segment-type numeral display device, and FIG. 3 is a plan view showing an arrangement example of the LED chips.
【００１４】 図２は１セグメント当たりの断面図を示し、底面ケース５、反射ケース６等か らなり、ＬＥＤチップ１ａ，１ｂは散乱剤を含むエポキシ樹脂７で封止されてい る。各セグメントは図３に示すように、１セグメント当たり２つのリード端子ａ −１，ａ−２，ｂ−１，ｂ−２，・・・，ｇ−１，ｇ−２よりなり、ＬＥＤチッ プ１ａ，１ｂのダイボンド、金線２による接続は図１、図２に詳しく示されると おりである。FIG. 2 shows a cross-sectional view per segment, which is composed of a bottom case 5, a reflection case 6, etc., and the LED chips 1a and 1b are sealed with an epoxy resin 7 containing a scattering agent. As shown in FIG. 3, each segment consists of two lead terminals a-1, a-2, b-1, b-2, ..., G-1, g-2 per segment. The die bond of 1a and 1b and the connection by the gold wire 2 are shown in detail in FIGS.
【００１５】 上述のとおり、数字表示装置のセグメント等のように１つの発光部に少なくと も２個のＬＥＤチップ１ａ，１ｂを配列して高輝度化が達成できるとともに、供 給される電流は、ＬＥＤチップ１ａ，１ｂが直列接続されていて、１個のＬＥＤ チップの場合と同様に低電流駆動が可能であり、又、ＬＥＤチップ１ａ，１ｂは 各別個のリード端子３ａ，３ｂに配列するもので、リードパターンの構成が簡単 でかつ小サイズの表示装置にも容易に適用できる。As described above, high brightness can be achieved by arranging at least two LED chips 1a and 1b in one light emitting part such as a segment of a numerical display device, and the supplied current is , LED chips 1a and 1b are connected in series and can be driven at a low current as in the case of one LED chip, and the LED chips 1a and 1b are arranged on separate lead terminals 3a and 3b. However, the structure of the lead pattern is simple and can be easily applied to a small-sized display device.
【００１６】 なお、セグメント型表示装置の他、本考案屋外用ＬＥＤランプ等高輝度が必要 とされる各種装置に応用して非常に有用である。In addition to the segment type display device, the present invention is very useful when applied to various devices requiring high brightness such as an outdoor LED lamp of the present invention.
【００１７】[0017]
以上のように本考案によれば、低電流駆動が可能でかつ高輝度化が達成できる 、実用価値の高いＬＥＤ表示装置が提供できる。 As described above, according to the present invention, it is possible to provide an LED display device having a high practical value, which can be driven at a low current and can achieve high brightness.
【図１】本考案の一実施例を示す要部平面図（ａ）、及
び同断面図（ｂ）である。FIG. 1 is a plan view (a) and a sectional view (b) of a main part showing an embodiment of the present invention.
【図２】セグメント型数字表示装置における断面図であ
る。FIG. 2 is a cross-sectional view of a segment type numeric display device.
【図３】セグメント型数字表示装置におけるＬＥＤチッ
プの配置例を示す平面図である。FIG. 3 is a plan view showing an arrangement example of LED chips in the segment type numerical display device.
【図４】従来例を示す要部平面図（ａ）、及び同断面図
（ｂ）である。FIG. 4 is a plan view (a) and a sectional view (b) of a main part showing a conventional example.
【図５】他の従来例を示す要部平面図（ａ）、及び同断
面図（ｂ）である。FIG. 5 is a plan view (a) and a sectional view (b) of a main part showing another conventional example.
【図６】他の従来例を示す要部平面図（ａ）及び同断面
図（ｂ）である。FIG. 6 is a plan view (a) and a sectional view (b) of a main part showing another conventional example.
【図７】他の従来例を示す要部平面図（ａ）及び同断面
図（ｂ）である。FIG. 7 is a plan view (a) and a sectional view (b) of a main part showing another conventional example.
１ａ，１ｂ ＬＥＤチップ ２ 金線 ３ａ，３ｂ リード端子 1a, 1b LED chip 2 Gold wire 3a, 3b Lead terminal
Claims (1)
ぞれ極性の異なる、少なくとも２個のＬＥＤチップを各
リード端子に配列し、前記ＬＥＤチップ間を金線により
直列接続したことを特徴とするＬＥＤ表示装置。Claims for utility model registration 1. At least two LED chips having the same wavelength but different polarities are arranged in each lead terminal for one light emitting part, and a gold wire is provided between the LED chips. An LED display device characterized by being connected in series with each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP053795U JPH056859U (en) | 1991-07-11 | 1991-07-11 | LED display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP053795U JPH056859U (en) | 1991-07-11 | 1991-07-11 | LED display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH056859U true JPH056859U (en) | 1993-01-29 |
Family
ID=12952756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP053795U Pending JPH056859U (en) | 1991-07-11 | 1991-07-11 | LED display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH056859U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS521215U (en) * | 1975-06-23 | 1977-01-07 | ||
| JP2015002317A (en) * | 2013-06-18 | 2015-01-05 | ローム株式会社 | Led light source module |
-
1991
- 1991-07-11 JP JP053795U patent/JPH056859U/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS521215U (en) * | 1975-06-23 | 1977-01-07 | ||
| JP2015002317A (en) * | 2013-06-18 | 2015-01-05 | ローム株式会社 | Led light source module |
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