JPH0567972A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To obtain an output with excellent linearity by shifting an off-level of a complementary pulse fed to a switch circuit 1 according to an output signal so as to suppress pulse leakage to the output signal. CONSTITUTION:An output signal from a hold capacitor 2 is fed back to a shift circuit 3a of a pulse shaping circuit 3 via a feedback circuit 4 and fed back to an off-level of a complementary pulse fed to a switch circuit 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample hold circuit used for preprocessing of A / D conversion.

[0002]

2. Description of the Related Art A sample and hold circuit turns on a switch circuit at the time of sampling to guide an input signal to a hold capacitor, and turns off this switch circuit at the time of holding to maintain the input signal level at the time of sampling. Circuit. In a sample and hold circuit used in an image signal processing circuit, a measuring instrument, etc., high-speed switching is required, and thus a circuit in which diodes and transistors are connected in a bridge shape may be used as a switch circuit.

FIG. 6 shows an example of a conventional sample hold circuit using a diode bridge as a switch circuit. In this sample hold circuit, the input signal is input to the hold capacitor 12 via the input buffer circuit 15 and the switch terminals 11a and 11d of the switch circuit 11. The control terminals 11b, 11 of this switch circuit 11
Pulses complementary to each other are applied to c via the pulse shaping circuit 13 when the sample hold pulse is sampled. When the complementary pulses are applied, the switch terminals 11a and 11d of the switch circuit 11 are turned on, and the hold capacitor 12 is charged to the input signal level.

Further, at the time of holding the sample hold pulse, an off-level voltage is applied to the control terminals 11b and 11c of the switch circuit 11, and the switch terminals 11a and 11c.
Since d is turned off, the input buffer circuit 15 and the hold capacitor 12 are cut off from each other. Then, the hold capacitor 12 holds the input signal level at the time of sampling, and this can be read out via the output buffer circuit 16.

[0005]

The switch circuit 11 applies a complementary pulse to the control terminals 11b and 11c to turn on all the diodes connected in a bridge shape so that the switch terminals 11a and 11d are connected to each other. To balance.

Therefore, when a signal as shown in FIG. 7 is input as an input signal to the switch terminal 11a of the switch circuit 11 shown in FIG. 6, the complementary pulses applied to the control terminals 11b and 11c are the input signals. The pulse height is shifted according to the level change of the pulse. However, since the off-level voltage applied to the control terminals 11b and 11c of the switch circuit 11 at the time of holding is always constant, the pulse amplitude of this complementary pulse changes as shown in the figure. Then, in the output signal from the switch terminal 11d,
There is a problem that the complementary pulse component applied to the switch circuit 11 at the time of sampling leaks as shown in the figure and the linearity of the output waveform is impaired. That is, in the illustrated case, an upward pulse leak occurs in the output signal from the switch terminal 11d in the portion where the input signal level is high, and the switch terminal 11 in the portion where the input signal level is low.
A downward pulse leak occurs in the output signal from d.

In view of the above circumstances, the present invention feeds back the output signal to the off level of the complementary pulse applied to the switch circuit by feeding back the output signal to the off level of the complementary pulse applied to the switch circuit. Accordingly, it is an object of the present invention to provide a sample hold circuit capable of suppressing the pulse leak to the output signal.

[0008]

A sample and hold circuit of the present invention forms a bridge shape by a pulse shaping circuit for generating a complementary pulse at the time of sampling based on a sample and hold pulse, and a complementary pulse generated by the pulse shaping circuit. A sample hold circuit comprising: a switch circuit for turning on a connected switch element; and a hold means for holding an input signal through the switch circuit,
A feedback circuit for feeding back the output signal of the holding means to the pulse shaping circuit is further provided, and the pulse shaping circuit shifts an off level at the time of holding a complementary pulse based on the output signal fed back by the feedback circuit. The shift circuit is provided to achieve the above object.

[0009]

EXAMPLES The present invention will be described below with reference to examples.

FIG. 1 shows a schematic configuration of a sample hold circuit according to the present invention. In this embodiment, the input signal is input to the hold capacitor 2 which is a holding means via the switch circuit 1. The switch circuit 1 is formed by connecting switch elements such as diodes in a bridge shape. The switch element is turned on by applying a complementary pulse to the pair of control terminals 1b and 1c, and the other switch terminal 1
It is a circuit that balances a and 1d. Therefore, when an input signal is input to the switch terminal 1a, while the complementary pulse is being applied, the input signal level also appears at the other switch terminal 1d and the hold capacitor 2 can be charged.

The sample hold pulse is input to the pulse shaping circuit 3. The pulse shaping circuit 3 is a circuit that generates a complementary pulse to be applied to the switch circuit 1 at the time of sampling based on the sample hold pulse. Further, the pulse shaping circuit 3 shifts the off level when the complementary pulse is held by the shift circuit 3a based on the output signal from the hold capacitor 2 fed back via the feedback circuit 4.

As a result, when a complementary pulse is applied to the control terminals 1b and 1c of the switch circuit 1 at the time of sampling, the pulse height of the complementary pulse is shifted according to the input signal level of the switch terminal 1a. However, during hold, the off level of the complementary pulse is shifted according to the output signal by the shift circuit 3a of the pulse shaping circuit 3, so the pulse amplitude of this complementary pulse is always constant.

Therefore, according to the sample hold circuit of the present embodiment, it is possible to suppress the pulse leak of the complementary pulse applied to the switch circuit 1 to the output signal.

This embodiment will be described more specifically with reference to FIGS. 2 and 3. The input signal is input to the input buffer circuit 5. The input buffer circuit 5 is composed of an operational amplifier with a high input impedance, and is a circuit for performing sampling without affecting the input signal. The output of the input buffer circuit 5 is connected to the switch terminal 1a of the switch circuit 1. The switch circuit 1 is a circuit in which four diodes, each having a particularly short switching time, are connected in a bridge shape. When all the diodes are turned on by applying a complementary pulse to the control terminals 1b and 1c, the switch terminals are switched. There is a balance between 1a and 1d. The switch terminal 1d of the switch circuit 1 is connected to one terminal of the hold capacitor 2 and also to the output buffer circuit 6. Hold capacitor 2
Is a capacitor for holding the level of the input signal, and the other end side is grounded. The output buffer circuit 6 is
This is a circuit that is composed of an operational amplifier with high input impedance and that allows the input signal level held in the hold capacitor 2 to be taken out with a small leak current. The output of the output buffer circuit 6 is sampled and held. Become a signal.

A sample and hold pulse for determining the timing of sampling and holding is input to the pulse shaping circuit 3. The pulse shaping circuit 3 is a circuit that outputs complementary and mutually complementary pulses at the time of sampling by inputting the inverted and non-inverted signals of the sample-hold pulse to the differential circuit 3b. Both outputs of the differential circuit 3b are connected to the control terminals 1b and 1c of the switch circuit 1, respectively.

The output of the output buffer circuit 6 is input to the shift circuit 3a of the pulse shaping circuit 3 via the feedback circuit 4. The shift circuit 3a is a differential circuit 3b.
It is a circuit that shifts the off level at the time of holding in the complementary pulse output from each according to the output signal.

The operation of the sample hold circuit having the above configuration will be described.

At the time of sampling the sample-hold pulse, the differential circuit 3b of the pulse shaping circuit 3 outputs a complementary pulse, which is applied to the control terminals 1b and 1c of the switch circuit 1. Then, all the diodes of the switch circuit 1 are turned on, and the switch terminals 1a and 1d are balanced. Therefore, when an input signal is input to the switch terminal 1a, the input signal level appears at the switch terminal 1d and the hold capacitor 2 is charged.

When the sample hold pulse is held, the output of the differential circuit 3b of the pulse shaping circuit 3 is turned off, all the diodes of the switch circuit 1 are turned off, and the input signal and the hold capacitor 2 are separated from each other. To be cut off. Therefore, during this hold, the input signal level held in the hold capacitor 2 at the previous sampling is output as an output signal via the output buffer circuit 6.

When an input signal as shown in FIG. 3 is input to the switch terminal 1a of the switch circuit 1 via the input buffer circuit 5, the pulse heights of complementary pulses applied to the control terminals 1b and 1c are increased. Varies according to this input signal as in the conventional case. However, the output signal is fed back via the feedback circuit 4 to the pulse shaping circuit 3 which applies the complementary pulse. Therefore, the differential circuit 3b in the pulse shaping circuit 3
Since the off-level output of is also shifted by the shift circuit 3a according to the output signal, the pulse amplitude of the complementary pulse is always constant as shown in the figure.

As a result, according to the sample hold circuit of this embodiment, the complementary pulse applied to the switch circuit 1 can be prevented from leaking to the output signal as shown by the waveform of the switch terminal 1d in the figure. it can.

Although the diode bridge as shown in FIG. 4 is used as the switch circuit 1 in this embodiment,
For example, a circuit in which transistors are connected in a bridge shape as shown in FIG. 5 can be used.

[0023]

As is apparent from the above description, according to the sample-hold circuit of the present invention, the off level of the complementary pulse applied to the switch circuit is shifted according to the output signal, so that the pulse to this output signal is shifted. It is possible to suppress leakage and obtain an output with excellent linearity.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing the configuration of the embodiment in more detail.

FIG. 3 is a time chart showing a waveform of each part in the embodiment.

FIG. 4 is a circuit diagram showing a configuration of a switch circuit in the embodiment.

FIG. 5 is a circuit diagram showing a configuration of a switch circuit using transistors.

FIG. 6 is a circuit diagram showing a configuration of a conventional sample hold circuit.

FIG. 7 is a time chart showing waveforms of respective parts in the conventional sample hold circuit.

[Explanation of symbols]

 1 switch circuit 2 hold capacitor 3 pulse shaping circuit 3a shift circuit 4 feedback circuit

Claims (1)

[Claims] 1. A pulse shaping circuit for generating a complementary pulse at the time of sampling based on a sample hold pulse, and a switch circuit for turning on a switch element connected in a bridge shape by the complementary pulse generated by the pulse shaping circuit. A sampling and holding circuit for holding an input signal via the switch circuit, further comprising a feedback circuit for feeding back an output signal of the holding means to the pulse shaping circuit, the pulse shaping circuit A sample-hold circuit including a shift circuit that shifts an off level when a complementary pulse is held, based on an output signal fed back by the feedback circuit.