JPH0567595A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0567595A
JPH0567595A JP22679591A JP22679591A JPH0567595A JP H0567595 A JPH0567595 A JP H0567595A JP 22679591 A JP22679591 A JP 22679591A JP 22679591 A JP22679591 A JP 22679591A JP H0567595 A JPH0567595 A JP H0567595A
Authority
JP
Japan
Prior art keywords
resist
metal
deposited film
patterning
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22679591A
Other languages
Japanese (ja)
Inventor
Tomoyuki Hikita
智之 疋田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP22679591A priority Critical patent/JPH0567595A/en
Publication of JPH0567595A publication Critical patent/JPH0567595A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To enable normal patterning of a fine metal on a sloping surface by conducting, after formation of a deposited film on the entire surface of a substrate, anisotropic etching under the etching condition that a selection ratio for the resist is high to form the resist on the slope in such a condition that a deposited layer is buried. CONSTITUTION:After an oxide film 1 is formed on a substrate, a metal 2 is formed on the oxide film 1. Moreover, after a resist 3 is formed on the metal 2, the resist 3 is patterned. Next, a deposited film 4 is formed on the entire surface of substrate including the resist 3 after the patterning. Thereafter, a mask is formed in such a condition that a deposited film 4 is buried in a recess 5 in the lateral direction generated at the time of patterning of the resist 3 by etching the deposited film 4 under the etching condition that a selection ratio for the resist 3 is high. After etching the metal 2 using the resist 3 as a mask, the resist 3 and deposited film 4 are removed and the metal 2 is patterned.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】 本発明は半導体装置の製造方法
に関し、特に微細なメタルパターンの形成方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a fine metal pattern.

【0002】[0002]

【従来の技術】 LSIの製造において、メタルのパタ
ーニングは重要なポイントであり、微細化のキーテクノ
ロジーと言える。図2に従来の方法を説明する。基板
(図示せず)上にシリコン酸化膜11を形成した後、そ
のシリコン酸化膜11上にメタル12を形成する。次
に、このメタル12上にレジスト13を形成し、マスク
10を用いて露光によりレジスト13をパターニングす
る。〔図2(a)〕。図2(b)は、レジスト13をパ
ターニングした状態である。
2. Description of the Related Art Patterning of metal is an important point in the manufacture of LSI and can be said to be a key technology for miniaturization. A conventional method will be described with reference to FIG. After forming the silicon oxide film 11 on the substrate (not shown), the metal 12 is formed on the silicon oxide film 11. Next, a resist 13 is formed on the metal 12, and the resist 13 is patterned by exposure using the mask 10. [FIG. 2 (a)]. FIG. 2B shows a state in which the resist 13 is patterned.

【0003】次に、このレジストパターンの状態でエッ
チングを行うことによりメタル12のパターニングを行
う。
Next, the metal 12 is patterned by etching in the state of this resist pattern.

【0004】[0004]

【発明が解決しようとする課題】 ところが、従来の方
法では、特に、下地の傾斜する面でのメタルのパターニ
ングは困難を極めている。これはメタルの反射率が高
く、特に、傾斜面では乱反射が生じるため、誤露光さ
れ、現像後に図2(b)に示すようにレジスト13は部
分的に細ってしまうため、正常なパターニングに悪影響
を与える。そのため図2(c)に示すようにパターニン
グされたメタル12は正常な形をとらず、部分的に欠け
た不良な形となる。このような問題は、LSIの微細化
に障害となり、デバイスの信頼性を低下させるため、改
善が望まれている。
However, in the conventional method, it is extremely difficult to pattern the metal particularly on the inclined surface of the base. This is because the metal has a high reflectance, and diffused reflection occurs particularly on the inclined surface, resulting in erroneous exposure, and the resist 13 is partially thinned after development as shown in FIG. 2B, which adversely affects normal patterning. give. Therefore, as shown in FIG. 2C, the patterned metal 12 does not have a normal shape, but has a partially defective defective shape. Such problems hinder the miniaturization of LSIs and reduce the reliability of the device, and therefore improvements are desired.

【0005】本発明は以上の問題点を解決すべくなされ
たもので、上述したような異常なエッチングを回避し
て、傾斜面での微細なメタルの正常なパターニングを可
能とする、半導体装置の製造方法を提供することを目的
とする。
The present invention has been made to solve the above-mentioned problems, and it is possible to avoid abnormal etching as described above and to perform fine patterning of fine metal on an inclined surface of a semiconductor device. It is intended to provide a manufacturing method.

【0006】[0006]

【課題を解決するための手段】 本発明の半導体装置の
製造方法は、基板上に酸化膜を形成した後、その酸化膜
上にメタルを形成し、そのメタル上にレジストを形成し
た後、そのレジストをパターニングし、次いで、そのパ
ターニング後のレジストを含む上記基板全面に堆積膜を
形成した後、上記レジストとの選択比の高いエッチング
条件下で上記堆積膜をエッチングすることにより、上記
レジストのパターニングの際に生じた横方向への凹部に
上記堆積膜が埋め込まれた状態のマスクを形成して、上
記メタルをパターニングする工程を有することによって
特徴付けられる。
According to a method of manufacturing a semiconductor device of the present invention, an oxide film is formed on a substrate, a metal is formed on the oxide film, and a resist is formed on the metal. Patterning the resist by patterning the resist and then forming a deposited film on the entire surface of the substrate including the patterned resist, and then etching the deposited film under etching conditions having a high selection ratio with the resist. It is characterized by including a step of patterning the metal by forming a mask in a state where the deposited film is embedded in a lateral concave portion generated at the time of.

【0007】[0007]

【作用】 露光によりパターニングされたレジストは、
そのレジスト下部に形成されているメタルの傾斜面の乱
反射により凹部を生じるが、次工程でその基板全面に堆
積膜を形成することにより、その凹部にはその堆積膜が
埋め込まれる。その後、レジストとの選択比の高いエッ
チング条件で異方性エッチングを行うことにより、傾斜
面のレジストは堆積膜が埋め込まれた状態に形成され
る。
[Function] The resist patterned by exposure is
Although a concave portion is formed due to diffused reflection of the inclined surface of the metal formed under the resist, the deposited film is buried in the concave portion by forming a deposited film on the entire surface of the substrate in the next step. After that, anisotropic etching is performed under etching conditions having a high selection ratio with respect to the resist, whereby the resist on the inclined surface is formed in a state where the deposited film is embedded.

【0008】[0008]

【実施例】 図1は本発明の実施例を経時的に示す模式
断面図である。以下に、図面を参照しつつ、本発明の実
施例を説明する。従来と同様の方法により、基板(図示
せず)上にシリコン酸化膜1を形成した後、そのシリコ
ン酸化膜1上にメタル2を形成する。次に、このメタル
2上にレジスト3を形成し、マスク(図示せず)を用い
てレジスト3を露光によりパターニングする。この工程
においても、上述したように、傾斜面においてはレジス
ト下部のメタル2の乱反射によって誤露光が起こるた
め、パターニングされたレジスト3は部分的に細くな
り、凹部5ができる〔図1(a)〕。
EXAMPLE FIG. 1 is a schematic sectional view showing an example of the present invention over time. Embodiments of the present invention will be described below with reference to the drawings. After the silicon oxide film 1 is formed on the substrate (not shown) by the same method as the conventional method, the metal 2 is formed on the silicon oxide film 1. Next, a resist 3 is formed on the metal 2, and the resist 3 is exposed and patterned by using a mask (not shown). Also in this step, as described above, erroneous exposure occurs on the inclined surface due to diffused reflection of the metal 2 under the resist, so that the patterned resist 3 becomes partially thin and a recess 5 is formed [FIG. 1 (a)]. ].

【0009】その後、上述した状態の基板全面にSOG
4(Spin On Glass)を回転塗布し、このSOG4を所定
の温度で乾燥し、硬化させる。この工程により、レジス
ト3が除去された部分すなわち、凹部5はSOG4が埋
め込まれた状態となる〔図1(b)〕。次に、レジスト
3との選択比の高いエッチング条件でSOG4を全面的
に異方性エッチングを行うことにより、凹部5のSOG
4は埋め込まれた状態のまま、レジスト3が再びパター
ニングされた形となる〔図1(c)〕。
After that, the SOG is formed on the entire surface of the substrate in the above-mentioned state.
4 (Spin On Glass) is spin-coated, and this SOG4 is dried and cured at a predetermined temperature. By this step, the SOG 4 is filled in the portion where the resist 3 is removed, that is, the recess 5 [FIG. 1 (b)]. Then, the SOG 4 is anisotropically etched over the entire surface under an etching condition having a high selection ratio with respect to the resist 3, so that the SOG in the recess 5 is etched.
4 is in a buried state, and the resist 3 is patterned again [FIG. 1 (c)].

【0010】そして、このように形成されたレジスト3
をマスクにしてメタル2のエッチングを行った後、レジ
スト3およびSOG4を除去することにより、メタル2
のパターニングが完成する〔図1(d)〕。なお、本発
明実施例では、レジスト3に生じた凹部5を埋め込む堆
積膜としてSOGを用いたが、このSOGに限らずステ
ップカバレージが良いければ、たとえば、PSGやP−
SiN等を用いてもよい。
Then, the resist 3 formed in this way
After the metal 2 is etched using the mask as a mask, the resist 3 and the SOG 4 are removed.
Patterning is completed [FIG. 1 (d)]. In the embodiment of the present invention, SOG is used as the deposited film that fills the recess 5 formed in the resist 3. However, if the step coverage is not limited to this SOG, for example, PSG or P-
You may use SiN etc.

【0011】以上の方法により、傾斜面の反射により誤
って露光されることにより、レジスト3が除去された部
分をSOG4で埋めることによって、反射率の高い傾斜
面においても平坦面と同様に、メタル2のパターニング
を行うことができる。
According to the above method, the portion where the resist 3 is removed by being erroneously exposed due to the reflection on the inclined surface is filled with SOG4. 2 patterning can be performed.

【0012】[0012]

【発明の効果】 以上説明したように、本発明によれ
ば、誤露光により部分的に欠けたり、細くなったりした
レジスト部分をSOGで埋め込むことにより、正常な形
のレジストに成形するようにしたから、傾斜を有するメ
タルの微細なパターニングを良好に行うことが可能とな
る。その結果、LSIの微細化を容易に行うことがで
き、しかも、デバイスの信頼性を向上させることができ
る。
As described above, according to the present invention, a resist portion that is partially chipped or thinned due to erroneous exposure is filled with SOG to form a resist having a normal shape. Therefore, fine patterning of a metal having an inclination can be favorably performed. As a result, the miniaturization of the LSI can be easily performed, and the reliability of the device can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明実施例を説明する図FIG. 1 is a diagram illustrating an embodiment of the present invention.

【図2】 従来例を説明する図FIG. 2 is a diagram illustrating a conventional example.

【符号の説明】[Explanation of symbols]

1・・・・シリコン酸化膜 2・・・・メタル 3・・・・レジスト 4・・・・SOG 1 ... ・ Silicon oxide film 2 ・ ・ ・ ・ ・ ・ Metal 3 ・ ・ ・ ・ ・ ・ Resist 4 ・ ・ ・ ・ SOG

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基板上に酸化膜を形成した後、その酸化
膜上にメタルを形成し、そのメタル上にレジストを形成
した後、そのレジストをパターニングし、次いで、その
パターニング後のレジストを含む上記基板全面に堆積膜
を形成した後、上記レジストとの選択比の高いエッチン
グ条件下で上記堆積膜をエッチングすることにより、上
記レジストのパターニングの際に生じた横方向への凹部
に上記堆積膜が埋め込まれた状態のマスクを形成して、
上記メタルをパターニングする工程を有する半導体装置
の製造方法。
1. An oxide film is formed on a substrate, a metal is formed on the oxide film, a resist is formed on the metal, the resist is patterned, and then the patterned resist is included. After the deposited film is formed on the entire surface of the substrate, the deposited film is etched under an etching condition having a high selection ratio with the resist, so that the deposited film is formed in the concave portion in the lateral direction generated during the patterning of the resist. Form a mask with the embedded
A method for manufacturing a semiconductor device, comprising the step of patterning the metal.
JP22679591A 1991-09-06 1991-09-06 Manufacture of semiconductor device Pending JPH0567595A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22679591A JPH0567595A (en) 1991-09-06 1991-09-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22679591A JPH0567595A (en) 1991-09-06 1991-09-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0567595A true JPH0567595A (en) 1993-03-19

Family

ID=16850737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22679591A Pending JPH0567595A (en) 1991-09-06 1991-09-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0567595A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8205755B2 (en) 2006-03-22 2012-06-26 3M Innovative Properties Company Filter media

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8205755B2 (en) 2006-03-22 2012-06-26 3M Innovative Properties Company Filter media

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