JPH0567582A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a capacitor and a field-effect transistor which have a structure wherein an electrostatic breakdown is hard to cause even when the surface of a semiconductor substrate is electrified positively by an ion beam in an ion implantation process. CONSTITUTION:A semiconductor device is formed by the manufacturing method, of the semiconductor device, which is featured in such a way that the area of a region which is not overlapped with a counter electrode 14b in a diffusion layer 12 is equal to the area of the counter electrode 14b by the following: a process to form the diffusion layer 12 on a semiconductor substrate 10; a process to form an insulating film 13; a process to form a conductor thin film 14a; and a process wherein the conductor thin film 14a is patterned and the counter electrode 14b is formed. By this constitution, the electrification amount of a diffusion-layer region 15 by an ion beam in an ion implantation operation becomes equal to the electrification amount of the counter electrode 14b, no potential difference is caused between the diffusion layers 12, 15 and the counter electrode 14b, and no electric field is applied to the capacitor insulating film 13 which is sandwiched between the diffusion layer 12 and the counter electrode 14b. As a result, no electrostatic breakdown of the capacitor insulating film 13 is caused.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, which prevent damage to an insulating film due to charging of the surface of a semiconductor substrate by an ion beam during ion implantation.

[0002]

2. Description of the Related Art An ion implantation technique, which is a technique for introducing impurities in a semiconductor device manufacturing technique, is widely used because the implantation amount can be accurately controlled.

The ion implantation technique is a technique for ionizing an impurity element, then mass spectrometrically selecting a desired ion species, accelerating it to a predetermined acceleration energy, and introducing necessary impurities into a semiconductor substrate. Further, it is necessary to cover the region where the impurities need not be introduced with a substance having a sufficient blocking ability so that the impurities cannot reach the semiconductor substrate. As a mask material for this purpose, a photoresist which is an organic photosensitive film is generally used.

A conventional example will be described below. Figure 4 (a)
(E) is a figure explaining the process of forming a diffusion layer and forming a capacitor by ion-implanting arsenic on a semiconductor substrate using a conventional ion-implantation technique. Here, a p-type silicon substrate is used as the semiconductor substrate, and arsenic (As) is used as the implanted ion species. In FIG. 4, 40 is p
Type silicon substrate, 41 is a field oxide film, 42 is As
A diffusion layer for a capacitor formed by injecting
43 is a capacitor insulating film, 44a is a polysilicon film, 4
4b is a polysilicon counter electrode formed by patterning the polysilicon film 44a, 45 is an electrode diffusion layer formed by high-concentration implantation of As, 46 is an interlayer insulating film, 47,
48 is an electrode.

First, as shown in FIG. 4A, a 5000 Å thick field oxide film 4 is formed on a p-type silicon substrate 40.
Arsenic (As) acceleration energy 50K after forming 1
Implantation is performed with eV and an implantation dose of 1 × 10 ¹³ cm ^-2 to form a capacitor diffusion layer 42.

Next, as shown in FIG. 4B, a 200 Å thick capacitor insulating film 43 is deposited by oxidation, and a 2000 Å thick polysilicon film 44 is deposited by a CVD method. Next, as shown in FIG. 4C, the polysilicon counter electrode 44b and the capacitor insulating film 43 are patterned and formed. Then, as shown in FIG. 4B, the electrode diffusion layer 45 for taking out the electrode 47 from the capacitor diffusion layer 42 is injected with high concentration of As (120 KeV, injection amount 1
× 10 ¹⁵ cm ^-2 ). Next, as shown in FIG. 4 (e), an interlayer insulating film 46 made of SiO ₂ and having a thickness of 2000 Å is formed by a sputtering method, and electrodes 47, 48 made of an aluminum alloy are formed.
To form.

[0007]

However, the electrode diffusion layer 45 shown in FIG. 4D is formed by the above method.
In the case of forming As by injecting As in a high concentration, the positively charged ion beam of As is generated by the polysilicon counter electrode 44.
Since it is injected into both the surface b and the surface on the electrode diffusion layer 45, if the area of the polysilicon counter electrode 44b and the area of the electrode diffusion layer 45 are different, the total amount of charged charges is different.

Therefore, the potentials of the polysilicon counter electrode 44b and the electrode diffusion layer 45 are different and the capacitor insulating film 43 is different.
An electric field may be applied to the capacitor insulating film 43 to cause dielectric breakdown.

In view of the above points, the present invention provides a semiconductor device including a capacitor and a field effect transistor having a structure in which electrostatic breakdown is less likely to occur even when the surface of a semiconductor substrate is positively charged by an ion beam, and a method of manufacturing the same. The purpose is to do.

[0010]

In order to achieve this object, the present invention has a structure in which the area of the region of the diffusion layer not covered by the counter electrode is equal to the area of the counter electrode.

[0011]

With this configuration, the amount of charge in the diffusion layer region by the ion beam at the time of ion implantation is equal to the amount of charge in the counter electrode, and there is no potential difference between the diffusion layer and the counter electrode, and the diffusion layer and the counter electrode are sandwiched. Since no electric field is applied to the formed capacitor insulating film, electrostatic breakdown of the capacitor insulating film does not occur.

[0012]

1 (a) to 1 (e), a diffusion layer is formed and a capacitor is formed by ion-implanting arsenic on a semiconductor substrate using the ion-implantation technique according to the first embodiment of the present invention. It is a figure explaining a process. Here, a p-type silicon substrate is used as the semiconductor substrate, and arsenic (As) is used as the implanted ion species. In FIG. 1, 10 is a p-type silicon substrate, 11 is a field oxide film, 12 is a diffusion layer for capacitors formed by implanting As, 13 is a capacitor insulating film, 14a is a polysilicon film, and 14b is a polysilicon counter electrode. , 15 is an electrode diffusion layer formed by high-concentration implantation of As, 16 is an interlayer insulating film, 1
Reference numerals 7 and 18 are electrodes. 1 (a) and 1 (b) are basically the same as FIGS. 4 (a) and 4 (b) of the conventional example, and a description thereof will be omitted. That is, the feature of the present invention is that a pattern is formed so that the area of the electrode diffusion layer 15 is equal to the area of the polysilicon counter electrode 14b, as shown in FIGS.
That is, As was injected. After that, as shown in FIG. 1E, a thickness of SiO _{2 of} 200 is formed by the CVD method.
Electrodes 17 and 18 made of an aluminum alloy are formed on the 0 Å interlayer insulating film 16 by a sputtering method.

When the electrode diffusion layer 15 shown in FIG. 1D is formed by injecting As at a high concentration as in the first embodiment, a positively charged ion beam of As is generated. It is injected into both surfaces of the polysilicon counter electrode 14 and the electrode diffusion layer 15. At this time, the polysilicon counter electrode 14
And the area of the electrode diffusion layer 15 are equal, the total amount of charged electric charge is equal. Therefore, the polysilicon counter electrode 1
4 and the electrode diffusion layer 15 have the same potential, no electric field is applied to the capacitor insulating film 13, and
Dielectric breakdown is suppressed.

As a result, the breakdown rate of the capacitor insulating film 13 is 14% (capacitor insulating film area 500 μm ² ,
The area of the electrode diffusion layer was 24 μm ² , but in the present invention, the area could be reduced to 2% (capacitor insulating film area 500 μm ² , electrode diffusion layer area 500 μm ² ).

2 (a) to 2 (d) illustrate a step of forming a p-type source region and a p-type drain region of a p-channel MOS transistor in a complementary MOS semiconductor integrated circuit according to the second embodiment of the present invention. FIG.

In FIG. 2, 20 is an n-type silicon substrate,
21 is a p-type well, 22 is a gate oxide film, 23 is a polysilicon layer, 24 is a field oxide film, 25 is an ion implantation window, 26 is a photoresist layer, 27 is an ion implantation layer, 28
Is a p-type diffusion layer.

First, as shown in FIG. 2A, a p-type well 21 for forming an n-channel MOS transistor is selectively formed inside the n-type silicon substrate 20, and the p-type well 21 is formed on the surface of the n-type silicon substrate 20. A gate electrode composed of a 200 Å thick gate oxide film 22 and a 500 Å thick polysilicon layer 23 in a predetermined portion, and a 5000 Å thick field oxide film 2
After forming No. 4, a photoresist is applied in a thickness of 1 μm, and exposure and development processes are performed to form a photoresist layer (light-shielding layer) 26 having an ion implantation window 25. Then, heat treatment is performed at a temperature of 160 ° C. for about 20 minutes.

Next, as shown in FIG. 2B, boron (B) implantation is performed to form source and drain regions in the n-type silicon substrate portion exposed in the ion implantation window 25. Here, boron trifluoride (BF ₃ ) was used as the ion source gas, and implantation was performed with an acceleration energy of 50 KeV, an ion beam current of 6 mA, and an implantation dose of 1 × 10 ¹⁵ cm ^-2 . At this time, the time required for the injection is about 300 seconds. By the above steps, the photoresist layer 26 on the n-type silicon substrate on which the boron ion (B ⁺ ) implantation layer 27 is formed is removed by using the oxygen plasma method or the like, and the state of FIG. Then, by performing annealing for activating the implanted B ⁺ and heat treatment for diffusion, a p-type diffusion layer 28 to be a source and a drain as shown in FIG. 2D is formed.

When the ion implantation layer 27 is formed by implanting B as shown in FIG. 2B as in the second embodiment, a positively charged ion beam of B is applied to the gate electrode. Implanted on the surfaces of both the polysilicon layer 23 and the ion implantation window 25. At this time, the polysilicon layer 2 of the gate electrode
Since the area of No. 3 and the area of the ion implantation window 25 are equal, the total amount of charged electric charge is equal. Therefore, the potentials of the polysilicon layer 23 of the gate electrode and the ion implantation window 25 become equal, the electric field is not applied to the gate oxide film 22, and the gate oxide film 22
Dielectric breakdown is suppressed. As a result, the gate oxide film 22
The conventional destruction rate was 6% (gate oxide film area: 5.2 μm ² ,
Source and drain forming diffusion layer area 8.2 .mu.m ²⁾ a had been, but 2% in the present invention (gate oxide film area 5.2 .mu.m ^2,
The area of the diffusion layer for forming the source / drain could be reduced to 5.2 μm ² ).

3A to 3E are steps of forming a diffusion layer by ion-implanting arsenic on a semiconductor substrate by using the ion-implantation technique according to the third embodiment of the present invention to form a capacitor. It is a figure explaining. Here, a p-type silicon substrate, an implanted ion species and arsenic (As) are used as the semiconductor substrate. In FIG. 3, 30 is a p-type silicon substrate, 31 is a field oxide film, 32 is a capacitor diffusion layer formed by implanting As, 33 is a capacitor insulating film, 34a is a polysilicon film, and 34b is a polysilicon counter electrode. , 35 are electrode diffusion layers formed by high-concentration implantation of As, 36 are interlayer insulating films, 3
Reference numerals 7 and 38 are electrodes, and 39 is a photoresist layer.

First, as shown in FIG. 3A, a 5000 Å thick field oxide film 3 is formed on the p-type silicon substrate 30.
1 is formed and then As is injected with an acceleration energy of 50 KeV and an injection amount of 1 × 10 ¹³ cm ⁻² to form a capacitor diffusion layer 32.
To form.

Next, as shown in FIG. 3B, a capacitor insulating film 33 having a thickness of 200Å is deposited by oxidation, and a polysilicon film 34a having a thickness of 2000Å is deposited by the CVD method. Next, as shown in FIG. 3C, the polysilicon counter electrode 34b and the capacitor insulating film 33 are patterned and formed. After that, as shown in FIG. 3D, the electrode diffusion layer 35 for taking out the electrode 37 from the capacitor diffusion layer 32 is injected with high concentration of As (120 KeV, injection amount 1 × 10 ¹⁵ cm ^-2 ). To form. At this time, the exposed area of the polysilicon counter electrode 34b is covered with the photoresist layer 39 so as to be equal to the area of the electrode diffusion layer 35. Then, as shown in FIG. 3 (e), a thickness of 2000 Å made of SiO ₂ is formed by the CVD method.
Electrodes 37 and 38 made of an aluminum alloy are formed on the inter-layer insulation film 36 by sputtering.

When the electrode diffusion layer 35 shown in FIG. 3D is formed by injecting As at a high concentration as in the third embodiment, a positively charged ion beam of As is generated. It is injected into both surfaces of the polysilicon counter electrode 34b and the electrode diffusion layer 35. At this time, the polysilicon counter electrode 3
Since the exposed area of 4b and the area of the electrode diffusion layer 35 are equal, the total amount of charged electric charge is equal. Therefore, the polysilicon counter electrode 34b and the electrode diffusion layer 35 have the same potential, an electric field is not applied to the capacitor insulating film 33, and dielectric breakdown of the capacitor insulating film 33 is suppressed.

As a result, the breakdown rate of the capacitor insulating film is
Conventional 14% (exposed area of polysilicon counter electrode 500μ
m ² and electrode diffusion layer area 24 μm ² ), but in the present invention, 4% (exposed area of polysilicon counter electrode 24 μm
m ² and the diffusion layer area for the electrode 24 μm ² ).

It is a matter of course that the structure as in the above embodiment may be applied to some capacitors or MOS transistors on the semiconductor substrate or may be applied to all capacitors or MOS transistors.

[0026]

As described above, according to the present invention, the area of the diffusion layer not covered with the counter electrode is equal to the area of the counter electrode. Electrostatic breakdown of the capacitor insulation film because the charge amount of the counter electrode becomes equal, no potential difference occurs between the diffusion layer and the counter electrode, and no electric field is applied to the capacitor insulation film sandwiched between the diffusion layer and the counter electrode. It is possible to provide a semiconductor device and a method for manufacturing the same, in which

[Brief description of drawings]

FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a process sectional view of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a process sectional view of a method for manufacturing a semiconductor device of a conventional example.

[Explanation of symbols]

10 p-type silicon substrate (semiconductor substrate) 11 field oxide film 12 capacitor diffusion layer (diffusion layer) 13 capacitor insulating film 14a polysilicon film 14b polysilicon counter electrode 15 electrode diffusion layer (region of diffusion layer not covered by counter electrode) ) 16 Interlayer insulating film 17, 18 Electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/336 29/784

Claims (6)

[Claims] 1. A semiconductor device comprising a diffusion layer provided on a semiconductor substrate, a capacitor insulating film, and a counter electrode,
A semiconductor device, wherein an area of a region of the diffusion layer which is not covered with the counter electrode is equal to an area of the counter electrode. 2. In all semiconductor devices including a diffusion layer, a capacitor insulating film, and a counter electrode provided on a semiconductor substrate, the area of a region of the diffusion layer not covered by the counter electrode is the area of the counter electrode. Semiconductor devices characterized by being equal. 3. A semiconductor device comprising a source / drain region, a gate insulating film, and a gate electrode provided on a semiconductor substrate, wherein the source / drain region and the gate electrode have the same area. 4. A semiconductor device comprising a source / drain region, a gate insulating film, and a gate electrode provided on a semiconductor substrate, wherein the source / drain region and the gate electrode have the same area. apparatus. 5. A method of manufacturing a semiconductor device, wherein a capacitor including a diffusion layer, an insulating layer, and a conductor thin film is formed on a semiconductor substrate, wherein an area of a region of the diffusion layer which is not covered by the counter electrode is an area of the counter electrode. A method of manufacturing a semiconductor device, wherein the conductor thin film is patterned so as to be equal. 6. A step of forming a diffusion layer on a semiconductor substrate, a step of forming an insulating film, a step of forming a conductor thin film, a step of patterning the conductor thin film to form a counter electrode, and the diffusion. Covering the diffusion layer or the counter electrode with a photoresist layer so that the exposed area of a region of the layer that does not overlap the counter electrode is equal to the area of the counter electrode; and performing ion implantation from the photoresist layer. A method of manufacturing a semiconductor device, comprising: