JPH0567165A - Coverage rate measuring system for logic circuit - Google Patents

Coverage rate measuring system for logic circuit

Info

Publication number
JPH0567165A
JPH0567165A JP3229332A JP22933291A JPH0567165A JP H0567165 A JPH0567165 A JP H0567165A JP 3229332 A JP3229332 A JP 3229332A JP 22933291 A JP22933291 A JP 22933291A JP H0567165 A JPH0567165 A JP H0567165A
Authority
JP
Japan
Prior art keywords
coverage rate
measurement
coverage
condition
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3229332A
Other languages
Japanese (ja)
Inventor
Ichiro Okubo
一郎 大窪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Solution Innovators Ltd
Original Assignee
NEC Software Hokuriku Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Software Hokuriku Ltd filed Critical NEC Software Hokuriku Ltd
Priority to JP3229332A priority Critical patent/JPH0567165A/en
Publication of JPH0567165A publication Critical patent/JPH0567165A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To check the detailed operation range in a logic circuit by measuring the frequency in passage of an accessed address. CONSTITUTION:When the coverage rate is measured at the time of generating a simulation model of the logic circuit and executing the simulation, a coverage rate measurement object setting part 1 sets the measurement object of the coverage rate, and a measurement object condition setting part 2 sets the coverage rate measurement condition of the measurement object. A coverage rate measurement memory adding part 3 adds a coverage rate measuring memory into the logic simulation model, and a connection changing part 4 changes the connection in accordance with addition of the coverage rate measuring memory. A condition discriminating part 5 discriminates the condition at the time of executing the simulation; and in the case of success of the condition, a passage frequency setting part 6 sets the frequency in passage as the measurement result to the coverage rate measuring memory, and a coverage rate editing and display part 7 displays the measurement result.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、論理回路のシミュレー
ションモデルの作成及びシミュレーションの実行の際の
網羅率測定方式に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of measuring a coverage rate when creating a simulation model of a logic circuit and executing the simulation.

【0002】[0002]

【従来の技術】従来、論理回路のシミュレーション時に
は、論理回路が設計通り行われたか否かの評価の1つと
して、対象となる回路がすべてトレース(検証)された
か否かの程度、すなわち、網羅率の測定が行われてい
る。
2. Description of the Related Art Conventionally, when simulating a logic circuit, one of the evaluations as to whether or not the logic circuit has been performed as designed is the degree of whether all the target circuits have been traced (verified), that is, the coverage. The rate is being measured.

【0003】そして、このような網羅率の測定を行う場
合、シミュレーション実行時において判定条件が成立す
ると、網羅率測定用追加メモリにアクセスアドレス格納
レジスタのアクセスアドレスで示されるアドレスに
“1”を書き込んでいた。
When such a coverage ratio is measured, if a determination condition is satisfied during execution of the simulation, "1" is written in the address indicated by the access address of the access address storage register in the additional memory for coverage measurement. I was out.

【0004】[0004]

【発明が解決しようとする課題】上述した従来の論理回
路の網羅率測定方式は、判定条件が成立したときに、網
羅率測定用追加メモリに“1”を書き込んでいたが、ア
クセスされたアドレスの通過回数については測定してい
なかった。そのため、論理回路内の詳細な動作範囲がチ
ェックできないという欠点があった。
In the above-mentioned conventional coverage measurement method for logic circuits, when the determination condition is satisfied, "1" is written in the additional memory for coverage measurement. The number of passages was not measured. Therefore, there is a drawback that the detailed operation range in the logic circuit cannot be checked.

【0005】[0005]

【課題を解決するための手段】本発明は、論理回路のシ
ミュレーションモデルの作成及びシミュレーションの実
行の際の網羅率測定方式であって、前記網羅率の測定対
象を設定する第1の手段と、前記測定対象の網羅率測定
条件を設定する第2の手段と、前記論理シミュレーショ
ンモデル内に網羅率測定用メモリを追加する第3の手段
と、前記網羅率測定用メモリの追加による接続変更を行
う第4の手段と、前記シミュレーション実行時に条件判
定を行う第5の手段と、この第5の手段が条件成立を判
定したとき、前記網羅率測定用メモリに測定結果である
通過回数を設定する第6の手段と、この第6の手段によ
る前記測定結果を表示する第7の手段とを備えている。
SUMMARY OF THE INVENTION The present invention is a method of measuring a coverage rate when creating a simulation model of a logic circuit and executing a simulation, and first means for setting a measurement target of the coverage rate, Second means for setting the coverage measurement condition of the measurement target, third means for adding a coverage measurement memory in the logic simulation model, and connection change by adding the coverage measurement memory A fourth means, a fifth means for making a condition judgment at the time of executing the simulation, and a fifth means for setting a number of passages as a measurement result in the coverage measuring memory when the fifth means judges that the condition is satisfied. 6 means and 7th means for displaying the measurement result by the 6th means.

【0006】[0006]

【実施例】次に本発明の実施例について図面を参照して
説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0007】図1は本発明の一実施例の構成を示すブロ
ック図である。図中、網羅率測定対象設定部1は、回路
記述内の網羅率測定を行う対象を入力する。測定対象条
件設定部2は、網羅率測定対象のアクセスするアドレス
を格納するレジスタを設定する。また、アクセスアドレ
ス格納レジスタのアドレスが、所定の条件を満たさない
と真のアクセスアドレスと認められないようなときの条
件設定を行う。網羅率測定メモリ追加部3は、網羅率測
定結果を格納するメモリであり、そのメモリを回路内に
追加を行う。接続変更部4は、測定対象条件設定部2で
設定されたレジスタ群と、網羅率測定メモリ追加部3と
で追加した網羅率測定メモリの接続を行う。以上によ
り、網羅率測定の可能なシミュレーションモデルが作成
される。次に、シミュレーション実行部の処理として、
条件は判定部5は、シミュレーションモデルのシミュレ
ーション実行中に、測定対象条件設定部2で設定した条
件が成立したか否かの判定を行う。条件成立時に測定結
果である通過回数設定部6は、条件成立時にどのアドレ
スをアクセスしたかを調べ、網羅率測定メモリの同一ア
ドレス内の値に“1”を加算した値を設定する。網羅率
編集表示部7は、シミュレーションの終了後、網羅率測
定用追加メモリ内の測定結果の編集出力として、“0”
でないアドレスの数をカウントして網羅率を出力する。
また、メモリ内の値は動作回数を示す。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the coverage measurement target setting unit 1 inputs a target for which the coverage measurement is performed in the circuit description. The measurement target condition setting unit 2 sets a register that stores an address accessed by the coverage ratio measurement target. Further, condition setting is performed when the address of the access address storage register cannot be recognized as a true access address unless a predetermined condition is satisfied. The coverage percentage measurement memory addition unit 3 is a memory for storing the coverage percentage measurement result, and adds the memory to the circuit. The connection changing unit 4 connects the register group set by the measurement target condition setting unit 2 and the coverage measuring memory added by the coverage measuring memory adding unit 3. As described above, a simulation model capable of measuring the coverage rate is created. Next, as the processing of the simulation execution unit,
The condition determination unit 5 determines whether or not the condition set by the measurement target condition setting unit 2 is satisfied during the simulation of the simulation model. When the condition is satisfied, the passing count setting unit 6 which is the measurement result checks which address is accessed when the condition is satisfied, and sets a value obtained by adding “1” to the value in the same address of the coverage measurement memory. After the simulation is completed, the coverage percentage edit display unit 7 displays “0” as the edited output of the measurement result in the additional memory for coverage percentage measurement.
Count the number of non-addresses and output the coverage.
The value in the memory indicates the number of operations.

【0008】続いて、本実施例の処理について説明す
る。
Next, the processing of this embodiment will be described.

【0009】図2は本発明の網羅率測定のイメージを示
す図である。
FIG. 2 is a diagram showing an image of coverage rate measurement according to the present invention.

【0010】まず、網羅率測定対象設定部1は、回路記
述内の網羅率測定対象11を設定する。また、測定対象
条件設定部2は、網羅率測定対象となるアクセスアドレ
スをアクセスアドレス格納レジスタ12に設定する。そ
して、アクセスアドレス格納レジスタ12のアドレス
が、所定の条件を満たさないと真のアクセスアドレスと
認められないようなときの条件値を条件レジスタ13に
設定する。網羅率測定メモリ追加部3は、網羅率測定結
果を格納する網羅率測定用追加メモリ14を回路内に追
加を行う。このメモリ追加により接続変更部4は、測定
対象条件設定部2で設定されたアクセスアドレス格納レ
ジスタ12,条件レジスタ13と網羅率測定メモリ追加
部3とで追加した網羅率測定用追加メモリ14との接続
を行う。以上により、網羅率測定の可能なシミュレーシ
ョンモデルが作成される。次にシミュレーション実行部
の処理として、条件判定部5は、シミュレーションモデ
ルのシミュレーション実行中に、測定対象条件設定部2
で設定した条件レジスタ13の条件値が成立したか否か
の判定を行う。そして、測定結果設定部6は、条件成立
時にアクセスアドレス格納レジスタ12のアドレスを求
め、網羅率測定用追加メモリ14(初期値は全て0とす
る)の同一アドレス内の値に“1”を加算した値を書き
込む。網羅率編集表示部7は、シミュレーションの終了
後、網羅率測定用追加メモリ14内の測定結果の編集出
力として、“0”でないアドレスの数をカウントして網
羅率を出力する。また、網羅率測定用追加メモリ14内
の値は、動作回数を示すため、動作回数の多いアドレス
を求める事ができる。
First, the coverage measurement target setting unit 1 sets a coverage measurement target 11 in the circuit description. The measurement target condition setting unit 2 also sets an access address to be a coverage measurement target in the access address storage register 12. Then, a condition value is set in the condition register 13 when the address of the access address storage register 12 cannot be recognized as a true access address unless a predetermined condition is satisfied. The coverage rate measurement memory addition unit 3 adds a coverage rate measurement additional memory 14 for storing the coverage rate measurement result in the circuit. Due to the addition of the memory, the connection changing unit 4 includes the access address storage register 12 and the condition register 13 set by the measurement target condition setting unit 2 and the additional memory 14 for coverage ratio measurement added by the coverage ratio measurement memory addition unit 3. Make a connection. As described above, a simulation model capable of measuring the coverage rate is created. Next, as the processing of the simulation execution unit, the condition determination unit 5 determines that the measurement target condition setting unit 2 is executing during the simulation execution of the simulation model.
It is determined whether or not the condition value of the condition register 13 set in step 1 is satisfied. Then, the measurement result setting unit 6 obtains the address of the access address storage register 12 when the condition is satisfied, and adds “1” to the value in the same address of the additional memory 14 for coverage measurement (all initial values are 0). Write the specified value. After the simulation is completed, the coverage percentage edit display unit 7 counts the number of addresses that are not “0” and outputs the coverage percentage as an edited output of the measurement result in the additional memory for coverage percentage measurement 14. Further, since the value in the additional memory 14 for coverage measurement indicates the number of operations, it is possible to obtain an address having a large number of operations.

【0011】[0011]

【発明の効果】以上説明したように本発明は、論理シミ
ュレーションモデル内に網羅率測定用メモリを追加する
と共に、シミュレーション実行時における条件成立時に
は測定結果である通過回数を書き込むことにより、論理
回路内の詳細な動作範囲がチェックできるという効果を
有する。
As described above, according to the present invention, the memory for measuring the coverage rate is added to the logic simulation model, and the number of passages which is the measurement result is written when the condition is satisfied during the execution of the simulation. The effect is that the detailed operation range of can be checked.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

【図2】本実施例における処理のイメージを示す図であ
る。
FIG. 2 is a diagram showing an image of processing in the present embodiment.

【符号の説明】[Explanation of symbols]

1 網羅率測定対象設定部 2 測定対象条件設定部 3 網羅率測定メモリ追加部 4 接続変更部 5 条件判定部 6 通過回数設定部 7 網羅率編集表示部 11 網羅率測定対象 12 アクセスアドレス格納レジスタ 13 条件レジスタ 1 Coverage rate measurement target setting section 2 Measurement target condition setting section 3 Coverage rate measurement memory addition section 4 Connection changing section 5 Condition determination section 6 Pass count setting section 7 Coverage rate edit display section 11 Coverage rate measurement target 12 Access address storage register 13 Condition register

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 論理回路のシミュレーションモデルの作
成及びシミュレーションの実行の際の網羅率測定方式で
あって、前記網羅率の測定対象を設定する第1の手段
と、前記測定対象の網羅率測定条件を設定する第2の手
段と、前記論理シミュレーションモデル内に網羅率測定
用メモリを追加する第3の手段と、前記網羅率測定用メ
モリの追加による接続変更を行う第4の手段と、前記シ
ミュレーション実行時に条件判定を行う第5の手段と、
この第5の手段が条件成立を判定したとき、前記網羅率
測定用メモリに測定結果である通過回数を設定する第6
の手段と、この第6の手段による前記測定結果を表示す
る第7の手段とを備えることを特徴とする論理回路の網
羅率測定方式。
1. A coverage ratio measuring method for creating a simulation model of a logic circuit and executing a simulation, comprising: first means for setting a measurement target of the coverage ratio; and coverage ratio measurement conditions for the measurement target. Setting means, a third means for adding a coverage measuring memory in the logic simulation model, a fourth means for changing the connection by adding the coverage measuring memory, and the simulation. Fifth means for performing condition determination at the time of execution,
When the fifth means determines that the condition is satisfied, the number of passages which is the measurement result is set in the coverage ratio measurement memory.
And a seventh means for displaying the measurement result obtained by the sixth means.
JP3229332A 1991-09-10 1991-09-10 Coverage rate measuring system for logic circuit Pending JPH0567165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3229332A JPH0567165A (en) 1991-09-10 1991-09-10 Coverage rate measuring system for logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3229332A JPH0567165A (en) 1991-09-10 1991-09-10 Coverage rate measuring system for logic circuit

Publications (1)

Publication Number Publication Date
JPH0567165A true JPH0567165A (en) 1993-03-19

Family

ID=16890498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3229332A Pending JPH0567165A (en) 1991-09-10 1991-09-10 Coverage rate measuring system for logic circuit

Country Status (1)

Country Link
JP (1) JPH0567165A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7327063B2 (en) 2005-07-07 2008-02-05 Denso Corporation Rotary electric machine for vehicles

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7327063B2 (en) 2005-07-07 2008-02-05 Denso Corporation Rotary electric machine for vehicles

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