JPH0567006A - Memory controller - Google Patents

Abstract

PURPOSE:To decrease the occupancy volume of a circuit part using a memory chip by providing a means which reads out a parity value corresponding to a data value from a parity chip at the time of reading the data value from one of the plural data memory chips. CONSTITUTION:A memory controller 1 is equipped with a NAND circuit 13 which inputs a chip selection signal, and a NAND circuit 12 which inputs a writing signal. Then, the control of a parity chip reading signal is operated by the output of a flip flop 14 which inputs the output of the NAND circuit 12 at a set terminal S side, and inputs the output of the NAND circuit 13 at a reset terminal R side, and the output of an NAND circuit 15 which inputs the chip selection signal, the writing signal, and the output of the flip flop 14. Also, a parity chip selection signal is prepared by a decoder 8 which inputs address signals A17-A19, and a parity value prepared by a parity value preparing part 6 is written in the appropriate area of a parity memory chip 2 by the pertinent signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller, and more particularly to a memory controller which generates a parity value when writing a data value to a memory and controls writing and reading of the generated parity value.

[0002]

2. Description of the Related Art In a conventional memory controller, in order to prevent an error in writing and reading which occurs when writing data into a memory for storing data and taking out the written data in the memory, it is necessary to prevent an error in the memory. Each time data is written to the memory controller, the memory controller generates a parity value according to the content of the data to be written, and when this memory controller writes the data to the memory chip for data storage, the memory chip for data storage When the above-mentioned parity value is written in a memory chip provided as a parity value storage chip installed in a one-to-one correspondence with each other and predetermined data is read from this memory chip for data storage A parity value is generated based on the data read out, and a pair of data is stored in the memory chip for storing the read data. The parity value corresponding to the above-mentioned data is read from the memory chip for storing the parity value corresponding to, and both parity values are compared. If both parity values match, the correct data is read. If the two parity values are different from each other, it is determined that the read data has an error.

[0003]

In the conventional memory controller described above, a parity value is generated, and the parity value is written in the memory chip by this parity value, and an error caused when reading and writing data read from this memory is prevented. In this case, since a memory chip that stores the parity value in a one-to-one correspondence with each memory that stores data is used, other memory chips that store actual data In addition, since the same number of memory chips for storing parity values are used as the memory chips for storing data, a large number of memory chips are required when the number of memory chips for storing data is large, and the number of memory chips is also large. Due to the large number, there is a drawback that the occupied volume of the memory unit using such a memory controller becomes large.

According to the present invention, a small number of memory chips for storing parity values can be used for a memory chip for storing a plurality of data, and the occupied volume of a circuit portion using such a memory chip is small. It is to provide a memory controller capable of

[0005]

SUMMARY OF THE INVENTION A memory controller according to the present invention is provided with a plurality of target memories each having a chip select signal, a read signal, a write signal, an address signal and a data value which are input from the outside. Controlling the writing and reading of a data value to and from the data memory chip, and generating a parity value according to a predetermined processing method for this data value when the data value is input, and a parity memory for storing a specific parity value. When the read signal is stored in the chip, the data value at the address specified by the address signal is read from one of the plurality of data memory chips specified by the address signal, and the read data is read. This data when regenerating the parity value for the value and storing said data value The parity value stored in the memory for storing the specific parity value is read out and compared with the regenerated parity value, and when these two parity values are different, an error signal is generated and externally generated. In the memory controller which outputs the parity chip read signal and the parity chip write signal for the specific one parity memory chip, the memory controller outputs and generates the chip select signal, the read signal and the write signal. Means for writing the data value to one of the plurality of data memory chips in response to the write signal, the data value within an area pre-allocated for each data memory chip in the parity memory chip. The parity value is written in the area corresponding to the data chip in which the data is written. One of the parity values stored in the parity chip when the data value is read from one of the memory chips, the read data value is read from the area corresponding to the data memory chip from which the data value is read. And a means for reading the parity value corresponding to.

[0006]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an example of the connection relationship between the memory controller of the present invention and a memory chip.
2 is a block diagram showing an embodiment of the memory controller of the present invention used in FIG. 1, and FIG. 3 is a timing chart for explaining the operation of the memory controller shown in FIGS. 1 and 2.

The memory controller 1 of the present invention includes a parity memory chip 2 for storing a parity value generated by the memory controller 1 and data (not shown) sent from the outside. Are connected to data memory chips 3 and 4 which store the stored data in response to a write command from the device and output the stored data in response to a read command from the outside. Six similar memory chips are similarly connected between 3 and 4.

As the parity memory chip 2, a SRAM (static RAM) having a capacity of 256 KB (kilobit) for inputting / outputting a value in units of 8 bits is used in FIGS. 1 and 2, and the data memory chips 3 and 4 are omitted. The six memory chips are 1 MB (128 K × 8 bits) SRAM that inputs / outputs a value in units of 8 bits.

The read timing is the same as in normal memory access. When the chip select signal (CS) from an external device (not shown) changes from a high level (logical value "1") to a low level (logical value "0"), the memory controller 1 outputs the parity memory chip 2 The parity chip select signal (PMCS signal) and the parity chip read signal (PMOE) are set to low levels and added to the parity chip memory 2, and reading of the memory is started. The parity values (PDB0 to PDB7) stored so far are separately output from the parity memory chip 2.

In addition, in FIG. 1 and FIG.
The shaded lines that are parallel to each other in the book indicate that there are a plurality of similar connections and that a plurality of these connections are omitted. For example, 1 for PDB0 to PDB7
If there is a wire connection and two diagonal lines are drawn on this wire, it means that there is one wire as PDB0, and similarly, that there are separate wires from PDB1 to PDB7. There is.

Further, the above-mentioned chip select signal CS is shifting to the low level, and the address signals A17 to A1
When 9 is input, the data chip read signal MCS
Any one of 0 to MCS7 becomes the low level, and one of the eight data memory chips 3 to 4 which is the connection destination is selected.

When the read signal (RD) becomes low level, the data chip read signal (MOE) becomes low level in synchronization with this, and the memory controller 1 causes the address signals A0 to A16 in the selected data memory. The data value is read from the address specified by. The memory controller 1 regenerates the parity value based on the read data value. How to generate the parity value from the data value may be determined in advance. The memory controller 1 also reads the R read from the parity memory chip 2.
The parity value corresponding to the above-mentioned regenerated parity value among the parity values from DB0 to RDB7 is extracted using the low level signal of the signals from MCS0 to MCS7. The extracted parity value is the parity value that has already been generated at the time of writing the corresponding data value in the data memory chip and stored in the parity memory chip 2.

The memory controller 1 compares the regenerated parity value and the parity value read and extracted from the parity chip 2 and if there is a difference between the two, generates an error signal (PE) and outputs it to the outside.

The comparison of the parity values is performed when the read signal (RD) applied from the outside rises from the low level to the high level (time X in FIG. 3). At the write timing, when the CS signal changes from high level to low level,
The memory controller 1 uses the parity chip read signal (PM
The parity value is read from the parity memory chip 2 to the parity memory chip 2 by setting the OE signal) to a low level. Then, a write signal (WR signal) input from the outside
When is shifted from the high level to the low level, the PMOE signal is masked and the level is set to the high level. At this time, the memory controller 1 internally latches the parity value read from the parity memory chip 2, and then sets the parity chip write signal (PMWE) to a low level in synchronization with the write signal WR. Parity memory chip 2
Write the parity value to. The parity value is the write signal WR
Data value D added from the outside when is low level
The memory controller 1 generates the parity value used for the above-described writing based on B0 to DB7.

The memory controller 1 uses the data chip select signals MCS0 to MCS7 generated based on the externally applied address signals A17 to A19 to generate only one of the eight bits in the parity memory chip. A value is written, and the remaining 7 bits are directly written with the value read from the parity memory chip 2 prior to this writing. Data memory chips 3 to 4
Up to 8 data memory chips can be written data values to the data chip select signals MCS0 to MCS7.
Only one of these is set to a low level in the memory controller 1 based on the address signals A17 to A19, and this low level data chip select signal is output to the target data memory chip. Address signals A0 to A1 separately added from the outside in the data memory chip to which the data chip select signal of
Write the externally applied data value to the address specified by 6.

The memory controller of the present invention shown in the block diagram of FIG. 2 receives a chip select signal as input, delays the signal for a predetermined time, and then outputs a delayed signal and the chip select signal. N having two outputs of the delay circuit 21 as inputs
An AND circuit 13 and a NAND circuit 12 having a second input which is an output of a delay circuit 22 which outputs a signal delayed by a preset time with a write signal as a first input;
The output of the NAND circuit 12 is input to the set terminal S side, and N
A flip-flop 14 having the output of the AND circuit 13 as the input on the reset terminal R side, and a NAND having the chip select signal, the write signal, and the output of the flip-flop 14 as the inputs
The output of the circuit 15 controls the parity chip read signal.

At the write timing, when the write signal WR changes from high level to low level (time Y in FIG. 3), the output of the NAND circuit 12 becomes low level.
Since the flip-flop 14 is set and the output to the NAND circuit 15 becomes high level, the output of the NAND circuit 15 becomes high level. That is, the parity chip read signal PMOE is no longer active.

After that, when the chip select signal CS changes from the low level to the high level, the flip-flop 15
Is reset, the parity chip read signal PMO
E is determined by the levels of the chip select signal CS and the write signal WR.

For example, when the chip select signal CS goes low, the parity chip read signal PMOE goes low, that is, in the active state.

External address signals A17 to A for designating any one of the eight data memory chips 3 to 4.
19 and a parity chip select signal PMCS is input by the decoder 8 which receives the parity chip select signal PMCS.
When S is at a low level, a data chip select signal MCS0 for selecting one of the above-mentioned data memory chips
~ Generate MCS7. The data chip select signal connected to any one data memory chip selected from the above-mentioned data chip select signals becomes low level. That is, when the data memory chip 3 is selected, only the data chip select signal MCS0 becomes low level.

The parity value is externally added or one of the data values DB0 to DB7 read from the data chip selected by the data chip select signal is provided in the memory controller 1 in the parity value generating section. Input to 6. It is generated based on the data value input by a predetermined generation method. At the time of write timing, the parity values are eight selectors 19 to 20 (six selectors are omitted).
One bit is output from any one of the above. The parity chip select signal PMCS and the parity chip write signal PM input to the NOR gate 18 at the write timing.
Since WE becomes low level and the output of the NOR gate 18 becomes high level, all the tri-state buffers 23 and 24 controlled by this output (the same tri-state buffer is omitted besides this) are all provided. Since the selectors 19 and 20 and the like are in the 0 impedance state, the parity value passes through these tristate buffers and is output to and written in the parity memory chip 2.

At the read timing, the NOR gate 1
The output of 8 becomes a low level, and the parity value read from the parity memory chip 2 at this time is input from the right side of the tri-state buffers 23 and 24, but the tri-state buffers 23 and 24 have a high impedance. Therefore, the selector 7, which does not reach the selectors 19 and 20 and reaches the terminals on the input side of the selector 7 and the input side of the register 11, outputs the parity value corresponding to the data memory chip designated by the address signals A17 to A19. Select from the parity values PDBIN0 to PDBIN7 read from the TA memory chip and EXOR
Output to the input side of the gate 16. This EXOR gate 1
The parity value output from the parity value generating unit 6 described above with respect to the data value read from any one of the data memory chips 3 to 4 is also input to 6. EXOR gate 1
6 becomes a low level state when the above-mentioned two inputs are different, and this state is output as an error signal to the outside via the register 17.

The register 11 latches the parity value read from the parity memory chip 2 just before writing the parity value in the parity memory chip 2 and EXORs it.
Output to gates 9 and 10. The selectors 19 and 20 described above are controlled by the data chip select signal, and when the data chip select signal is at a low level, the parity value connected to the terminal A side is selected and output.
When the level is high, the signal connected to the terminal B side is selected and output.

As is clear from the above description, all the parity values generated when writing data values to a plurality of data memory chips are stored in one parity memory chip, and these data memory chips are used to store the parity values. When reading data, the parity value corresponding to the read data value can be retrieved from the aforementioned parity memory chip.

[0026]

As described above, by using the memory controller of the present invention, when data values are stored in a plurality of data memory chips, the parity value is stored in one parity memory chip. When reading this data value from the plurality of data memories described above, it is possible to read the stored parity value corresponding to this data value from the above-mentioned parity memory chip. The number of parity memory chips used can be reduced as compared to the case of using the memory controller described in (1) above, and therefore, the occupied volume of the memory system can be made smaller than before.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example in which a memory controller of the present invention and a memory chip are connected.

FIG. 2 is a block diagram showing an embodiment of the memory controller shown in FIG.

FIG. 3 is a timing chart illustrating the operation of the memory controller shown in FIG.

[Explanation of symbols]

 1 Memory Controller 2 Parity Memory Chip 3 Data Memory Chip 4 Data Memory Chip 5 OR Gate 6 Parity Value Generator 7 Selector 8 Decoder 9 EXOR Gate 10 EXOR Gate 11 Register 12 NAND Circuit 13 NAND Circuit 14 Flip-Flop 15 NAND Circuit 16 EXOR Gate 17 Register 18 NOR Gate 19 Selector 20 Selector 21 Delay Circuit 22 Delay Circuit 23 Tri-State Buffer 24 Tri-State Buffer

Claims (1)

[Claims] 1. Writing data values to a plurality of data memory chips by inputting a chip select signal, a read signal, a write signal, an address signal and a data value, which are externally input to a plurality of target memories. When reading is controlled and when the data value is input, a parity value is generated by a predetermined processing method for this data value and stored in a parity memory chip for storing a specific parity value, and the read signal is input. In this case, the data value at the address specified by the address signal is read from one of the plurality of data memory chips specified by the address signal, and the parity value for the read data value is regenerated and the data is read. When storing a value, a memory for storing the specific parity value corresponding to this data value In the memory controller which reads the parity value stored in the memory and compares it with the regenerated parity value and generates an error signal when the two parity values are different from each other, and outputs the error signal to the outside. Specific 1 from the read signal and the write signal
Means for generating and outputting a parity chip read signal and a parity chip write signal for each of the parity memory chips, and the data value in one of the plurality of data memory chips according to the write signal. When writing, the parity value is written in an area corresponding to a data chip in which the data value is written in an area pre-allocated for each data memory chip in the parity memory chip. When the data value is read from one of the memory chips, the data read out from the area corresponding to the data memory chip in which the data value is read out of the parity values stored in the parity chip. And a means for reading a parity value corresponding to the value.