JPH0566734A - Display control device - Google Patents

Abstract

PURPOSE:To obtain an excellent display in accordance with a sense of an operator and the working environment by operating a knob, etc., provided, for example, on an external part of a display device by an operator and selecting an interlace mode corresponding to the operating quantity. CONSTITUTION:An interlace mode setting knob 26i is provided by standing side by side with a knob for brightness volume at a lower side part of a frame of the display device 26. By operating the knob 26i by the operator, a thinning line number in the interlace can be selected from a thin line number to a coarse one. Namely an operating quantity of the knob 26i is A/D converter by an A/D converter 26t, and it is inputted in a conversion table 53 as a selection signal SEL. In the conversion table 53, an interlace table in accordance with the selection signal SEL is selected. Thus the display corresponding to the liking of the operator or the working environment is available and the flexibility for the system of the display device is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device,
More specifically, the present invention relates to a display control device for a display device using a ferroelectric liquid crystal as an operation medium for display update and having a display element capable of maintaining a display state updated by application of an electric field or the like.

[0002]

2. Description of the Related Art Generally, in information processing systems and the like, a display device is used as an information display means having a visual representation function of information, and a CRT display device is widely known as such a display device. ..

In the display control of the CRT display device, the writing operation of the system side CPU to the video memory as the display data buffer and the reading and displaying operations of the display data from the video memory by the CRT controller are independently executed. It

In the case of the display control of the CRT as described above, the writing of the display data to the video memory for changing the display information and the operation of reading the display data from the video memory and displaying it are independent. The program on the information processing system side has an advantage that desired display data can be written at any timing without the need to consider the display timing at all.

On the other hand, since the CRT requires a certain length in the thickness direction of the display screen, the volume of the CRT becomes large as a whole, and it is difficult to reduce the size of the entire display device.
Further, this impairs the degree of freedom in using the information processing system using such a CRT as a display, that is, the degree of freedom in installation location, portability, and the like.

A liquid crystal display (hereinafter referred to as LCD) can be used as a display device that compensates for this point. That is, according to the LCD, the display device as a whole can be downsized (particularly thin). Some of these LCDs include ferroelectric liquid crystal (FLC: Ferroelectric Liquid Crystal).
There is a display using a liquid crystal cell (hereinafter referred to as "FLCD: FLC display"), and one of its features is that the liquid crystal cell has a storage property of a display state against the application of an electric field. That is, in FLCD, the liquid crystal cell is sufficiently thin, and the elongated FLC molecules in the liquid crystal cell are oriented in the first stable state or the second stable state depending on the direction of application of the electric field. However, each alignment state is maintained. Due to such bistability of the FLC molecule, FLCD has a memory property. Details of such FLC and FLCD are described in, for example, Japanese Patent Application No. 62-76357. The FLCD has the above-mentioned memorability, but the display update operation of the FLC is relatively slow. Therefore, for example, cursor movement, character input, scrolling, etc., the display must be immediately rewritten. It may not be possible to follow changes in information.

The FLCD having such contradictory characteristics is
To derive from or supplement these properties,
Various driving modes for the display are possible. That is, in the refresh drive in which the scan lines on the display screen are sequentially and continuously driven similarly to the CRT and other liquid crystal display devices, there is a relatively long time margin in the drive cycle. In addition to this refresh driving, partial rewriting driving for updating the display state of only the portion (line) corresponding to the change on the display screen and interlaced driving for driving by thinning out the scanning lines on the display screen are possible.
Then, the partial rewriting drive or the interlace drive can improve the followability to the change of the display information.

On the other hand, if such an FLCD can be used as a display device of an information processing system while being compatible with a CRT, the flexibility of the system can be increased and its value can be increased.

[0009]

As described above, since various driving modes are possible in the FLCD, display information (character, character,
It is important that an appropriate drive mode is selected according to a line drawing, a natural image, etc.) and a display change mode (still image, moving image, scroll, etc.).

By the way, as one of the driving modes of the FLCD,
The interlaced drive described above is suitable when only the display of a plurality of predetermined ranges on the display screen is changed or updated, such as when inputting characters, or when the movement of a graphic of a predetermined size is displayed. It is a driving mode.

That is, according to this interlace drive, in addition to the normal interlace in which a predetermined number of scan lines on the display screen are thinned out and driven one line at a time, in a block made up of a plurality of scan lines, one line at a time is continuously provided. It is also possible to drive the scanning lines so that the scanning lines between the blocks are thinned, or to randomly access the scanning lines (the number of scanning lines to be thinned is random). Therefore, if an appropriate interlace drive mode (interlace mode) is selected according to the display information and the mode of display change, it is possible to perform display with high display quality.

Further, if the operator can arbitrarily set the interlace mode, it is possible to obtain a good display according to the operator's feeling and working environment.

On the other hand, when the FLCD is used for the display device of the information processing system while having compatibility with the CRT, the CPU on the system side exclusively outputs the display data and its address for display change to the display device side as described above. It will only be transferred. Therefore, how to reliably recognize the display information and the display change mode based on the transfer of the display data and the address becomes a problem.

The object of the present invention is made based on the above-mentioned viewpoint. The object of the present invention is to meet the preference of the operator of the display device and the working environment in which the display device is placed.
An object is to provide a display control device that enables selection of an optimum interlace mode.

[0015]

Therefore, according to the present invention,
In a display control device of a display device, which comprises a display element capable of holding an updated display state and drives the display element based on display data designated by an address, a scanning line formed of the display element Is supplied from among the plurality of interlace data, which is data of the address for interlace driving for thinning and driving, and which is capable of supplying a plurality of interlace data different depending on the number of thinned lines. Selecting means for the operator of the display device to select arbitrary interlace data, and interlace data supply control means for supplying the interlace data selected via the selecting means,
It is characterized by having.

[0016]

With the above arrangement, the operator can select the interlace mode according to the operation amount by operating the knob or the like provided on the outer shape of the display device, for example. ..

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an information processing system in which an FLC display device having a display control device according to an embodiment of the present invention is used as a display device for displaying various characters and image information.

In the figure, 11 is a CPU that executes control of the entire information processing system, 13 is a main memory that stores a program executed by the CPU 11 and is used as a work area at the time of execution, and 14 is a CPU that runs through the CPU 11. Instead of a DMA controller (Direct Memory Access Controller) that transfers data between the main memory 13 and the various devices that make up this system.
troller, hereafter referred to as DMAC). 15 is Ethernet
LAN (local area network) 16 such as (by XEROX) and the LAN interface between this system, 17
It is an input / output device (hereinafter referred to as I / O) that has ROM, SRAM, RS232C type interface, etc. Various external devices can be connected to the I / O 17. Reference numerals 18 and 19 are a hard disk device and a floppy disk device as external storage devices, respectively, and 20 is a disk interface for connecting signals between the hard disk device 18 and the floppy disk device 19 and this system. 21 is an inkjet printer capable of relatively high resolution recording,
A printer that can be configured by a laser beam printer or the like, and 22 is a printer interface for making a signal connection between the printer and this system. 23 is a keyboard for inputting character information such as various characters and control information, 24 is a mouse as a pointing device, 25 is a key interface for connecting signals between the keyboard 23 and the mouse 24 and this system. is there. Reference numeral 26 denotes an FLC display device (hereinafter, also referred to as FLCD) whose display is controlled by an FLCD interface 27 as a display control device according to an embodiment of the present invention. It has a display screen as a medium. Reference numeral 12 denotes a system bus including a data bus, a control bus, and an address bus for connecting signals between the above-mentioned devices.

In the information processing system in which the above-described various devices are connected, the system user generally
Operate while responding to various information displayed on the display screen of FLCD26. That is, characters supplied from the external device connected to LAN16, I / O 17, hard disk 18, floppy disk 19, scanner 21B, keyboard 23, mouse 24,
Image information and the like, operation information related to the user's system operation stored in the main memory 13 is displayed on the display screen of the FLCD 26, and the user edits the information and gives an instruction operation to the system while viewing this display. Here, each of the above-described various devices and the like constitutes display information supply means for the FLCD 26.

(First Embodiment) FIG. 2 is a block diagram showing details of the FLCD interface 27 according to the first embodiment of the present invention.

In the figure, 31 is an address bus driver,
Reference numeral 32 is a control bus driver, and 33, 43, 44, 45 are data bus drivers, each of which is connected to each bus of the system bus 12. The absolute address data when the CPU 11 accesses the system video RAM (hereinafter also referred to as VRAM) for rewriting the display contents, etc., is the address bus driver.
It is given to the access monitor circuit 50 via 31. The absolute address (data) input to the access monitor circuit 50 is
It is converted into a line address (data) corresponding to the scan line on the display screen, and depending on the write signal supplied from this circuit, the FIFO (A) memory 36 or FIFO (B)
The data is selectively written in the memory 37. This FIFO (A) or FI
The selection of FO (B) is made according to the switching of the switch S1. The FIFO (A) 36 and FIFO (B) 37 are FIFO (First In First Out) memories that read data in the order in which they were written, and the lines written in these FIFO (A) 36 and FIFO (B) 37. The address data is selectively read according to the switching of the second switch S2.

The access monitor circuit 50 also generates an icon detection signal E when the preset address data of the icon and the address data accessed by the CPU 11 match, as will be described in detail with reference to FIG. .. Then, this icon detection signal is input to the conversion table 53.

Further, the access monitor circuit 50 discriminates the address data for the CPU 11 to access the memory 41 during a predetermined period, and if a different address is accessed, outputs the data to the sampling counter 34, and the counter 34 outputs this data. Count the number of data taken. This count is
It is given to the synchronization control circuit 39 and can be used to determine the ratio of partial rewriting and refresh driving.

The absolute address supplied to the FLCD interface 27 of this embodiment via the address bus driver 31 is also input to the address selector 35, whereby the CP
U 11 can access the video memory 41.

The address data read from the FIFO (A) 36 or the FIFO (B) 37 and the address data output from the address counter 38 and passed through the address conversion table 53, which will be described later, are switched by the third switch S3. In accordance with the above, both are selectively applied to one input portion of the address selector 35 via the address conversion circuit 47. The address counter 38 increments the line address of the video memory 41 by "1" to generate address data for refresh driving the entire display screen. The timing of generating the address data is determined by the synchronization control circuit 39. Controlled.

The synchronization control circuit 39 is composed of the switches S1 and S
2 and S3 switching control signals and a data transfer request signal to the memory controller 40 described later are also generated. The horizontal control signal (HSYNC) generated by the FLCD 26 side is controlled every time the display drive for one line of the display screen is performed by controlling the timing of generating the data transfer request signal and the switching timing of the switches S1, S2 and S3 by the synchronous control circuit 39.
According to.

The control signal from the CPU 11 is given to the memory controller 40 via the control bus driver 32, and the memory controller 40 responds to the control signal by the address selector 35 and the video memory 41.
To control. That is, the memory controller 40 has a memory access request signal output from the CPU 11 when rewriting the data in the video memory 41 and a data transfer request signal output from the synchronization control circuit 39 when displaying the data in the video memory 41. And the output from the address selector 35 is switched according to this, and one of the two address data given to the input part of the address selector 35 is selected and given to the video memory 41.

The video memory 41 stores display data and is composed of a dual port DRAM (dynamic RAM). The display data supplied via the data bus driver 33 is written in the portion designated by the address from the address selector 35, and the video memory 41
The display data stored in the display data designated by the address from the address selector 35 is read out and displayed on the FLCD 26 via the driver receiver 42.
Further, the driver / receiver 42 supplies the horizontal synchronization signal HSYNC from the FLCD 26 to the synchronization control circuit 39.

Further, via the data bus driver 43,
Data for setting the ratio between partial rewriting and refresh driving is given to the synchronous control circuit 39.

The FLC panel of the FLCD 26 is provided with a temperature sensor 26a for detecting its temperature.
The output signal of 26a is sent to the CPU1 via the data bus driver 44.
Transferred to 1.

In the configuration shown in FIG. 2 above, when the CPU 11 changes the display, the address of the video memory 41 corresponding to the rewriting of the desired data is the memory controller.
Given to 40. In response, the memory controller 40
Then, the memory access request signal of CPU11 and the synchronous control circuit
Arbitration with the data transfer request signal from 39 is performed. When the access on the CPU 11 side obtains the right, the memory controller 40 makes the address selector 35
On the other hand, switching is performed so that the address from the address driver 31, that is, the address currently accessed by the CPU 11 is selected as the address to be given to the video memory 41. At the same time, a control signal is generated from the memory controller 40 to the video memory 41, and data is read / written via the data bus driver 33, that is, data is rewritten in the video memory 41. At this time, the address data accessed by the CPU 11 is stored in the FIFO (A) 36 or the FIFO (B) 37 via the access monitor circuit 50 and the switch S1 and is used in the transfer of display data described later. In this way, the display data access method seen from the CPU 11 is the same as in the CRT.

On the other hand, when data is read from the video memory 41 and transferred to the FLCD 26 for display, a data transfer request is issued from the synchronization control circuit 39 to the memory controller 40, and the address of the switch S3 is set as an address for the video memory 41. According to the switching, the address on the address counter 38 or the FIFO side is selected by the address selector 35 after passing through the address conversion circuit 47. At the same time, a control signal for data transfer is generated from the memory controller 40, the display data of the line of the corresponding address is transferred from the memory cell of the video memory 41 to the shift register, and the driver is driven by the control signal of the serial port.
Output to 42.

The synchronization control circuit 39, as described above, uses the FLCD 26.
By switching the switch S3 on the basis of the horizontal synchronizing signal HSYNC from, the cycle for completely refreshing the display screen or the partial rewriting cycle for rewriting the line accessed by the CPU 11 is caused. Here, the full refresh cycle is a cycle in which lines constituting a display screen are sequentially driven for display, and this cycle is accessed according to addresses sequentially incremented by an address counter 38 as described later. This is possible by changing the lines one by one. Further, the partial rewriting cycle of the access line is to rewrite the line accessed by the CPU 11 within a predetermined time immediately before the cycle.

The address conversion table 53 includes a table for directly outputting the address data input from the address counter 38 and a plurality of interlace tables for converting these data into addresses that can be displayed in the interlace mode. One of these tables is selected according to the icon detection signal E from the access monitor circuit 50 described in detail in FIG.

As the interlace table, as will be described later with reference to FIGS. 12 and 13, there are provided a plurality of interlace mode tables in which the number of thinning lines is constant and a plurality of interlace mode tables in which the number of thinning lines change irregularly. Equipped.

Further, the address conversion circuit 47 restores the line address data corresponding to each scanning line of the display screen to the address data for accessing the video memory 41.

In this way, the address data for accessing the video memory 41 for displaying is basically the address data for refreshing the entire screen of the FLC display 26 in accordance with the switching of the switch S3. The address data for rewriting the partial line accessed by the CPU 11 to change the display content and the address data are output in a time division manner. However, the icon detection signal E from the access monitor circuit 50 causes the address of the partial rewriting or refresh. Besides, the address of the interlace mode suitable for a predetermined display state can be set.

FIG. 3 is an access monitor circuit shown in FIG.
It is a block diagram which shows the detail of 50.

In FIG. 3, reference numeral 501 denotes a first comparison circuit, which is used when the access address of the CPU 11 input via the address driver 31 and a plurality of types of icon addresses stored in the first register 46A match. The detection signal E is output. This icon address means a predetermined address which the CPU 11 always accesses when selecting an icon. That is, the first register 46A stores the address of each of the plurality of icons 10 displayed on the display screen of the FLCD 26 as shown in FIG.
When the cursor 2 is moved to point to the icon 1 such as "input paper" and is selected by clicking the mouse or the like, the first comparison circuit 501 outputs the detection signal E corresponding to the icon 1. And this icon detection signal E
Inputs into the conversion table 53 and selects the optimum conversion table for the icon 1 called "input paper". In particular,
When the icon "input paper" is selected, the display screen of the FLCD 26 displays a space 4 for inputting characters and the like as shown in FIG. Then, characters and the like input by the operator's key operation are sequentially displayed in the space 4. Therefore, possible display change modes (modes) in the case of this "input paper" display are display of characters and the like in response to pressing of a key, cursor movement, scrolling, and the like. Therefore, as a display drive mode suitable for each of these display change modes, a non-interlace mode (sequential drive without thinning lines. That is, refresh drive. In the present invention, this non-interlace mode is regarded as one of the interlace modes. Yes)) table. As a result, in particular, characters such as scrolling are prevented from being scattered, and characters or the like can be surely recognized even during scrolling.

In the display mode of "input paper", when the display changes relatively quickly, for example, when the cursor is moved, the display of the movement of the cursor will be described in detail with reference to FIG. Since line rewriting compensates for this and an appropriate display is made, there is no problem even if the non-interlaced (refresh) mode is set as the display drive mode in this "input paper" mode.

As another example of the interlace mode selection according to the icon setting, when the icon "graphic" is set, for example, the 4-interlace mode as described later in FIG. 12 is selected.

Referring again to FIG. 3, an address conversion circuit 502 converts an absolute address accessed by the CPU 11 into a line address. Ie address bus driver
The address input to the access monitor circuit via 31 is an absolute address in the VRAM on the system side and is converted into a line address corresponding to the display screen of the FLCD 26.

Reference numeral 503 is a comparison circuit, which determines whether the access address of the CPU 11 is in the display area or the work area of the system side VRAM, and when the access address is in the display area, to that effect. Is output.

That is, when the CPU 11 accesses the VRAM on the system side for display control, it accesses not only the display area but also the work area. As a result, the CPU access address input to the access monitor circuit 50 includes the work area address. Therefore, the comparison circuit
The address to be input in 503 is determined, and only when this address is in the display area of the VRAM, it is written in the FIFO (A) 36 or the FIFO (B) 37 as described later. As the configuration of the comparison circuit 503, for example, a comparison circuit that determines whether the upper 2 digits of the VRAM address is 10 or less may be used. In this case, when the upper two digits of the address input to the comparison circuit 503 is 10 or less, the fact that it is the address of the display area is output.

Reference numeral 505 is a latch comparison circuit, and the comparison circuit 50
Upon receiving the output indicating that the display area is the address data of the display area, the address data is fetched from the address conversion circuit 502 and compared with the address data fetched and latched during the same sampling period. If the comparison is not a match, the newly fetched address data is latched and is output to the FIFO memory 36 (37). At the same time, an output indicating that a different line is accessed is output. This prevents access to overlapping lines in the video memory 41. The output indicating access to the different line is also transferred to the sampling counter 34, and the sampling counter 34 counts this output.

504 is a FIFO control circuit, which is a comparison circuit 503.
The write signal is output to the FIFO memory 36 (37) in response to the AND between the output indicating that the display area is from the display area and the output indicating that the latch comparison circuit 505 is accessing to a different line, and the latch circuit is output to this memory. Permits writing of address data input via the 505.

FIG. 6 is a timing chart of each signal in the time division drive. A basic operation of alternately performing the refresh operation and the line rewriting operation in time division will be described with reference to FIG.

Here, an example is shown in which the refresh cycle is performed in units of 4 lines and the access line rewriting cycle is performed in units of 3 lines.

In FIG. 6, REE / ACS is a timing at which a full refresh cycle and an access line rewrite cycle are alternately generated. The full refresh cycle is "1" and the access refresh is "0". Indicates a line rewrite cycle. Further, T _a represents the time of the full refresh cycle, and T _b represents the time of the access line rewrite cycle. In this example,
Although T _a : T _b = 4: 3, the optimum value can be selected depending on the required refresh rate and the like. That is, the refresh rate can be increased by increasing the ratio of T _a , and the responsiveness of partial change can be improved by increasing the ratio of T _b .

To explain the states of the FIFO (A) 36 and the FIFO (B) 37, when the switch S1 is connected to the FIFO (A) 36 side (state A / B of the switch S1 = “1”), the CPU 11 The address of the line accessed by is sampled and stored in FIFO (A) 36. On the other hand, when the switch S1 is connected to the FIFO (B) 37 side (A / B = "0"), the line address accessed by the CPU 11 is stored in the FIFO (B) 37. Also, switch S2 is FIFO
When connected to the (A) 36 side (state of switch S2 A / B =
“1”), the address stored in FIFO (A) 36 is output,
When the switch S2 is connected to the FIFO (B) 37 side (A / B =
“0”), the address stored in the FIFO (B) 37 is output.

Once the entire screen has been refreshed,
When the FLCD 26 outputs the vertical synchronizing signal VSYNC or when a carry occurs in the address counter 38, the address counter 38 is cleared and the line output in the next full refresh cycle returns to the 0th line. As described above, the address counter 38 uses the horizontal sync signal from the sync control circuit 39.
The count is incremented to "1", "2", "3" according to the sync signal generated each time HSYNC is counted. This sync signal generated by the sync control circuit 39 causes the data bus driver 43 to operate. It is output according to the parameters M and N input to the synchronization control circuit 39 via. That is, the parameters M and N determine the ratio between the refresh cycle and the partial rewrite cycle in a certain period, and the synchronization signals are output for the number of lines of the refresh cycle determined by this parameter, and are not output during the partial rewrite. On the other hand, when the addresses of the lines L1, L2, L3 are accessed by the CPU 11, at this time, if the switch S1 is connected to the FIFO (A) 36, the addresses of L1, L2, L3 are stored here and then When switch S2 is connected to FIFO (A) 36
The addresses of L1, L2, L3 are output from here, and L1, L2, L3 are selected as output lines. Here, the switching signal of the switch S3 is given as RFF / ACS from the synchronous control circuit 39,
In the line access cycle in which RFF / ACS is “1”, the output line address is switched to the output from the FIFO (A), FIFO (B) side. When REF / ACS becomes "1", the switch S3 is switched to the address counter 38 side, and
The address counter 38 sequentially starts counting up in response to the synchronizing signal output from the synchronizing control circuit 39 in synchronization with the horizontal synchronizing signal HSYNC, and the refresh operation is performed from the line following the previous cycle. In FIG. 4, for example, after the line output of L3, “4”, “5”, which is a continuation of the previous cycle,
The lines "6" and "7" are output. In the same manner as above, the above operation is repeated, but the reason why two FIFOs are prepared is that the memory accessed address is sampled on the one hand and the sampled address is output on the other hand at the same time without any conflict and efficiently. This is because
That is, the address sampling period is from the output start of the access line of the other FIFO to the end of the refresh cycle. at the same time,
The address sampling period of the other FIFO will start.

As described above, in the basic operation, the refresh cycle and the line rewriting cycle are alternately repeated, and in FIG. 6, the repeating cycle is set to 7 lines as one unit.
Although it was explained that T _a : T _b = 4: 3, the environmental conditions such as temperature, the type of data to be displayed, the display change mode such as the cursor movement described above or the difference in the display device material of the FLCD, the access from the CPU, etc. The ratio between T _a and T _b can be changed according to the refresh rate or the like required according to the frequency (specifically, the value of the sampling counter) or the like.

(Second Embodiment) FIG. 7 is a block diagram showing a configuration of the access monitor circuit 50 shown in FIG. 3 according to a second embodiment of the present invention. The same elements as those shown in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 7, the address conversion circuit 502 is
The absolute address is converted into a main scanning address and a sub scanning address (that is, the above-mentioned line address) indicating the positions in the main scanning direction (X direction) and the sub scanning direction (Y direction) on the display screen. The main scanning address and the sub scanning address are input to the display mode determining circuit 510, and the display mode determining circuit 510 generates an interlace mode selection signal based on these addresses. The interlace mode selection signal is converted into the conversion table 53 shown in FIG.
And the conversion table 53 selects the optimum interlace table according to this signal.

FIG. 8 is a block diagram showing the details of the display mode determination circuit 510.

The X-direction min detection circuit 5101 detects the minimum value of the main scanning addresses that are continuously input, and also the X-direction Ma
The x detection circuit detects the maximum value. Then, the difference between them is calculated by the difference circuit 5105 to obtain the mode decision circuit.
Enter in 5109. Similarly for consecutive sub-scanning addresses, Y
The direction Min detection circuit 5103, the Y direction Max detection circuit 5104, and the difference circuit 5106 determine the difference between the maximum value and the minimum value of the sub-scanning address and input it to the mode determination circuit 5109.

The difference between the maximum value and the minimum value indicates the width of each consecutively input address.
Thereby, the displayed shape and its size can be detected. The mode determination circuit 5109 has a table for outputting an interlace mode selection signal according to this shape or the like, and outputs an interlace mode signal according to the shape or the like to be displayed. As a result, in the conversion table 53 (FIG. 2), the interlace mode table according to the shape or the like is selected. For example, the interlace mode in which the number of thinned lines is large can be selected as the shape is relatively large.

The minimum value of the sub-scanning address detected by the Y direction Min detection circuit is the latch 5107 and the difference circuit 51.
Enter in 08. The minimum value input to the latch 5107 is input to the difference circuit 5108 after a predetermined time. The difference circuit 5108 calculates the difference between these two minimum values, and this difference is also input to the mode determination circuit 5109. The difference output by the difference circuit 5108 is
It represents the minimum value of the sub-scanning address per predetermined time, which indicates the amount of movement (moving speed) of the displayed shape or the like.

As described above, the mode decision circuit 5109
Outputs an interlace mode selection signal according to the size of the displayed shape or the amount of movement of the shape, and the conversion table 53
In, an appropriate interlace table is selected according to this selection signal. For example, as described above, the interlace table having a larger number of thinning lines is selected as the size of the shape and the amount of movement increase.

(Third Embodiment) In the first and second embodiments described above, the configuration is such that the display drive signal is provided in the optimum interlace mode according to the amount of movement such as the selected icon and the size of the displayed shape. As described above, in this example, a configuration in which the operator can arbitrarily select the interlace mode will be described.

FIG. 9 is an explanatory diagram showing a display example of the FLCD 26 according to this example. The figure shows the menu screen,
When the operator moves the cursor 2 to the icon 8 called "interlace" and clicks it, a subwindow 9 for setting interlace is displayed. The operator can move the cursor 2 to this display unit and arbitrarily set the number of thinning lines from a relatively fine interlace to a relatively rough interlace.

FIG. 10 is an external perspective view of the FLCD 26 having another structure for the operator to arbitrarily set the interlace mode.

On the lower side of the device frame around the display screen 26d, an interlace mode setting knob 26i is provided side by side with the luminance volume knob 26v. By operating the knob 26i, the operator can select the thinning line number from the thinning line number in the interlace.

FIG. 11 is a block diagram showing the FLCD interface 27 according to the configuration for interlace setting described in FIG. In the figure, the same elements as those shown in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 11, the manipulated variable of the knob 26i is A / D converted by the A / D converter 26t, and the selection signal
It is input to the conversion table 53 as SEL. Then, the conversion table 53 selects the interlace table according to the selection signal SEL.

In the third embodiment described above, the selected interlace mode is different depending on the number of thinned lines, but the interlaced mode in which the number of thinned lines is converted at random or a block having a predetermined number of lines is used. Then, an interlace mode in which lines are sequentially driven and lines between blocks are thinned may be selected.

12 and 13 are explanatory views showing an example of the interlace table in the conversion table 53 of each of the above-mentioned embodiments. Each table shown in FIG. 12 stores address data of a line to be accessed on the display screen in accordance with each of addresses 0 to N generated by the address counter 38. For example, in the table corresponding to the 32 interlace mode, the address data of the first line at address 0, the 33rd at address 1, ... The second line at address k are stored. As a result, when this table is used for conversion, the lines of the address data to be stored are driven every 31 lines in this order from address 0 to address N.

For example, as described in the second embodiment, when the displayed shape is a figure such as "circle", the 8-interlace mode is selected.

The conversion table shown in FIG. 13 stores address data of lines to be accessed on the display screen in accordance with each of addresses 0 to k generated by the address counter 38. For example, in the table of 10 32 interlace modes on the leftmost side in the figure, address 0 is the first, address 1 is the second, ... address 9 is the 10th, address
321st to 10th, 322nd to 11th, ..., Address 19th
The address data of the 330th line is stored in. That is, first, the 1st to 10th lines from the top of the display screen are sequentially driven, then the lines of 10 lines x 31 (32 interlaces) are skipped, and the 321st to 330th lines are sequentially driven. .. After that, when the lines of the entire display screen are driven in the same manner, this is repeated.

In addition to the interlace tables shown in FIGS. 12 and 13, the conversion table 53 includes an interlace table in which the number of thinning lines randomly changes and a table in which the number of thinning lines is zero, that is, a non-interlaced (refresh drive) table. It is stored as an interlace table, and these tables are selected according to the icon, the display shape, and the operation input by the operator, as shown in each of the above embodiments.

[0072]

As is apparent from the above description, according to the present invention, the operator operates the knob or the like provided on the outer shape of the display device to set the interlace mode according to the operation amount. It becomes possible to select.

As a result, the display according to the operator's preference and work environment becomes possible, and the flexibility of the display device system can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing system incorporating a display control device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an FLCD interface according to the first exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing details of an access monitor circuit shown in FIG.

FIG. 4 is a front view of a display screen showing a display example of the FLCD according to the first embodiment.

FIG. 5 is a front view of a display screen showing a display example of the FLCD according to the first embodiment.

6 is a timing chart for explaining time division driving in the FLCD interface shown in FIG.

FIG. 7 is a block diagram showing details of an access monitor circuit according to a second embodiment of the present invention.

8 is a block diagram showing details of the display mode determination circuit shown in FIG. 7. FIG.

FIG. 9 is a front view of a display screen showing a display example according to a third embodiment of the present invention.

FIG. 10 is an external perspective view of an FLCD according to a third embodiment of the present invention.

11 is a block diagram of the FLCD interface of the embodiment shown in FIG.

FIG. 12 is an explanatory diagram showing an interlace table according to an embodiment of the present invention.

FIG. 13 is an explanatory diagram showing an interlace table according to the embodiment of the present invention.

[Explanation of symbols]

 1,8 Icon 2 Cursor 9 Sub window 11 CPU 12 Address bus 13 Main memory 14 DMA controller 15 LAN interface 16 LAN 17 I / O device 18 Hard disk device 19 Floppy disk device 20 Disk interface 21 Printer 22 Printer interface 23 Keyboard 24 Mouse 25 key Interface 26 FLCD (FLCD display) 26a Temperature sensor 26i Interlace setting knob 27 FLCD interface 31 Address bus driver 32 Control bus driver 33,43,44,45A, 45B Data bus driver 34 Sampling counter 35 Address selector 36 FIFO (A) memory 37 FIFO (B) memory 38 Address counter 39 Synchronous control circuit 40 Memory controller 41 Video memory 42 Driver receiver S1, S2, S3 switch 46 A, 46B register 47 Address conversion circuit 50 Access monitor circuit 51, 5 1A Rewrite area judgment circuit 51B Event detection circuit 53 Address conversion table 501 Comparison circuit 502 Address conversion circuit 503 Comparison circuit 504 FIFO control circuit 505 Latch comparison circuit 510 Display mode decision circuit 5101 X direction Min detection circuit 5102 X direction Max detection circuit 5103 Y Direction Min detection circuit 5104 Y direction Max detection circuit 5105, 5106, 5108 Difference circuit 5107 Latch 5109 Mode decision circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenzo Ina 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (2)

[Claims] 1. A display control device of a display device, comprising a display element capable of holding an updated display state, and performing display by driving the display element based on display data specified by an address, Interlace data supply means for supplying interlace data, which is data for interlace driving for thinning and driving scanning lines made up of elements, and which is different depending on the number of thinning lines, and a plurality of interlace data An interlace data supply control means for supplying the interlace data selected via the selecting means to the operator of the display device to select arbitrary interlace data supplied from the inside. A display control device characterized by the above. 2. The display control device according to claim 1, wherein the display element has a ferroelectric liquid crystal as an operation medium for updating the display state.