JPH0564922A - Processing system for smoothing image - Google Patents

Abstract

PURPOSE:To enable a pixel data to be easily processed for smoothing by a simple judge operation without making a circuit complicated by a method wherein in a thermal printer or the like having a line array like recording head which outputs an image by dividing one pixel into unit elements in a sub scan direction, the unit element is shifted in the sub scan direction or is increased and decreased in its number. CONSTITUTION:When an image is outputted by dividing one pixel into five unit elements P1-P5, a corresponding 100% diameter pixel data is formed by applying a pixel signal to three unit elements among five unit elements. Thereby, the pixel signal is applied to central three unit elements excepting the upper end one and the lower end one to compose a corresponding pixel data (b2) for an ordinary state. Besides, when a data is processed for smoothing, by increasing or decreasing the unit element to which the pixel signal is to be applied by one unit element before and behind in the sub scan direction according to adjacent pixel information, printing positions for the three stages (b2), (b2), (b3) can be set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image smoothing processing method in a linear dot printer in which pixel forming elements are arranged substantially along the main scanning direction, such as an LED printer or a thermal printer, and more particularly to a dot shape. The present invention relates to an image smoothing processing method capable of smoothing an oblique line or a curved portion included in a formed pixel pattern to obtain a high quality image.

[0002]

2. Description of the Related Art Conventionally, as in an LED printer or a thermal printer, an array of pixel forming means arranged in one line in the main scanning direction is driven (lit) simultaneously on one line or in block units based on video data. A dot printer is also known in which a matrix-shaped pixel pattern is formed on a recording material such as a photosensitive drum that moves relatively in the sub-scanning direction while being controlled.

Since all printers of this type adopt a method of arranging pixel patterns in a matrix of n × m to form an arbitrary character or figure, when forming a curve or a diagonal line like V or ◯. The print boundary portion is formed in a stepped shape, and a plurality of pixels are arranged close to each other at an intersecting portion such as X, so that the portion becomes thick and inevitably the print quality deteriorates. ..

In order to solve such a drawback, for example, in a laser printer which forms a pixel pattern while optically scanning a modulated beam in the main scanning direction, the beam corresponding to the target pixel is delayed to perform the main scanning at the pixel forming position. By changing the pixel diameter by shifting in the direction or by changing the beam output, it has been attempted to eliminate the stepped portion and the thickness at the print boundary portion. In the LED printer, the arrangement interval of the pixel forming elements is fixed in the main scanning direction,
Moreover, in LED printers, LEs arranged in a line
Since the D element can be driven and controlled only in units of n bits or in units of one scanning line, it is difficult to use the smoothing processing means used in the laser printer as described above.

For this reason, in a device such as an LED printer that outputs image information in units of one scanning line, each pixel is shifted by a certain amount in the main scanning direction for each different scanning line, and each pixel is diagonally arranged in the sub-scanning direction. A smoothing processing method has been proposed in which the coordinate conversion of pixels is performed so as to output the pixel. (Japanese Patent Publication No. Sho 62-24987, etc.)

However, in the above-mentioned prior art, since the coordinate movement is performed in units of lines, it is difficult to achieve smoothing processing in units of characters, and in the above-mentioned technique, the shift is performed only in the main scanning direction. However, in the case of a step portion having a steep inclination, it is difficult to achieve smooth smoothing processing even if the logical sum is calculated.

In order to eliminate such a drawback, the target pixel itself is replaced with a narrowed (flattened) pixel, and the flattening of the target pixel is performed not only in the main scanning (horizontal) direction but also in the sub-scanning direction. In the scanning (vertical) direction, in other words, there has been proposed a technical means (Japanese Patent Laid-Open No. 2-112966) configured to perform in the biaxial directions of right, left, up, and down.

[0008]

According to the present technology, the replacement of a flat pixel is performed by four compensation subcells that narrow the pixel in the main scanning direction and four compensation subcells that narrow the pixel in the subscanning direction. The pixel is prepared, and the pixel of interest is replaced by appropriately selecting these while comparing them with the reference pixel pattern. For example, in the case of an LED printer, the flatness in the vertical direction is controlled by controlling the lighting time of the LED array. However, on the contrary, the arrangement interval of each LED element is fixed, and in such a case, flattening in the horizontal direction is difficult unless the light intensity of each LED element is adjusted. Further, since the element is generally made into a chip in units of a plurality of bits, it is substantially difficult to adjust the strength of the element.

As prior art, in US Pat. No. 4,437,122, one pixel is 3 × in the main scanning direction and the sub scanning direction.
There is also a technique of performing a smoothing process by dividing the unit element into a matrix of 3 and comparing it with a reference pixel pattern in the unit unit. However, in the case of such a technique, the unit division in the horizontal direction is impossible in the case of an LED printer. Therefore, the application is difficult, and the number of reference pixel patterns necessary for collectively converting into a total of 9 unit elements of 3 × 3 in the biaxial direction is unnecessarily large. As a result, the circuit configuration is unavoidably increased in size, and the comparison operation is delayed, which makes it impossible to cope with the speedup.

In view of the above-mentioned drawbacks of the prior art, the present invention is a linear dot printer such as a thermal printer or an LED printer, which does not complicate the circuit configuration and can be easily and accurately performed by a simple determination operation. An object is to provide an image smoothing processing method capable of performing smoothing processing. Another object of the present invention is to provide an image smoothing processing method in a line printer capable of improving the quality of the dots themselves together with the image smoothing and obtaining a high quality image that can sufficiently endure the expansion of the data after the smoothing processing. The purpose is to do.

[0011]

Conventionally, in an LED printer or the like in order to improve image quality, one pixel forming a dot image is divided into P unit elements in the sub-scanning direction, and the divided unit elements are divided. An image output method for outputting a pixel pattern in units of n bits obtained by dividing one scanning line or m dividing one scanning line while repeatedly applying the same pixel signal to each other (Japanese Patent Publication No. 62-26626, Japanese Patent Publication No. 60-134660, etc.)
Is proposed. The present invention effectively utilizes such a pixel division method.

That is, according to the first aspect of the invention, before the smoothing process or when the smoothing process is not performed, as shown in FIG. 1, three or more, preferably five or more of the divided unit elements are prepared, Without applying a pixel signal to all of the divided unit elements, the unit element group N (N <N
P) is configured to output a pixel pattern in units of one scanning line or n bits while repeatedly applying a pixel signal, and at the time of smoothing processing, the pixel signal is applied only to the unit element forming one pixel. Instead of applying, a reference pixel to be subjected to the smoothing process is selected corresponding to adjacent pixel information, and a pixel signal is applied to the selected reference pixel or a plurality of unit pixels It is characterized in that it outputs.

In this case, as shown in FIG. 1, the black pixel to which the pixel signal is applied may be increased or decreased in the sub-scanning direction within the range of the reference pixel, or as shown in FIG. To
The black unit element may be reduced or added to the range of another pixel adjacent to the range of the reference pixel.

The present invention is characterized in that empty unit cells for smoothing processing are arranged on both upper and lower sides of the unit pixel group N of pixels to be actually applied. The actual pixels that are not processed become small, and it is difficult to form a so-called solid black surface image.

The invention according to claim 4 is effectively applied to an image output system in which the divided unit element group P and the basic unit element group N to be actually applied coincide with each other, and more preferably, a smooth circuit configuration is employed. It is an object of the present invention to provide an image output method capable of performing smoothing processing on the image output method that employs the above-described unit element division method. As shown, a boundary pixel that switches from a white pixel to a black pixel or from the black pixel to a white pixel along one scanning direction, and a boundary pixel that is located on the preceding or next scanning line adjacent to the boundary black pixel 1 Alternatively, while performing a logical product and a logical sum with a plurality of reference pixels, a black unit element is appropriately added or reduced to the boundary pixel, the reference pixel or a pixel area adjacent to these pixels to perform smoothing processing. ..

In this case, the boundary pixel is not necessarily limited to a black pixel, and may include a white pixel. Further, the present invention is effectively applied to an image output method in which the unit element group P and the basic unit element group N to be actually applied match, but the invention is not limited to this, and the output method of P> N according to claim 1. Of course, it is also applicable.

[0017]

Next, the details of the invention of each of the claims will be described step by step. A. The invention according to claim 1 In order to explain the present invention with reference to FIG. 1, when a printer which divides one pixel into five unit elements in the sub-scanning direction and outputs an image is used, FIG. As shown, the pixel data (100% diameter) can be formed by applying a pixel signal to three of the five unit elements. Pixel signals are applied to the three unit pixels in the center except for forming the corresponding pixel data b2. On the other hand, when the data is smoothed, the pixel signals are applied corresponding to adjacent pixel information. It is possible to set the printing position in three stages by increasing or decreasing the power unit element by one unit in the front and rear direction in the sub-scanning direction. (B
1, b3)

Further, the unit elements P4 and P5 to which the pixel signals are to be applied
By increasing or decreasing, 33% (b5), 67% (b4), 10
The pixel size can be changed to 0% (b2). Therefore, according to the present invention, by combining both of the above controls, the pixel at the intersection such as X can be set to 67% (2 unit pixels) to avoid thickening, and the pixel signal should be applied. By gradually increasing or decreasing the unit element, it becomes possible to form a curved line or an inclined line in which the step is not noticeable.

The control is made finer by increasing the difference between the unit prime group P and the unit prime number N to which the pixel signal should be applied. With such a configuration, the density of adjacent pixels is increased. The spacing becomes sparse, which makes it difficult to achieve smoothing. Therefore, in the invention described in claim 2), in order to enable more precise control while maintaining an appropriate pixel density, the unit element to which the pixel signal is applied as shown in FIG. 2A. Is not increased or decreased in the same pixel, but the increase / decrease area is set to be able to increase / decrease the unit element to a position including a part of the division unit element of another adjacent pixel located in the sub-scanning direction. is there. (B6-b12)

Thus, in the case of the above embodiment, it is possible to increase / decrease the division unit element at the upper end or the lower end of another pixel adjacent to each other so that at least 7 steps of step control can be performed, and FIG. As shown, the division unit element is included to increase or decrease 33% (b13, b14), 6
7% (b15, b16), 100% (b17, b1
8), 133% (b19, b20), 167% (b2
1, b22) and 5 kinds of pixel sizes, 35 kinds of step control are possible. (b13 to b22)

A, the invention according to claim 4 For example, in the case of an image output system constituted so that a corresponding black pixel can be formed by applying a pixel signal to all unit elements divided into four unit elements, The smoothing process is performed as described above. First, FIG. 6 shows an embodiment in which a black unit element is added. The unit element (first and second) to be loaded for smoothing is determined from the image of (a) before the smoothing process by first determining the scanning line. , A boundary pixel (A) that switches from a white pixel (0) to a black pixel (1) is extracted, and the reference pixel (E, F) adjacent to the boundary pixel (A) on its preceding or next scanning line is extracted. ) And AND to determine * 1 and * 2. * 1 'is * 1
The bit shift (delay) is set automatically when is added.

Next, the unit pixels (* 3, * 4) are determined by first extracting the boundary black pixel (F) that switches from the black pixel (1) to the white pixel (0), and then determining the boundary black pixel (F). And the reference pixel (A, G) adjacent to the preceding or next scanning line are ANDed to determine * 3 and * 4. Note that * 4 'is automatically set by a delay when * 4 is added as in the above. * 1: A (0 → 1) ΛEΛF * 2: A (0 → 1) ΛEΛF * 3: F (1 → 0) ΛAΛG * 4: F (1 → 0) ΛAΛG

FIG. 7 shows an embodiment in which a black unit pixel is added / deleted. First, a boundary pixel (A, which switches from a white pixel (0) to a black pixel (1) in the image data (a) before the smoothing process is changed.
A ') is extracted, and the boundary pixel (A, A') is ANDed with the reference pixel (B) adjacent to the preceding or next scanning line to determine the unit element * 1 to be added. , The boundary black pixel (B, which switches from the black pixel (1) to the white pixel (0),
B ′) is extracted, and the reference black pixel (A, B ′) adjacent to the boundary black pixel (B, B ′) on the preceding or next scanning line (A,
A ') is the same as the above until the logical product is taken to determine * 2, but in the case of deletion, the boundary black pixel (B, B') is extracted and the boundary black pixel (B, B ') is extracted. And a unit pixel to be deleted by logically ANDing the same scan line and the reference pixels (A, A′D) adjacent to the previous or next scan line.
Determine 3. * 1: A, A '(0 → 1) ΛB * 2: B, B' (1 → 0) ΛA (A ') * 3: B, B' (1 → 0) ΛD (A) ΛA (A ' )

FIG. 8 shows another embodiment in which the lower two unit element lines (iii, iv) of the scan line are related to the upper two unit element lines (i, ii) of the next scan line. A procedure for setting the additional unit primes (a to g) will be described. First, a boundary pixel (A) that switches from a white pixel (0) to a black pixel (1) in the I scan line is extracted, and the boundary pixel (A) and II are extracted.
The logical product of the adjacent reference pixels (E, F) on the scan line is set, and b is set by preceding by 1 bit in the iii unit pixel line, and then the black pixel (1) to the white pixel (in the I scan line). The boundary black pixel (C) which is switched to 0) is extracted, and the reference pixel (G, H) adjacent to the boundary black pixel C on the II scanning line is extracted.
Then, the iii unit element line is delayed by 1 bit to set b2, and then the iv unit element line is advanced or delayed by 2 bits respectively, a1, a2 and g1, g.
Set 2.

Similarly, the II scan line also has boundary pixels (F, G).
Is extracted, and the boundary pixel (F, G) and the reference pixel (A, B or B, C) adjacent to each other on the I scan line are ANDed, and 1 bit precedes in the unit pixel line ii as described above. (Delay) to set d and f, and in the case of i unit prime lines, each bit is advanced (delayed) to set c / e. To obtain black pixels. Therefore, even in such a system, the smoothing process can be easily performed by taking the logical sum of the boundary pixels (F, G) and the reference pixels (A, B, C).

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described in detail below as an example with reference to the drawings. However, unless otherwise specified, the dimensions, materials, shapes, relative positions, etc. of the components described in this embodiment are not intended to limit the scope of the present invention thereto, but are merely illustrative examples. Not too much. Figure 4
Is a time division type LED head circuit which takes in pixel-divided unit elements to which the present invention is applied and sequentially drives and controls LED elements in n-bit units. 1 is an n-bit L
An LED array 10 in which a plurality of LED chips 1A ... Incorporating ED elements 1a are arranged in rows is a drive IC of the LED array, and has a memory capacity corresponding to the number n of LED elements for each chip. The chip register 1A includes a shift register 11, a latch circuit 12, and a switch circuit 13 including switch elements 13a, the number of which corresponds to the number n of LED elements.
The element 1a and the switch element 13a are connected.

Reference numeral 4 designates the switch circuit 13 and L for each transfer control of the unit element to the shift register 11 side by n bits.
It is a block designating circuit for selectively selectively switching the connection with the ED chips 1A.

To briefly explain the operation of the head circuit, first, the first n-bit unit element is serially fetched and stored in the shift register 11 from the control circuit 53 (see FIG. 3) based on the clock. After that, the control circuit 5
Each of the LED elements 1a of the corresponding LED chip 1A by causing the latch circuit 12 to latch the n-bit unit element in parallel on the basis of the latch signal and transferring the output signal based on the latch data to the switch circuit 13 side.
Drive control.

After the data is transferred to the latch circuit 12 in the shift register 11, the next n-bit unit element is continuously stored serially, and after the n-bit data is stored, the latch circuit 12 is based on the latch signal. The control circuit 5 sends a switching signal to the block designating circuit 4, while switching the connection of the switch circuit 13 to the next LED chip 1B ..., Driving each LED element 1a of the LED chip 1B. The same operation is continuously performed m times, and the unit element data for one scanning line is output.

Thereafter, the LED chips 1A to 1N are processed in the same manner.
By performing the drive control of m times (N × m times) × 5 times, the pixel data of one scanning line as a unit element group divided into five or four as shown in FIG. 5 is developed.

FIG. 3 shows an embodiment according to claims 1 to 3,
In FIG. 3, in the control circuit provided on the video output side,
After the image information corresponding to a plurality of main scanning lines is fetched and subjected to smoothing processing, the processed divided pixel data can be serially transmitted to an LED head circuit provided in the print engine. ..

To briefly explain the configuration, 51 is a pattern memory, for example, a pixel signal for one scanning line developed in a video memory (not shown) is serially stored in the memory 51 based on a reference clock signal. A pixel signal line corresponding to one or a plurality of scanning lines before and after the pixel signal line to be output is always stored in the memory 51 while being input. Denoted at 52 is a decoder which also serves as a logic circuit. As shown in the enlarged portion of FIG. 3B, image information adjacent to the pixel of interest in the pattern memory 51, more specifically, R dots in the main scanning direction and sub scanning direction Taking into account the image information in the matrix Rχ1 for the χ dots, the divided pixels corresponding to the respective unit elements P1 to P5 based on the selector signal SL indicating the divided unit elements P1 to P5 corresponding to the information taken in by the control circuit 53. A signal is generated based on a predetermined logic circuit.

The divided pixel signal generated by the decoder 52 is transferred to the shift register on the print engine side via the control circuit 53 based on the reference clock CLK. On the other hand, every time the 1 division signal is transferred to the shift register, the pixel information (Rχ) to be referred to in the pattern memory 51 based on the reference clock CLK.
n) is shifted bit by bit in the main scanning direction to sequentially generate the target pixel * 2 * 3, and, for example, a divided pixel signal for one scanning line corresponding to the divided unit element P1 is shifted through the control circuit 53 through the shift register. 11, the select signal SL is switched after the transfer, the divided pixel signal corresponding to the unit pixel P2 is transferred based on the logic circuit incorporated in the decoder 52, and the above operation is repeated.

That is, more specifically, of the five unit element groups divided in the sub-scanning direction, three excluding the unit elements P1 and P5 at the upper and lower ends based on a selector signal SL from a control circuit (not shown). While the image data is generated while repeatedly applying the pixel signal to the unit pixel groups P2 to P4, the target pixel to be smoothed corresponding to the pixel information of another adjacent scanning line. As for the unit element groups P1 to P5 to be applied based on the logic circuit built in the decoder 52, the unit elements to be applied in the sub-scanning direction are increased or decreased as described in detail in the section of the operation of the invention. While developing the divided pixel pattern.

Reference numeral 53 denotes the unit pixel data output from the decoder 52, based on a reference clock, the shift register 1 of the LED head circuit on the print engine side.
1 is a control circuit that serially transmits to 1. Then, the unit elements serially transferred from the control circuit 53 are taken in, and the LED head circuit 1 side sequentially controls the driving of the LED elements in units of n bits. According to such a circuit, the smoothing processing based on the above-mentioned subtended invention can be smoothly performed.

9 and 10 show a smoothing processing circuit showing an embodiment of the invention described in claim 4. FIG. 9 is a block diagram showing an overall configuration diagram of the smoothing processing circuit of the present invention. For example, video data (hereinafter, VDATA) rasterized in an image RAM or the like (not shown) is converted into VCLK generated by the VCLK generation circuit 101. The data is transferred to the shift register 104 serially in synchronization with the shift register 10
After converting to N + 1 bit parallel data in step 4, SRA
Store in the first bank, first address of M105. Subsequent N + 1-bit converted parallel data is stored in the second address, and this operation is repeated thereafter for one line of VDAT.
Store A in the first bank of SRAM 105.

Similarly, VDATA of the second line is sequentially stored in the second bank, and VDATA of the third line is sequentially stored in the third bank. And VDATASR for N lines
When AMIOS's are stored in banks 1 to N, SRAM
The control circuit 103 uses the time until VDATA for storing at the first address of the N + 1th bank is available,
VD stored at each first address of the first to Nth banks
ATA is sequentially read based on the latch signal, stored in the latch-and-shift registers 106 to 112 respectively, and at the same time the converted parallel data is stored in the Nth bank and the first address based on the signal from the SRAM control circuit 103. , Latch and shift register 1
The data stored in 06 to 112 is loaded into the N line shift register 113.

By repeating the above operation in the same manner, the VDATA of the (N + 1) th line is transferred to the (N + 1) th of the SRAM 105.
The VDATA of the first to N-th lines stored in the SRAM 105 while being stored in the bank are continuously supplied to the N-line shift register 113 via the latch-and-shift registers 106 to 112. Then, the SRAM 105
On the side, when the VDATA of the Nth line has been stored in the Nth bank, the VDATA of the 9th line is stored in the first bank and further in the 10th bank based on the control signal from the SRAM control circuit 103.
By storing VDATA of the line in the second bank, the contents of the first to Nth banks are sequentially updated.

As a result, the N line shift register 1
In 13 is stored a bit map (N × 7) of 1 or more lines before and after the reference pixel (center bit) and 3-bit left and right while the contents are sequentially updated by data transfer from the SRAM 105. The smoothing processing can be performed in the smoothing processing circuit 120 described later by using the bitmap.

The smoothing processing circuit 120 includes an AND logic 123 including selectors 121A and 121B for selecting the reference pixels and AND circuits 122A and 122B, a line counter 124 for selecting a unit element line of each pixel,
Addition (deletion) obtained by the logical sum or logical product
When one bit is vacant between the unit element and the boundary pixel, the delay circuit 125A, 12 that fills (deletes) the bit
5B, a line counter 124 for selecting which unit element line and an OR for serially transmitting the divided pixel video data after the smoothing processing while taking the logical sum of the additional unit element and the logical product of the deletion unit element It is composed of a gate 127 and an AND gate 128.

Next, the operation of the smoothing processing circuit 120 will be described with reference to FIG.
First, the boundary pixel (A) that switches from the white pixel (0) to the black pixel (1) in the corresponding scan line M of the N line scan register is extracted, and then the counter from the line counter 124 is used. The N based on the signals (i to iv)
Previous position P-1 to next position P + in the line shift register 113
Of the pixels (B to M) positioned on one scan line, the selector 12 selects one or more reference pixels adjacent to the boundary pixel A.
1A and 121B, that is, when the counter signals are i and ii, the pixels (B to B) located on the scan line of the preceding P-1 are selected.
G), or when the counter signals are iii and iv, the reference pixel is selected from the pixels (HM) located on the scan line of the next order P + 1.

The reference pixel and the boundary pixel are ANDed.
The circuits 122A and 122B take a logical product to generate a necessary addition (deletion) unit elementary signal, and if necessary, the delay circuits 125A and 125B obtain the addition (deletion) unit obtained from the AND circuits 122A and 122B. As described above, one bit is further added between the elementary signal and the reference pixel to generate a continuous addition (deletion) unit elementary signal of two bits. The addition (deletion) unit element signal for smoothing obtained as described above is the OR circuit 129A,
The video data output from the N-line shift register 113 via the 129B and the OA gate 127 take the logical sum (in the case of addition) or the AND gate 128 take the logical product (delete) to divide the LEDs in unit element line units.
Serial transmission to the head circuit side.

According to this embodiment, the above-described operation of the present invention can be smoothly achieved. In the present invention, the selectors 121A, 121B and AND are used to perform different smoothing processing operations when adding and deleting the smoothing unit element.
Circuits 122A and 122B, delay circuits 125A and 12
5B, OR circuits 129A and 129B are provided in pairs.

[0044]

As described above, according to the present invention, there is provided a thermal printer or an LED printer having a line array recording head which outputs an image by dividing one pixel into a plurality of unit pixels in the sub-scanning direction. In the first aspect of the invention, the unit element is shifted or increased or decreased in the sub-scanning direction, and in the fourth aspect of the invention, the boundary pixel and the reference pixel are logically ANDed to complicate the circuit configuration. It is possible to perform smoothing processing easily and accurately with a simple determination operation without performing the above. And so on.

[Brief description of drawings]

1A and 1B are basic configuration diagrams showing a printing arrangement state for smoothing processing of the present invention.

2A and 2B show a print array state for smoothing processing in which a unit pixel for smoothing is shifted to an adjacent pixel area.

FIG. 3 is a block diagram of a smoothing processing circuit according to an embodiment of the invention described in claim 1.

FIG. 4 is a LE adopting a time division method to which the present invention is applied.
D printer LED head circuit diagram

5 shows a dot pattern output by the LED head circuit of FIG.

FIG. 6 shows an operation procedure for performing the smoothing operation of the invention according to claim 4, and particularly this figure shows a procedure for performing the smoothing processing only by adding a unit element.

FIG. 7 shows an operation procedure for performing the smoothing processing operation of the invention according to claim 4, and particularly this figure shows a procedure for performing the smoothing processing by adding / deleting a unit element.

FIG. 8 shows an operation procedure for performing the smoothing operation of the invention according to claim 4, and particularly this drawing shows a procedure for performing the smoothing processing by paying attention to adjacent unit element lines.

FIG. 9 is an overall block diagram of a smoothing processing controller according to an embodiment of the present invention.

10 is a block diagram of a main part of a smoothing processing circuit portion in FIG.

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location // G09G 5/36 8121-5G

Claims (4)

[Claims] 1. A plurality of unit pixels (P ≧ 1
3), and an image output method in which a pixel pattern is output in units of one scanning line or n bits while applying a corresponding pixel signal to the divided unit element, one or more of the divided unit element P. While forming a pixel pattern while applying a corresponding pixel signal to the unit pixel of, the reference pixel to be subjected to the smoothing process is selected in correspondence with the adjacent pixel information, and the selected reference pixel is selected. Image output method characterized in that a pixel signal is applied to the unit pixel of 2. The image output system according to claim 1, wherein the unit pixel to which the pixel signal is applied is increased or decreased within a range of one pixel. 3. The image output system according to claim 1, wherein the unit element for applying the pixel signal is added to the unit element of another pixel adjacent to and exceeding one pixel. 4. A pixel dot is divided into a plurality of unit element groups in the sub-scanning direction, and a pixel pattern is formed in units of one scanning line or n bits while applying corresponding pixel signals to the divided unit element groups. In the image output method for outputting, a pixel along which a pixel signal is not applied (hereinafter referred to as a white pixel) along one scanning direction is switched to a pixel to which a pixel signal is applied (hereinafter referred to as a black pixel), or the black pixel is switched to a white pixel. The boundary pixel and the reference pixel or these pixels are adjacent to each other while taking a logical product and a logical sum of the boundary pixel and one or more reference pixels located on the preceding or next scanning line adjacent to the boundary pixel. Image output method characterized by performing smoothing processing by appropriately adding or reducing black unit pixels to the pixel area