JP2812344B2 - Image smoothing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for smoothing an image in a line-shaped dot plink in which pixel forming elements are arranged substantially in the main scanning direction, such as an LED plink or a thermal plink, and more particularly to a dot-like method. The present invention relates to an image smoothing method capable of obtaining a high-quality image by smoothing oblique lines or curved portions included in a formed pixel pattern.

[0002]

2. Description of the Related Art Conventionally, like an LED printer or a thermal printer, an array of pixel forming means arranged in one line in the main scanning direction is driven (lighted) on a line basis or in block units based on video data. A dot printer that forms a matrix pixel pattern on a recording material such as a photosensitive drum that relatively moves in the sub-scanning direction while being controlled is also known.

[0003] In order to adopt a method of forming an arbitrary character or figure by arranging pixel patterns in an n x m matrix, any printer of this type forms a curve or diagonal line such as V or 〇. However, the printing boundary portion is formed in a step shape, and in a portion intersecting like X, since a plurality of pixels are arranged close to each other, the portion becomes thick, and the printing quality inevitably deteriorates. .

In order to eliminate such a drawback, for example, in a laser printer which forms a pixel pattern while optically scanning a modulated beam in the main scanning direction, a beam corresponding to a target pixel is delayed so that the pixel forming position is scanned in the main scanning direction. By shifting the pixel direction by changing the pixel diameter by changing the direction of the beam or by changing the beam output, a thermal printer in which pixel forming elements are arranged in a line shape, In the LED printer, the arrangement interval of the pixel forming elements is fixed in the main scanning direction,
In LED printers, LEs are arranged in a line.
Since the driving of the D element can be controlled only in units of n bits or in units of one scanning line, it is difficult to employ a smoothing processing means used in a laser printer as described above.

For this reason, in an apparatus such as an LED printer that outputs image information in units of one scanning line, each pixel is shifted by a fixed amount in the main scanning direction for each different scanning line, and each pixel is obliquely arranged in the sub-scanning direction. There has been proposed a smoothing processing method configured to perform pixel coordinate conversion so as to output as follows. (Japanese Patent Publication No. 62-24987, etc.)

However, in the prior art, since the coordinate movement is performed in units of lines, it is not only difficult to perform smoothing processing in units of characters, but also because the technique is a shift only in the main scanning direction. In the case of a step portion having a steep inclination, it is extremely difficult to achieve smooth smoothing even if a logical sum is obtained.

In order to solve this drawback, the target pixel itself is replaced with a narrowed (flattened) pixel, and the flattening of the target pixel is performed not only in the main scanning (horizontal) direction but also in the sub-scanning direction. In the scanning (vertical) direction, in other words, there is proposed a technical means (Japanese Patent Laid-Open No. 2-112966) in which the scanning is performed in the biaxial directions of right, left, up and down.

[0008]

According to the present technology, replacement of flat pixels is performed by four compensation subcells for narrowing pixels in the main scanning direction and four compensation subcells for narrowing pixels in the subscanning direction. It is prepared and replaced appropriately by comparing these with the reference pixel pattern to replace the pixel of interest. For example, in the case of an LED printer, the vertical direction is controlled by controlling the lighting time of the LED array. Although the arrangement is possible, the arrangement interval of each LED element is fixed, and in such a case, it is difficult to flatten in the horizontal direction unless the light intensity of each LED element is adjusted. In addition, since the element is generally formed into a chip in units of a plurality of bits, it is substantially difficult to adjust the intensity of the element.

In US Pat. No. 4,437,122 as a prior art, one pixel is divided by 3 × in a main scanning direction and a sub-scanning direction.
There is also a technique of dividing the matrix into unit elements in the form of a matrix and performing a smoothing process while comparing the pixel elements with a reference pixel pattern. However, such a technique cannot perform horizontal unit division in the case of an LED printer. Therefore, it is difficult to apply the method. In addition, the number of reference pixel patterns necessary for converting into a total of nine unit elements of 3 × 3 collectively in two axial directions becomes uselessly large. As a result, the circuit configuration must be increased in scale, the comparison operation is delayed, and it is not possible to cope with high-speed operation.

In view of the drawbacks of the prior art, the present invention makes it easy and accurate with a simple determination operation without complicating the circuit configuration in a line-shaped dot blink such as a thermal blink or an LED blink. An object of the present invention is to provide an image smoothing method capable of performing a smoothing process. Another object of the present invention is to provide an image smoothing method in a line printer capable of improving the quality of the dots themselves together with the image smoothing and obtaining a high quality image that can sufficiently withstand the enlargement of the data after the smoothing processing. The purpose is to do.

[0011]

Conventionally, in order to achieve high image quality, in an LED printer or the like, one pixel forming a dot image is divided into P unit elements in the sub-scanning direction, and the divided unit elements are divided. An image output method in which a pixel pattern is output in units of n bits obtained by dividing one scan line or m into one scan line while repeatedly applying the same pixel signal (Japanese Patent Publication No. 62-26626, Japanese Patent Application Laid-Open No. 60-134660, etc.).
Has been proposed. The present invention effectively utilizes such a pixel division method.

That is, according to the first aspect of the present invention, before the smoothing process or at the time when the smoothing process is not performed, as shown in FIG. 1, three or more, preferably five or more, the divided unit elements are prepared, Without applying a pixel signal to all of the divided unit elements, a unit element group N (N <N <
P), a pixel pattern is output in units of one scanning line or n bits while repeatedly applying a pixel signal. At the time of smoothing processing, the pixel signal is output only to a unit element constituting one pixel. Instead of applying a pixel signal, a reference pixel to be subjected to the smoothing process is selected in accordance with adjacent pixel information, and a pixel signal is applied to one or a plurality of unit elements of the selected reference pixel to thereby apply a pixel signal to the pixel pattern. Output is performed.

In this case, as shown in FIG. 1, the black unit element to which the pixel signal is applied may be moved or increased or decreased in the sub-scanning direction within the range of the reference pixel. As shown, the black unit element may be reduced or added to the range of another pixel adjacent beyond the range of the reference pixel.

The above invention is characterized in that empty unit elements for smoothing processing are arranged on the upper and lower sides of a unit element group N of pixels to be actually applied. Actual pixels that are not subjected to the processing become small, so that it is difficult to form a so-called solid black surface image.

[0015] In according the invention in claim 4, wherein it is effectively applied to an image output method before Symbol divider the unit pixel group P and actually applied to be a basic unit pixel group N are matched, and more preferably a simple circuit configuration Image smoothing that can perform smoothing processing smoothly
The purpose of the present invention is to provide a processing method , which is characterized by an image smoothing method adopting the unit element division method described above.
In processing method, as shown in FIGS. 6 to 8, wherein the component
While applying image signals corresponding to all the divided unit elements,
A pixel pattern is formed along with a pixel signal to which a pixel signal is applied (hereinafter, referred to as a black pixel) from a pixel to which a pixel signal is not applied (hereinafter, referred to as a white pixel) along one scanning direction, or a A boundary pixel to be switched to a white pixel, one or more reference pixels located on a preceding or next scanning line adjacent to the boundary pixel, and a logical sum
On the scan line of the boundary pixel , and
One or more pixels located on the sub-scanning line of the reference pixel
Add the black unit element of the dot as appropriate or add and
The point is that the smoothing process is performed by reducing the unit element of the boundary pixel .

In this case, the boundary pixels are not necessarily limited to black pixels but include white pixels. The present invention is not but is effectively applied to an image output method of a unit pixel group P and actually applied to be a basic unit pixel group N coincides limited only thereto, the output method according to claim 1, wherein P> N Of course, it is also applicable.

[0017]

Next, the details of the present invention will be described in order. A: The invention according to claim 1 The present invention will be described with reference to FIG. 1. When a pixel is divided into five unit elements in the sub-scanning direction and an image output is used, FIG. As shown, by applying a pixel signal to three of the five unit elements, corresponding pixel data (100% diameter) can be formed. A pixel signal is applied to the central three unit elements except for the pixel data b2 to form corresponding pixel data b2. On the other hand, when the data is subjected to smoothing processing, a pixel signal is applied in accordance with adjacent pixel information. By moving the power unit element back and forth by one unit element in the sub-scanning direction, it is possible to set the printing position in three stages. (B
1, b3)

Further, unit elements P4 and P5 to which a pixel signal is to be applied.
Is increased or decreased, 33% (b5), 67% (b4), 10%
The pixel size can be changed to 0% (b2). Therefore, according to the present invention, by combining the above two controls, the pixel at the intersection such as X is set to 67% (two unit pixels) so that the thickness can be avoided, and the pixel signal should be applied. By gradually increasing or decreasing the unit element, it is possible to form a curved or inclined line in which the step is not conspicuous.

By increasing the difference between the unit prime group P and the unit prime number N to which a pixel signal is to be applied, the control can be made finer. With such a configuration, the density of adjacent pixels can be reduced. The intervals are sparse, which makes it more difficult to achieve smoothing. Therefore, in the invention described in claim 2, in order to enable more precise control while maintaining an appropriate pixel density, a unit element to which the pixel signal should be applied as shown in FIG. Instead of increasing / decreasing within the same pixel, the increase / decrease area is set so that the unit element can be increased / decreased to a position including a part of the divided unit element of another adjacent pixel located before and after in the sub-scanning direction. is there. (B6 to b12)

Thus, in the case of the above-described embodiment, at least seven levels of step control can be performed by setting the division unit element at the upper end or lower end of another adjacent pixel so that it can be increased or decreased. As shown in the figure, 33% (b13, b14), 6
7% (b15, b16), 100% (b17, b1)
8), 133% (b19, b20), 167% (b2
1, b22) and five types of pixel sizes, enabling 35 types of step control. (b13-b22)

A. The invention according to claim 4 For example, in the case of an image output system configured so that a corresponding black pixel can be formed by applying a pixel signal to all unit elements divided into four unit elements, The smoothing process is performed as described above. First, FIG. 6 shows an embodiment in which a black unit element is added. The unit elements (first and second) to be added for smoothing are first determined from the image of FIG. Extracts a boundary pixel (A) that switches from a white pixel (0) to a black pixel (1), and a reference pixel (E, F) adjacent to the boundary pixel (A) on the preceding or next scanning line. ) To determine * 1 and * 2. Note that * 2 is automatically set by bit shift (delay) when * 1 is added.

Next, the unit pixels (* 3, * 4) are determined by first extracting a boundary black pixel (F) that switches from the black pixel (1) to the white pixel (0), and extracts the boundary black pixel (F). * 3 and * 4 are determined by taking the logical product of the adjacent reference pixel (A, G) on the preceding or next scanning line. Note that * 3 is automatically set by a delay when * 4 is added in the same manner as described above. * 1: A (0 → 1) ΛEΛF * 2: A (0 → 1) ΛEΛF * 3: F (1 → 0) ΛAΛG * 4: F (1 → 0) ΛAΛG

FIG. 7 shows an embodiment in which a black unit element is added / deleted. First, boundary pixels (A, A) which are switched from white pixels (0) to black pixels (1) based on image data (a) before smoothing processing.
A ′) is extracted, and the boundary pixel (A, A ′) is ANDed with the adjacent reference pixel (B) on the preceding or next scanning line to determine a unit element * 1 to be added. And a boundary black pixel (B, B) that switches from a black pixel (1) to a white pixel (0).
B ′), and a reference pixel (A, B) adjacent to the boundary black pixel (B, B ′) on the preceding or next scanning line.
A ′) is the same as above until the logical AND is determined to determine * 2, but in the case of deletion, the boundary black pixels (B, B ′) are extracted and the boundary black pixels (B, B ′) are extracted. And a unit element to be deleted by taking the logical product of the same scanning line and the adjacent reference pixels (A, A'D) on the preceding or next scanning line *
3 is determined. * 1: A, A ′ (0 → 1) ΛB * 2: B, B ′ (1 → 0) ΛA (A ′) * 3: B, B ′ (1 → 0) ΛD (A) ΛA (A ′) )

FIG. 8 shows another embodiment in which the lower two unit element lines (iii, iv) of the scan line are associated with the upper two unit element lines (i, ii) of the next scan line. A procedure for setting the additional unit elements (a to g) will be described. First, a boundary pixel (A) that switches from a white pixel (0) to a black pixel (1) is extracted on the I scan line, and the boundary pixel (A) and II
The logical AND of the adjacent reference pixels (E, F) on the scanning line is calculated, b is set one bit ahead in the iii unit element line, and then the black pixel (1) to the white pixel ( 0), and a reference pixel (G, H) adjacent to the boundary black pixel C on the II scan line is extracted.
AND is performed, and b2 is set by delaying one bit in the iii unit prime line, and then a1, a2 and g1, g are respectively delayed or delayed by two bits in the case of the iv unit prime line.
Set 2.

Similarly, the II scan line is also applied to the boundary pixels (F, G).
Is extracted, and the logical product of the boundary pixel (F, G) and the adjacent reference pixel (A, B or B, C) on the I scan line is calculated, and the ii unit elementary line is shifted by one bit in the same manner as described above. (Delay), d and f are set, and in the case of an i-unit elementary line, c / e is set by leading (delaying) by 2 bits each, but at this time, c and e are ORed due to double. To make a black pixel. Therefore, even in such a method, smoothing can be easily performed by calculating the logical sum of the boundary pixel (F, G) and the reference pixel (A, B, C).

[0026]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; However, unless otherwise specified, the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention, but are merely illustrative examples. Not just. FIG.
Is a time-division LED head circuit which takes in a pixel-divided unit element to which the present invention is applied and sequentially drives and controls the LED elements in n-bit units.
An LED array 10 in which a plurality of LED chips 1A... Incorporating the ED elements 1a are arranged in a row is a drive IC for the LED array, and has a memory capacity corresponding to the number n of LED elements for each chip. shift register 11, the number of switches element corresponding to the latch circuit 12, LED elements number n with
It consists switching circuit 13 comprising, thereby connecting the LED element 1a and the switching element 1 3 of the chip 1A through Matorittasu shaped wiring pattern.

Reference numeral 4 designates the switch circuit 13 and the L for each transfer control of the unit element to the shift register 11 side by n bits.
A block designating circuit for sequentially and selectively switching connections with the ED chips 1A.

Next, the operation of the head circuit will be briefly described. First, the first n-bit unit element is serially taken into the shift register 11 from the control circuit 53 (see FIG. 3) and stored based on the clock. Later, the control circuit 5
Each of the LED elements 1a of the corresponding LED chip 1A is transmitted by causing the latch circuit 12 to latch the n-bit unit element in parallel based on the latch signal and transferring an output signal based on the latched data to the switch circuit 13 side.
Is performed.

After the data is transferred to the latch circuit 12, the shift register 11 continues to serially store the next n-bit unit element. After storing the n-bit data, the latch circuit 12 Side, latches the data and transmits a switching signal from the control circuit 5 to the block designating circuit 4, switches the connection of the switch circuit 13 to the next LED chip 1B, and drives each LED element 1a of the LED chip 1B. Then, the same operation is continuously performed m times, and data of a unit element for one scanning line is output.

Hereinafter, the LED chips 1A to 1N are manufactured in the same manner.
Is performed m times (N × m times) × 5 times, pixel data of one scan line as a unit element group divided into five or four as shown in FIG. 5 is developed.

FIG. 3 shows an embodiment according to claims 1 to 3,
In FIG. 3, a control circuit provided on the video output side
After the image information corresponding to the plurality of main scanning lines is fetched and smoothed, the divided pixel data after the processing is serially transmitted to an LED head circuit provided in the print engine. .

To briefly explain the structure, reference numeral 51 denotes a pattern memory. For example, pixel signals for one scanning line developed in a video memory (not shown) are serially stored in the memory 51 based on a reference clock signal. The pixel signal line to be output and the pixel signal line corresponding to one or more scanning lines before and after the pixel signal line are always stored in the memory 51 while being input. Reference numeral 52 denotes a decoder which also serves as a logic circuit, as shown in the enlarged portion of FIG. 3B, image information adjacent to the pixel of interest in the pattern memory 51, more specifically, R dots in the main scanning direction and R dots in the sub scanning direction. The divided pixels corresponding to the respective unit elements P1 to P5 based on the selector signal SL indicating the divided unit elements P1 to P5 corresponding to the information taken from the control circuit 53, taking into account the image information in the matrix R # 1 for the dots. A signal is generated based on a predetermined logic circuit.

The divided pixel signal generated by the decoder 52 is transferred to a shift register on the print engine side via a control circuit 53 based on a reference clock CLK. On the other hand, each time the one divided signal is transferred to the shift register, pixel information (R #) to be referred to in the pattern memory 51 based on the reference clock CLK.
.. are sequentially generated while shifting n) one bit at a time in the main scanning direction. For example, a divided pixel signal for one scanning line corresponding to the divided unit element P1 is shifted via the control circuit 53 by the shift register. 11, the select signal SL is switched after the transfer, and the divided pixel signal corresponding to the unit element P2 is transferred based on the logic circuit incorporated in the decoder 52, and the above operation is repeated thereafter.

More specifically, of the five unit element groups divided in the sub-scanning direction, for example, three unit element groups except upper and lower unit elements P1 and P5 based on a selector signal SL from a control circuit (not shown). The image data is generated while repeatedly applying the pixel signal to the unit element groups P2 to P4. At this time, the pixel of interest to be subjected to the smoothing process in accordance with the pixel information of another adjacent scanning line As for, the unit elements P1 to P5 to be applied based on the logic circuit incorporated in the decoder 52 are increased or decreased in the number of unit elements to be applied in the sub-scanning direction as described in detail in the section of the operation of the present invention. While developing the divided pixel pattern.

A shift register 1 of the LED head circuit on the print engine side receives the unit pixel data output from the decoder 52 based on a reference clock.
1 is a control circuit for serial transmission. The unit elements serially transferred from the control circuit 53 are taken in, and the LED elements are sequentially driven and controlled in n-bit units on the LED head circuit 1 side. According to such a circuit, the smoothing processing based on the invention described in claim 1 can be performed smoothly.

FIGS. 9 and 10 show a smoothing circuit according to an embodiment of the present invention. FIG. 9 is a block diagram showing an overall configuration diagram of a smoothing processing circuit according to the present invention. For example, video data (hereinafter, VDATA) video-developed in an image RAM or the like (not shown) is converted into VCLK generated by a VCLK generation circuit 101. The data is serially transferred to the shift register 104 in synchronization with the shift register 10.
After converting the data into N + 1 bit parallel data in SRA4,
The data is stored in the first bank and the first address of M105. The subsequent N + 1-bit converted parallel data is stored in the second address, and thereafter, by repeating this, VDAT for one line
A is stored in the first bank of the SRAM 105.

Similarly, VDATA of the second line is sequentially stored in the second bank, and VDATA of the third line is sequentially stored in the third bank. And VDATA for N lines is S
When stored in the first to Nth banks of the RAMIO5, the SRAM
The control circuit 103 uses the time until VDATA to be stored in the first address of the (N + 1) th bank is prepared,
VD stored at each first address of the first to Nth banks
The ATA is sequentially read out based on the latch signal, stored in the latch and shift registers 106 to 112, respectively, and the converted parallel data is stored in the Nth bank and the first address based on the signal from the SRAM control circuit 103, and at the same time. , Latch and shift register 1
The data stored in 06 to 112 is loaded into the N-line shift register 113.

By repeating the above operation in the same manner, the VDATA of the (N + 1) th line is changed to the (N + 1) th line of the SRAM 105.
The VDATA of the first to Nth lines stored in the SRAM 105 are continuously supplied to the N-line shift register 113 via the latch and shift registers 106 to 112 while being stored in the bank. Then, the SRAM 105
On the other hand, when the VDATA of the Nth line is stored in the Nth bank, the VDATA of the ninth line is stored in the first bank based on the control signal from the SRAM control circuit 103, and then the 10th line
By storing the VDATA of the line in the second bank, the contents of the first to Nth banks are sequentially updated.

As a result, the N-line shift register 1
13 stores a bit map (N × 7) of one or more lines before and after the reference pixel (center bit), and three bits on the left and right sides while sequentially updating the contents by data transfer from the SRAM 105. Smoothing processing in the smoothing processing circuit 120 described later can be performed using the bitmap.

The smoothing processing circuit 120 is an AND logic comprising selectors 121A and 121B for selecting the reference pixel and AND circuits 122A and 122B (FIG. 10).
H, a line counter 1 for selecting a unit element line of each pixel
24, a delay circuit 125 that fills (deletes) one bit between the addition (deletion) unit element obtained by the logical sum or the logical product and the boundary pixel when the bit is empty.
A, 125B, a line counter 124 for selecting which unit element line, and a divided pixel video data after the smoothing processing is serially transmitted to the LED head circuit side while taking a logical sum of the additional unit element and the logical unit or the deleted unit element. An OR gate 127 and an AND gate 128 are provided.

Next, the operation of the smoothing processing circuit 120 will be described with reference to FIG.
First, a boundary pixel (A) that switches from a white pixel (0) to a black pixel (1) is extracted on a corresponding scan line M of an N-line scan register, and then a counter from a line counter 124 is extracted. N based on the signals (i to iv)
The leading P-1 to the next P + in the line shift register 113
One or a plurality of reference pixels adjacent to the boundary pixel A among the pixels (BM) located on one scan line are selected by the selector 12.
1A, 121B, that is, when the counter signal is i, ii, the pixels (B to B) located on the scan line of the leading P-1
G), and when the counter signal is iii or iv, a reference pixel is selected from the pixels (H to M) located on the next (P + 1) scan line.

The reference pixel and the boundary pixel are ANDed.
The necessary addition (deletion) unit elementary signal is generated by taking a logical product in the circuits 122A and 122B, and the addition (deletion) unit obtained from the AND circuits 122A and 122B by the delay circuits 125A and 125B when necessary. As described above, two bits of continuous addition (deletion) unit elementary signals are generated by further adding one bit between the elementary signal and the reference pixel. The addition (deletion) unit elementary signal for smoothing processing obtained as described above is added to the OR circuit 129A,
129B and the video data output from the N-line shift register 113 and the OA gate 127 take the logical sum (in the case of addition) or the AND gate 128 and take the logical product (deletion) to divide the LED in unit element line units.
Serially transmitted to the head circuit side.

According to this embodiment, the operation of the present invention described above can be smoothly achieved. In the present invention, in order to perform different smoothing processing operations when adding and deleting unit pixels for smoothing, selectors 121A, 121B, AND
Circuits 122A and 122B, delay circuits 125A and 12
5B and a pair of OR circuits 129A and 129B are provided.

[0044]

As described above, according to the present invention, there is provided a thermal printer or an LED printer having a line array recording head for outputting an image by dividing one pixel into a plurality of unit elements in the sub-scanning direction. In the invention described in the first aspect, the circuit configuration is complicated by shifting or increasing or decreasing the unit element in the sub-scanning direction, and in the invention described in the fourth aspect, by taking the logical product of the boundary pixel and the reference pixel. Without this, the smoothing process can be easily and accurately performed with a simple determination operation. And so on.

[Brief description of the drawings]

FIGS. 1A and 1B are basic configuration diagrams showing a print arrangement state for smoothing processing of the present invention.

FIGS. 2A and 2B show a print arrangement state for smoothing processing in which a smoothing unit element is shifted to an adjacent pixel area;

FIG. 3 is a block diagram of a smoothing processing circuit according to an embodiment of the present invention.

FIG. 4 is an LE adopting a time division method to which the present invention is applied;
LED printer circuit diagram of D printer

FIG. 5 shows a dot pattern output by the LED head circuit of FIG.

FIG. 6 shows an operation procedure for performing the smoothing processing operation of the invention according to claim 4, and particularly, FIG. 6 shows a procedure for performing the smoothing processing only by adding a unit element.

FIG. 7 shows an operation procedure for performing the smoothing processing operation according to the fourth aspect of the present invention. In particular, FIG. 7 shows a procedure for performing the smoothing processing by adding / deleting unit elements.

FIG. 8 shows an operation procedure for performing the smoothing processing operation according to the fourth aspect of the present invention, and in particular, FIG. 8 shows a procedure for performing the smoothing processing by focusing on adjacent unit element lines.

FIG. 9 is an overall block diagram of a controller for smoothing processing according to an embodiment of the present invention.

FIG. 10 is a block diagram of a main part of a smoothing processing circuit in FIG. 9;

Continuation of front page (56) References JP-A-61-45675 (JP, A) JP-A-64-24568 (JP, A) JP-A-1-321578 (JP, A) JP-A-3-142260 (JP) JP-A-3-265875 (JP, A) JP-A-62-200976 (JP, A) JP-A-54-153515 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB Name) B41J 2/485 G06T 5/30 G09G 5/28 610

Claims (4)

(57) [Claims] 1. One pixel is divided into a plurality of unit elements P in the sub-scanning direction.
(P ≧ 3), and an image smoothing processing method of outputting a pixel pattern in one scan line or n-bit units while appropriately applying a corresponding pixel signal to the divided unit element. A unit element group N (N <P) less than the divided unit element P
In addition, a pixel pattern is formed while applying a corresponding pixel signal, and at the time of smoothing processing, a reference pixel to be subjected to smoothing processing in correspondence with adjacent pixel information is selected, and a unit element of the selected reference pixel is selected. After applying the pixel signal to
Increase or decrease or move the added unit element group N back and forth in the sub-scanning direction
And outputting the pixel pattern. 2. The image smoothing processing method according to claim 1, wherein a unit element to which the pixel signal is applied is increased or decreased within a range of one pixel. 3. The image smoothing method according to claim 1, wherein a unit element to which the pixel signal is applied is added to a unit element of another pixel adjacent to the pixel beyond one pixel. 4. A pixel dot is divided into a plurality of unit element groups in the sub-scanning direction, and a pixel pattern is formed in one scanning line or n-bit unit while appropriately applying a corresponding pixel signal to the divided unit element group. In the image smoothing processing method to be output, the image signals corresponding to all the divided unit elements are not applied.
During the smoothing process , a pixel pattern to which a pixel signal is not applied (hereinafter, referred to as a white pixel) to a pixel to which a pixel signal is applied (hereinafter, referred to as a black pixel) or the black pixel is formed. While performing a logical calculation with a boundary pixel that switches from to a white pixel and one or more reference pixels located on a preceding or next scanning line adjacent to the boundary pixel, on a scanning line of the boundary pixel, and 1 or located on the sub-scanning line of the reference pixels appropriately adding or black unit containing a plurality of pixel dots, and performing a smoothing process to reduce the unit element of the addition and the boundary pixel Image smoothing processing method .