JPH0564901U - Comparison circuit - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a comparison circuit, and an object thereof is to realize a comparison circuit which is stable against temperature changes and suitable for IC. A voltage comparison unit 101 that compares a compared voltage with a reference voltage and changes an output value according to the result, and a current supply unit 102 that supplies an output current Iz according to the output of the voltage comparison unit 101. The first voltage drop unit 103 is provided with the output current I _Z of the current supply unit 102 and generates a voltage drop ΔV according to the output current value. The compared voltage is supplied to the voltage comparison means 101 via the first voltage reduction means 103, and the current supply means 102 is
The temperature coefficient of the output current I _Z is set to be substantially zero.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a comparison circuit, and more particularly to a comparison circuit applied to a system abnormality detection circuit or the like.

[0002]

[Prior Art]

 4 (A) and 4 (B) each show an example of a conventional comparison circuit. In the comparison circuits 3 and 4 of FIG.₁Current source I to the non-inverting input terminal of_CC1And Zenada Iodo D₁A reference voltage generated by a series circuit of and is supplied. Also, A₁ Power supply voltage V to the inverting input terminal of_CCIs resistance R_Four, R_Five, Or R_Four, R_Five’、 R _Five It is supplied after being divided by ".₁The output terminal of the transistor Q₃Is connected to the base of Q₃The collector of is the feedback resistor R in circuit 3._fThrough A₁It is connected to the inverting input terminal of_Five’、 R_FiveIs connected to the common connection point of ".₁Resistor R to the inverting input terminal of ₆ Through the noise prevention capacitor C_NAre connected.

In each of these circuits 3 and 4, A₁V compared to the reference voltage supplied to the non-inverting input terminal of_CCThrough a resistor A₁If the voltage supplied to the inverting input terminal of is high₁Output is low (L) level, and conversely, when it is low, A₁Output is at high (H) level. A₁When the output of is at L level, the transistor Q ₃ Is turned off, Q₃Almost no collector current flows, and in circuit 3, R_Four, R ₆ , R_f, In circuit 4 R_Four, R_Five’₃The current (feedback current) flowing into the collector of is almost zero.

On the other hand, when the output of Q ₃ is at H level, the transistor Q ₃ is turned on, and therefore R ₄ , R ₆ , R _{f in} the circuit 3 and R ₄ , R ₅ 'in the circuit 4 are turned on. A feedback current flows into the collector of Q ₃ via each of them. Therefore, in this case, the resistances through which the feedback currents flow respectively cause a voltage drop. Due to this voltage drop, V _CC of the operational amplifier A ₁ is inverted when the transistor Q ₃ is turned on and off. There is a difference in voltage. This is called a hysteresis characteristic, and it is a general characteristic required when performing a stable voltage comparison operation.

[0005]

[Problems to be solved by the device]

 In comparison circuit 3, however, feedback resistor R_fIt is necessary to minimize the feedback current that flows through the feedback resistor R for that purpose. _f It is necessary to use a resistor having a high value of about 10 MΩ. Such a resistor having a high resistance value is wide due to the resistance Rf when the circuit is made into an IC (integrated circuit), particularly when the precision of the resistance value is increased in order to improve the accuracy of the hysteresis characteristic. Area is required. This has been an obstacle to miniaturization of the circuit.

Further, in the circuit 4, since the feedback resistor R _f is not used, the above problem does not occur, but the noise absorbing capacitor C _T is directly connected to the inverting input terminal of the operational amplifier A ₁ . Therefore, the transient phenomenon of the charge / discharge operation of the capacitor C _T hinders the voltage detection operation of A ₁ .

The present invention has been made in view of the above problems, and an object of the present invention is to provide a comparator circuit which is stable against temperature changes and suitable for use in an IC.

[0008]

[Means for Solving the Problems]

The present invention compares the voltage to be compared with a reference voltage and changes the output value according to the result, as shown in the principle block diagram of FIG. 1, and according to the output of the voltage comparison means 101. It comprises a current supply means 102 for supplying an output current Iz, and a first voltage drop means 103 for supplying the output current I _{Z of the} current supply means 102 to generate a voltage drop ΔV according to the output current value. The voltage to be compared is supplied to the voltage comparison means 101 via the first voltage drop means 103, and the current supply means 102 is constructed so that the temperature coefficient of the output current I _Z becomes substantially zero. ing

[0009]

[Action]

In the present invention, since the temperature coefficient of the current I _Z supplied to the first voltage drop means 103 is set to substantially zero, the temperature of the voltage drop amount ΔV that is transmitted when the compared voltage is supplied to the voltage comparison means 101. The coefficient can be substantially zero.

[0010]

【Example】

FIG. 2 shows a circuit diagram of an embodiment of the present invention. The comparison circuit 1 shown in the figure is applied to a system abnormality detection circuit (hereinafter referred to as "watchdog circuit"), etc., which will be described later, and is used when the power supply voltage V _CC is lower than the reference voltage. This is to generate a reset output that resets the operation of.

The comparison circuit 1 generally includes an operational amplifier A ₁ (the voltage comparison means) as a differential amplifier, and four NPN transistors Q _{1 to} Q ₄ connected to the output of the operational amplifier A ₁ . A constant current source I _CC1 is connected between the inverting input terminal of the operational amplifier A ₁ and the power supply V _CC, and a Zener diode D ₁ is connected between the inverting input terminal and the ground. A series circuit of resistors R ₄ and R ₅ is connected between the power source V _CC and ground, and the common connection point between the resistors R ₄ and R ₅ is the hysteresis resistor R ₆ (the first Voltage drop means) to the non-inverting input terminal of the operational amplifier A ₁ .

The base of the transistor Q ₃ is connected to the output terminal of the operational amplifier A ₁ , the collector of Q ₃ is connected to the power supply V _CC via the resistor R _7, and the emitter of Q ₃ is grounded. .. The collector and emitter of the transistor Q ₁ (the third transistor) are connected to the collector and emitter of Q ₃ , respectively. The base of the transistor Q ₄ (first transistor) is connected to the collector of Q ₁ , the collector of Q ₄ is connected to the power source V _CC, and the emitter of Q ₄ is the resistor R ₁ (the second voltage). The voltage drop means) and R ₂ (the third voltage drop means) are connected to the ground via a series circuit. The base of the transistor Q ₂ (second transistor) is connected to the emitter of Q ₄ , the collector of Q ₂ is connected to the non-inverting input terminal of the operational amplifier A ₁ , and the emitter of Q ₂ is a resistor. It is grounded via R ₃ (the fourth voltage drop means). Note that the current supply means is constituted by four transistors Q ₁ to Q ₄ and four resistors R ₁ ~R _3, R _7.

Next, the operation of the comparison circuit 1 having the above configuration will be described. Constant current source I_CC1Zener diode D supplied with constant current from₁Functions as a constant voltage source. This Zener diode D₁Is the operational amplifier A as the reference voltage.₁It is supplied to the inverting input terminal of. Operational amplifier A compared to this reference voltage₁If the voltage supplied to the non-inverting input terminal of₁Output becomes low (L) level, and conversely when it is high, A ₁ Output becomes high (H) level.

Here, the power source V_CCIs the resistance R_Four, R_FiveThe voltage is divided by the series circuit of₆Through A₁Is supplied to the non-inverting input terminal of. Power supply V_CCGradually rises from the zero condition, but A₁The voltage supplied to the non-inverting input terminal of the Zener diode D₁If it is lower than the reference voltage supplied to the inverting input terminal by₁Is output at the L level as described above. Therefore transistor Q ₃ Almost no base current flows₃Is off and Q₃Almost no collector current flows. Therefore transistor Q_FourCurrent is applied to the base of_FourIs turned on and Q_FourCurrent from the emitter of the transistor Q₂Flows into the base of₂Is turned on. This makes Q₂Current I to the collector of_Z(Feedback current) flows in and its current I_ZIs the hysteresis resistance R₆And resistance R_FourPower through V_CCSupplied from

[0015] Further, the transistor Q ₄ is a current flows to the base for Q ₁ for a on-state, Q ₁ is in the ON state. Here, the collector current of Q ₁ is referred to as I ₁ .

Further, as described above, the feedback current I _Z is supplied from the power supply V _CC via the hysteresis resistance R ₆ and the resistance R ₄ , so that the voltage supplied to the inverting input terminal of the operational amplifier A ₁ is It is a value obtained by dividing the voltage of the power source V _CC by the series circuit of the resistors R ₄ and R ₅ and then reducing the voltage drop ΔV generated in the hysteresis resistor R ₆ by the I _Z. Then further increase the power V _CC is, the resistance R _4, the series circuit of R _5, the voltage supplied to the non-inverting input terminal of the operational amplifier A ₁ via a hysteresis resistor R ₆ is of the operational amplifier circuit A ₁ The output of A ₁ becomes H level when it increases as compared with the reference voltage supplied to the inverting input terminal. The voltage of the power supply V _CC when the output of A ₁ is inverted is referred to as a "rising threshold value".

As a result, a current flows into the base of the transistor Q ₃ , Q ₃ is turned on, and a current flows into the collector of Q ₃ . Therefore, the base potential of the transistor Q ₄ is greatly reduced due to the voltage drop of R ₇ , Q ₄ is turned off, and the emitter current of Q ₄ is hardly passed. Therefore the transistor Q is ₂ and Q ₁ of the base not flow current almost, Q _2, Q ₁ is turned off, respectively. Therefore, the collector current I _Z of the transistor Q ₂ hardly flows, so that almost no current flows in the hysteresis resistor R ₆ and almost no voltage drop occurs in R ₆ .

Next, the power supply voltage V_CCIs reduced from the normal value due to a failure of the power supply means (not shown), the operational amplifier A₁The voltage supplied to the non-inverting input terminal of₁It is lower than the reference voltage supplied to the inverting input terminal of₁The output of is inverted and becomes L level again. This A₁Power supply V when the output of_CCIs called the "falling threshold value". However, power supply V here_CCIn the stage in which the voltage of is larger than the above "falling threshold value", the feedback current I_ZHardly flows, and the hysteresis resistance R₆Almost no current flows through. Therefore R₆Voltage drop ΔV hardly occurs, and I _Z Is resistance R_FourHardly flows to I_Z× R_FourDoes not occur.

Therefore, the voltage applied to the non-inverting input terminal of the operational amplifier A ₁ is a value at which the voltage of the power supply V _CC is lower than the “threshold value at rise” by ΔV and I _Z × R ₄ described above. For the first time, the output voltage of the operational amplifier A ₁ is inverted, that is, the value corresponding to the reference voltage supplied to the inverting input terminal of A ₁ is lowered. Thus the "falling time threshold" becomes the ΔV and I _Z × R ₄ minutes less than the "rise time threshold". In this way, the characteristic that a certain difference is generated between the "rising threshold" and the "falling threshold" is called the hysteresis characteristic, which is generally required when performing stable voltage comparison operation. Characteristics.

Here, the voltage applied to the resistor R ₃ is referred to as V _Z. In the transistor Q _2, the value of the base current is almost negligible as compared with the collector current I _Z , so that the collector current I _Z is I _Z ≈V _Z / R ₃ . Next, this V _Z is

[0021]

[Equation 1]

It can also be stopped. Here, V _T = (kT / q) k is the Boltzmann constant, T is the absolute temperature, and q is the electric charge. Further, A _E1 and A _E2 represent the areas of the PN junctions of the transistors Q ₁ and Q ₂ , respectively. Further, A _E1 × I ₀ and A _E2 × I ₀ are approximately equal to the values obtained by reversing the signs of the reverse saturation currents of the transistors.

In the above equation, the resistance R₁, R₂Mutual ratio of each, and each transistor Q₁, Q ₂ The temperature coefficient of the equation is made substantially zero by appropriately setting the mutual ratio of the areas of the respective PN junctions as shown below.

First, let n be the ratio of the area of each PN junction to the transistor Q ₁ of Q ₂ . Therefore, the formula is as follows.

[0025]

[Equation 2]

Where

[0027]

[Equation 3]

That is, the rate of change of V _Z with respect to temperature at room temperature is set to 0. The left side of the above equation is

[0029]

[Equation 4]

It becomes In the formula, V _BE2 'is a value obtained by taking out ln (n) contained in V _BE2 and removing it from V _BE2 .

Since the value in the parentheses of this equation is the temperature coefficient of V _Z , it is set to 0 next.

[0032]

[Equation 5]

It becomes here,

[0034]

[Equation 6]

Both are temperature coefficients of the base-emitter voltage of the transistor and are equal to each other.

[0036]

[Equation 7]

Then, the above equation becomes

[0038]

[Equation 8]

It becomes The ratio of the mutual resistance values of the resistors R ₁ and R ₂ and the ratio of the mutual area of the PN junctions of the respective transistors Q ₁ and Q ₂ may be appropriately set so that the equation is satisfied. Further, by appropriately setting the operating point of the transistor Q ₂ , the collector current I _Z of Q ₂ can be suppressed without increasing the resistance value of the resistor R ₃ so that it is supplied to the hysteresis resistor R ₆ . The current value of the feedback current I _Z can be made relatively low. In the case of the present embodiment, by setting R ₃ to about 100 kΩ and V _Z to about 100 mV, it is possible to form a low-current current source of about 1 μA.

Therefore, it is possible to form a low-current current source whose current value does not change with temperature by using a resistor having a relatively low resistance value. Therefore, the power consumption of the comparison circuit 1 can be suppressed to a low level, and energy can be saved. Furthermore, it is possible to avoid manufacturing problems (particularly the IC area becomes large) that occur when converting a circuit using a highly accurate and high resistance resistor into an IC (integrated circuit). In addition, it is possible to make ICs in a small size. Also, the hysteresis resistance R₆Current I flowing in_ZSince the temperature coefficient of ΔV and I can be made substantially zero, _Z × R₆The temperature coefficient of can be made substantially zero, and a comparator circuit with stable hysteresis characteristics against temperature changes can be realized.

FIG. 3 shows the watchdog circuit to which the comparison circuit 1 of FIG. 2 is applied. The watchdog circuit 2 in the figure is for monitoring the power supply V _CC of the system such as another logic circuit to which this circuit is applied and the two clocks CK1 and CK2 as the synchronizing signals of the operation of this system. Is. The watchdog circuit 2 includes a watchdog unit 10, a power supply monitoring unit 20, a clock monitoring unit 30, a reset output unit 40, and an RCT unit 50. A voltage of 0.8 V is applied to the non-inverting input terminal of the operational amplifier A ₅₁ of the RCT section 50.

The watchdog unit 10 includes three transistors Q ₁₁ , Q ₁₂ , and Q ₁₃ , three flip-flop circuits F ₁₁ , F ₁₂ , and F ₁₃ and two operational amplifiers A ₁₁ and A ₁₂ . Become A voltage of 0.2 V is applied to the non-inverting input terminal of the operational amplifier A ₁₂ . In the watchdog unit 10, if at least one of the signals input to the logic circuit L ₁₁ that takes the sum of each negated input is low (L) level, its output is high (H). It becomes a level. In the flip-flop circuit F ₁₁ which receives an H level input from the logic circuit L ₁₁ to the S terminal, its output Q becomes H level, a current is flown into the base of the transistor Q ₁₁ , and the Q ₁₁ is turned on. A collector current flows in Q ₁₁ which is in the ON state, and the collector current discharges the electric charge of the capacitor C _T connected to the terminal T _C.

[0043] Further, the voltage terminal voltage of the capacitor C _T is supplied to the inverting input terminal of the operational amplifier circuit A ₁₂ reaches a predetermined threshold voltage V _CT has exceeded the threshold value of the A _12, the A ₁₂ The output goes high. The H-level output of A ₁₂ is input to the reset terminal R of the flip-flop circuit F ₁₁ , whereby F ₁₁ is reset and its Q output becomes L-level. With this L level output, almost no current flows into the base of the transistor Q ₁₁ , Q ₁₁ is turned off, and the discharge of the electric charge of the capacitor C _T is stopped.

Flip-flop circuit F₁₂The output of the power supply monitoring unit 20 is connected to the terminal XS set at the L level. The power supply monitoring unit 20 has a function substantially similar to that of the comparison circuit 1 as will be described later, and the power supply terminal T_VCCSupply voltage V supplied to_CCIs lower than the threshold, operational amplifier A₁Output becomes L level. This L level signal is the flip-flop circuit F₁₂F is input to the XS terminal of₁₂Is set, and its output Q becomes H level. The signal is the NOR circuit L of the reset output unit 40.₄₂ Input to L₄₂Output becomes L level, which is the NOT circuit N₄₁ Is inverted to H level, and transistor Q₄₁Is turned on. Therefore terminal T_RSTBecomes L level. Next, the clock monitoring unit 30 generally has three pulse generators P.₁~ P₃And the flip-flop circuit F₃₁And consists of. In this circuit 30, two kinds of clock pulses CK1 and CK2 from the system to which the watchdog circuit 2 is applied are respectively supplied to the terminals T. _CK1 , T_CK2Entered in. Pulse generator P₁, P₂Receives a falling edge of CK1 and CK2, respectively, and generates a negative pulse. Flip-flop circuit F₃₁Then the pulse generator P₁, P₂It is set and reset in response to the negative pulse input from each of, and the output Q is set to H level and L level. In addition, the logic circuit L that inverts the input signal and then calculates the product₃₁Then, the pulse generator P₁, P₂It receives the negative pulse emitted from each of the above and outputs the H level only during that period. Pulse generator P₃Then, the flip-flop circuit F₃₁Generates a positive pulse on the falling edge of the output of. NAND circuit L₃₂Then L₃₁And P₃In response to the respective outputs of the above, only when both are at the H level, the L level is output.

[0045] In the clock monitoring circuit 30, is set flip-flop circuit F ₃₁ when the falling edge of the pulse CK1 is inputted, F ₃₁ when the next falling edge of the pulse CK2 is inputted Will be reset. This reset feeds the falling edge from F ₃₁ to the pulse generator P ₃ , which causes P ₃ to generate a positive pulse. At this time, the logic circuit L ₃₁ outputs the H level by the negative pulse generated from the pulse generator P ₂ in response to the falling edge input from CK2. Therefore, the NAND circuit L ₃₂ receives these positive pulse and H level signal at the same time and outputs L level. This output is input to the logic circuit L ₁₁ of the watchdog unit 10 to discharge the charge of the capacitor C _T as described above.

The power supply monitoring unit 20 has substantially the same circuit configuration as the comparison circuit 1. However, the current source I in the comparison circuit 1_CC1Has a power terminal T at one end_VCCResistor R connected to₂₀Has been replaced by. Also, the hysteresis resistor R in the comparison circuit 1 ₆ , Transistor Q₁~ Q_Four, Resistance R₁~ R₃, R₇The illustration of each is omitted. In this circuit, like the comparison circuit 1, the power supply terminal T_VCCPower supply V_CCRises and reaches the above-mentioned "rising threshold", the operational amplifier A₁Output becomes H level and becomes L level when it falls and reaches the above-mentioned "falling threshold value".

FIG. 4 shows an operation time chart of the circuit of FIG. In the figure, (A) to (E) respectively indicate the power supply voltage V _CC , the clocks CK1 and CK2, the voltage of the capacitor C _T , and the voltage of the reset output output from the terminal T _RST . In the figure (A), when the power supply voltage V _CC gradually rises and reaches 0.8 V at the time a, the transistor Q ₄₁ of the reset output section 40 is turned on, and the transistor Q ₄₁ of the figure (E) is turned on. The reset output becomes almost 0. When V _CC further rises and reaches the above-mentioned "threshold value rising time" V _SH in FIG. 7A, the output of the power supply monitoring unit 20 becomes H level as described above. This output is input to the XS terminal of the flip-flop circuit F ₁₂ of the watchdog section 10, F ₁₂ is set, its XQ output becomes L level, and the transistor Q ₁₂ which was in the on state until then is turned off. ..

By this, Q₁₂The substantially conductive state between the collector and the emitter of the _CC11 Through the capacitor C_TThe electric charge begins to be charged. Therefore, from this time point b, the capacitor C in FIG._TVoltage starts to rise. Further C_TThreshold voltage V_CTOperational amplifier A₁₁Exceeds the threshold of₁₁Output of L level. This L level is the logic circuit L₁₁Is input to the flip-flop circuit F as described above.₁₁Set the transistor Q₁₁Is turned on, and the capacitor C_TDischarges the electric charge of. Also, A₁₁Flip-flop circuit F becomes₁₂Is reset. Therefore F₁₂Q output of becomes the L level. Furthermore A₁₁ Since the output of is set to the L level, the signal is changed to the NOT circuit N₁₁, NAND circuit L₁₂Through the flip-flop circuit F₁₃Is supplied to the XS terminal of the flip-flop circuit F₁₃Is set.

The voltage of the capacitor C _T decreases due to discharge, and the voltage decreases to about 0. When it becomes 2V, the output of the operational amplifier A ₁₂ becomes H level as described above. Therefore, this output is input to the R terminal, the flip-flop circuit F ₁₁ is reset, the transistor Q ₁₁ is turned off, and the charging of the capacitor C _T is started again. When the Q output of F ₁₁ is set to L level, the signal is input to the XR terminal of the flip-flop circuit F ₁₃ and F ₁₃ is reset. Therefore, the Q output of F ₁₃ is set to the L level, and this is input to the NOR circuit L ₄₂ of the reset output section 40 together with the Q output of the flip-flop circuit F ₁₂ which is set to the L level as described above, whereby the output of L ₄₂ is output. Is set to the H level, which is inverted through the NOT circuit N ₄₁ and set to the L level, turning off the transistor Q ₄₁ . Therefore, an H level signal is output from the very T _RST terminal shown at time point c in FIG.

Thereafter, as described above, the clock monitoring unit 30 sequentially inputs the clocks CK1 and CK2, respectively, whereby d, d ′, and At each time point of d ″, a positive pulse is generated from the pulse generator P ₃ to supply the L level to the logic circuit L ₁₁ of the watchdog section 10. Therefore, the flip-flop circuit F ₁₁ is set. The transistor Q ₁₁ is turned on, and the capacitor C _T is discharged as shown at the time points d, d ′, and d ″ in FIGS. Become. As a result, the output of the operational amplifier A ₁₂ is set to H level, the flip-flop circuit F ₁₁ is reset, the transistor Q ₁₁ is turned off, and the charging of the capacitor C _T is started.

The above operation is repeated while the power supply V _CC is equal to or higher than the “falling threshold value” V _SL and the clocks CK1 and CK2 are normally generated periodically. Therefore, the transistor Q ₄₁ of the reset output section 40 is not turned on, and the reset output output from the terminal T _RST is maintained at the H level. However, when the clock CK2 is periodically input as shown at time point g in FIG. 4 but CK1 is interrupted, the pulse generator P ₁ of the clock monitoring unit 30 does not generate a negative pulse after that, and therefore the flip-flop circuit is not generated. F ₃₁ cannot be set again after it has been reset by the negative pulse generated by pulse generator P ₂ . Therefore, thereafter, no positive pulse is generated from the pulse generator P _3, and the L level is not supplied to the watchdog unit 10.

As described above, when the L level is not supplied to the watchdog unit 10, the capacitor C _T is not discharged and its voltage rises. When this voltage reaches the threshold value V _CH at time h in FIG. 4 (D), the output of the operational amplifier A ₁₁ of the watchdog unit 10 becomes L level as described above, and the signal thereof is the NOT circuit N ₁₁ and the NAND circuit. It is supplied to the XS terminal of the flip-flop circuit F ₁₃ via L ₁₂ , and sets F ₁₃ . The Q output of F ₁₃ , which is set to the H level here, is supplied to the NOR circuit L ₄₂ via the AND circuit L _41, and the output of L ₄₂ is set to the L level. This signal is inverted by the NOT circuit N ₄₁ and set to H level to turn on the transistor Q ₄₁ . Therefore, the reset output supplied from the terminal T _RST falls to about 0.2 V as shown at the time point h in FIG. 4 (E).

In addition, due to a failure of a power supply means (not shown) that supplies the power supply V _CC to the power supply terminal T _VCC , the power supply voltage V _CC is "decreased at the time of falling" as shown at the time point l in FIG. 4 (A). When it decreases to the "threshold value" V _SL , the output of the operational amplifier A ₁ of the power supply monitoring circuit 20 becomes L level as described above. This signal is input to the XS terminal of the flip-flop circuit F ₁₂ of the watchdog unit 10 to set F ₁₂ . The Q output of this by F ₁₂ is an H level, NOR circuit L ₄₂ of reset output section 40 that has received the signal Outputs an L level, which is being inverted transistor Q ₄₁ in the ON state at N ₄₁ .. Therefore, the reset output supplied from the terminal T _RST is approximately 0 .. It falls to 2V. By setting the reset output to approximately 0 in this way, the system to which the watchdog circuit 2 is applied is reset, and the malfunction of the system due to the reduction of the power supply V _CC or the stop of the clocks CK1 and CK2 is prevented.

Further, by connecting a capacitor C _N to the terminal T _CN of the power supply monitor 20, noise contained in the power supply V _CC input from the power supply means is absorbed, and a watchdog circuit due to the noise is absorbed. 2 can be prevented. Here, as described above, the illustration of the resistor corresponding to the hysteresis resistor R ₆ of the comparison circuit 1 is omitted in the power supply monitoring circuit 20, and the noise prevention capacitor C _N is actually connected via this resistor R _6. It is connected to the operational amplifier A ₁ . Therefore, it is possible to prevent the transient phenomenon due to the charging / discharging action of the capacitor C _N when the power source V _CC fluctuates from adversely affecting the voltage detection function of the operational amplifier A ₁ .

Although the above embodiment is an example in which the present invention is applied to the watchdog circuit, it is needless to say that the present invention is not limited to this and can be applied to other power supply monitoring circuits.

[0056]

[Effect of the device]

 As described above, according to the present invention, the temperature coefficient of the amount of voltage drop that occurs when the voltage to be compared is supplied to the voltage comparison means can be made substantially zero, so that it is stable against temperature changes. It is possible to realize a hysteresis characteristic, and by appropriately setting the operating point of the PN junction element of the current control means, it is possible to reduce the current supplied to the first voltage drop means and reduce the power consumption. At the same time, it is possible to inexpensively, easily, and miniaturize the IC.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of the present invention.

FIG. 2 is a circuit diagram of an embodiment of the present invention.

3 is a circuit diagram of a watchdog circuit to which the circuit of FIG. 2 is applied.

FIG. 4 is an operation time chart of the circuit of FIG.

FIG. 5 is a circuit diagram of a conventional example.

[Explanation of symbols]

1, 100 comparison circuit 101 voltage comparison means 102 current supply means A ₁ operational amplifier (voltage comparison means) Q ₁ NPN transistor (third transistor) Q ₂ NPN transistor (second transistor) Q ₄ NPN transistor (first transistor) transistor) R ₁ resistance (second voltage drop means) R ₂ resistor (third voltage drop means) R ₃ resistor (fourth voltage drop means) R ₆ resistance (first voltage drop means)

Claims (2)

[Scope of utility model registration request] 1. A voltage comparison means for comparing a compared voltage with a reference voltage and changing an output value according to the result, a current supply means for supplying an output current according to the output of the voltage comparison means, and And a first voltage drop unit that receives the output current of the current supply unit and causes a voltage drop corresponding to the output current value. The compared voltage is supplied to the voltage comparison unit via the first voltage drop unit. The comparison circuit is configured such that the temperature coefficient of the output current is substantially zero. 2. The current supply means has a first transistor substantially driven by the output of the voltage comparison means, and a base connected to an emitter of the first transistor,
Connecting a second transistor driven by the first transistor, a third transistor driven by the first transistor, an emitter of the first transistor and a base of the third transistor, A second voltage drop means for producing a voltage drop according to the supplied current value and a third voltage drop for producing a voltage drop according to the supplied current value by connecting between the base and emitter of the third transistor. Means for connecting the emitter of the second transistor and the emitter of the third transistor, and a fourth voltage drop means for producing a voltage drop according to the value of the current supplied, the second voltage drop means The collector current of the transistor is used as the output current, and the temperature coefficient of the voltage applied to the fourth voltage lowering means is set to substantially zero, and the second and third voltage lowering means respectively. 2. The comparison circuit according to claim 1, wherein a mutual ratio of the voltage drop amounts of the above and a mutual ratio of the PN junction areas of the second and third transistors are set.