JPH0564547B2 - - Google Patents

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a single-phase bridge thyristor circuit in which a control advance angle γ of 180° is generated when the control advance angle γ is 175°.
This invention relates to a single-phase bridge thyristor circuit that controls conduction of a thyristor using a width gate signal.

(Prior art) In a single-phase bridge thyristor circuit, the gate width of the control pulse applied to the gate that controls the conduction of the thyristor is usually several microseconds, but the capacity of the power supply connected to the single-phase bridge thyristor circuit If the power supply is small and many other thyristor converters are installed in parallel, the commutation surge that occurs when controlling the other thyristor converters, and even the switching surge that occurs when the load is cut off, will cause a single-phase bridge thyristor circuit. This external surge pulse may cause the thyristor elements of the single-phase bridge thyristor circuit to be turned off even though they should remain conductive.

This will be explained using the single-phase pure bridge thyristor circuit shown in FIG. 1 and the waveform diagram shown in FIG. 2.

In Fig. 1, the gate pulse P _UY shown in Fig. 2b is applied to the gates of the U-phase thyristor 3 and the Y-phase thyristor 6, and the AC voltage applied to terminals 1 and 2 is controlled. The U-phase voltage shown by the solid line is applied to the inductive load Z, the U-phase DC current I _DC shown in FIG.
Apply the gate pulse P _VX shown in figure c and connect terminals 1 and 2.
The V-phase voltage shown by the solid line in FIG. 2a is applied to the load Z, and the V-phase DC current I _DC shown in FIG. Power control shall be performed. In such a case, for example, the external surge pulse P _S shown in FIG.
is applied to the gate of the U-phase thyristor 3, the thyristor 3, which had been conducting until now, is extinguished by this external surge pulse, and as shown in Fig. 2 f,
The shaded portion of the direct current I _DC flowing through the U-phase thyristor 3, the load Z, and the Y-phase thyristor 6 disappears. Therefore, a predetermined current cannot be supplied to the load Z, and smooth control cannot be performed.

As a measure against such external surge pulses, there is a method of setting the pulse width of the gate signal supplied to the thyristor element group to 180°. Such a method is
For example, U-phase thyristor 3, Y-phase thyristor 6, V
In this method, 180° width gate signals P' _UY and P' _VX shown in Figure 2 g and h are applied to the gates of phase thyristor 4 and V-phase thyristor 5, and the thyristors are not turned off even if an external surge pulse P _S is applied. .

However, although this measure eliminates the drawbacks mentioned above, it does not address other problems. In other words, if the generation point of the 180° width gate pulse is set near the firing advance angle γ = 0°, there may be differences in the characteristics of the thyristors used, errors in the adjustment of the RC time constant of the circuit device that controls the thyristors, etc. Due to temperature drift of other circuit elements, the 180° width gate pulse P′ _UY shown in Figure 2g is
The rear end of the 180° width gate pulse P′ _VX shown in h of the same figure.
There is a concern that an extremely serious accident could occur in which the front ends of the bridge thyristors overlap and all the thyristors connected to the single-phase bridge thyristor circuit become conductive, resulting in a short circuit on the power supply side. It was rare.

(Purpose) The present invention solves the drawbacks of the prior art described above, and aims to change the control advance angle γ of the next cycle from 175° (corresponding to control delay angle α = 5°) to
A 180° wide gate signal spanning 175° (corresponding to a control delay angle α = 5°) is used, and the rear end of the 180° wide gate signal in the previous cycle and the leading end of the 180° wide gate signal in the next cycle are used. An object of the present invention is to provide a single-phase bridge thyristor circuit that can reliably control conduction of a thyristor by preventing the thyristors from overlapping.

(Summary of the invention) The present invention has a control advance angle γ of 175° (control delay angle α
Generates gate phase signals A and B (herein referred to as A signal and B signal) with a width of 175° for each phase (U-Y, V-X) using a pulse signal with a width of 0° from = 5°). An AND signal C (referred to as C signal here) of the gate forbidden band signal of α = 0° to 5° and the U-phase synchronous signal, and an AND signal D (herein referred to as C signal) of the gate forbidden band signal of α = 0° to 5° ( A desired U-phase to Y-phase gate signal (herein referred to as D signal) is generated from the first flip-flop circuit which is set by the A signal and reset by the OR signal of the C signal and B signal. γ = 175° to 175° and a width of 180°), and the desired V phase to The rear end of the 180° wide gate signal of one phase (U-Y phase) overlaps the front end of the 180° wide gate signal of the other phase (V-X phase) so as to obtain a phase gate signal. It was made so that they would not match.

(Example) In the following, an example of the single-phase bridge thyristor circuit of the present invention will be described.

FIG. 3 shows a 180° width gate signal forming circuit which is a main part of an embodiment of the present invention, and FIG. 4 shows input and output waveforms of circuit elements constituting the circuit shown in FIG.

In FIG. 3, numeral 31 is a gate phase signal generating circuit that generates a pulse having a pulse width with a control advance angle γ of 175° to 0°.
The power supply voltage with the phase is input to a rectifier circuit (not shown), and the full-wave rectified voltage of the positive polarity U phase and V phase is input to the input terminal 4.
1 and control advance angle γ as shown in Figure 4d.
generates a 175° wide gate phase signal with a pulse width of 175° to 0°. 32 is an AND gate which is a first AND circuit, which receives the U-phase synchronization signal shown in FIG. 4b input to the input terminal 42 and the gate phase signal shown in FIG. The control advance angle γ shown in the figure f outputs a signal having a pulse width ranging from 175° to 0°. 33 is an AND gate which is a second AND circuit, and the U-phase synchronization signal shown in FIG. 4b input to the input terminal 42 and the input terminal 4
The control delay angle α input to 4 is inputted with the gate forbidden band signal shown in FIG. Outputs a series of pulse signals with pulse widths ranging from 0° to 5°. 34 is an AND gate which is a third AND circuit, into which the V-phase synchronization signal shown in FIG. 4c input to the terminal 43 and the gate phase signal shown in FIG. The control advance angle γ shown in Fig. h has a pulse width ranging from 175° to 0°, and outputs a signal whose phase is 180° different from the output signal of the AND gate 32 shown in Fig. F.
35 is an AND gate which is the fourth AND circuit,
The V-phase synchronization signal shown in FIG. 4c input to the terminal 43 and the gate prohibited band signal shown in FIG. The delay angle α has a pulse width ranging from 0° to 5°, and outputs a signal having a phase difference of 180° from the input signal of the AND gate 33 shown in g of the figure.

36 is an OR gate which is the first OR circuit;
The output of the AND gate 33 shown in Fig. 4g and the same Fig. 4h
The output of the AND gate 34 shown in FIG.
outputs a pulse signal with a width of 180° from 175° to a control advance angle γ of 175° in the next cycle. Reference numeral 37 denotes an OR gate which is a second OR circuit, into which the output of the AND gate 32 shown in FIG. 4 f and the output of the AND gate 35 shown in FIG. The control lead angle γ has a pulse width of 180° from 175° to the control lead angle γ of the next cycle of 175°, and the phase is 180° different from the phase of the pulse signal of the OR gate 36 shown in FIG. Outputs a pulse signal to

38 is input to the gate of the U-phase thyristor
For example, a JK flip-flop, which is a U-phase 180° wide gate signal generation circuit that generates a 180° wide gate signal,
The output of the AND gate 32 shown in FIG. _F is input to the set terminal S and set by the signal shown in _FIG. It is reset by the signal shown in . And flip-flop 38
The same figure applies even if the set signal shown in Figure 4 _l2 disappears.
l Since the current output state is maintained until the reset signal shown in ₁ is input, the control lead angle γ is a 180° pulse ranging from 175° to the control lead angle γ175° in the next cycle, as shown in m in the figure. Outputs a U-phase 180° wide gate signal.

39 is input to the gate of the V-phase thyristor
For example, a JK flip-flop, which is a V-phase 180° width gate signal generation circuit that generates a 180° width gate signal,
The output of the AND gate 34 shown in _{FIG .} It is reset by the signal shown in . For the flip-flop 39, for the same reason as described above, the control advance angle γ has a pulse width of 180° ranging from 175° to the control advance angle of 175° in the next cycle, and the U-phase Outputs a V-phase 180° width gate signal that has a 180° phase difference from the 180° width gate signal.

Next, the operation of the circuit having such a configuration will be explained.

The U-phase and V-phase synchronization signals shown in FIG. 4b and c are obtained from the AC power supply voltages of the U-phase and V-phase shown in FIG. is input to AND gates 32 and 33, and V
The phase synchronization signal is input to AND gates 34 and 35. The gate phase signal shown in FIG. 4d outputted from the gate phase signal generation circuit 31 is input to the AND gates 32 and 34, and the gate prohibited band signal shown in FIG. and 35 are input.

The AND gate 32 performs an AND operation between the U-phase synchronization signal shown in FIG. 4b and the gate phase signal shown in FIG. This is applied to the set terminal S of the flip-flop 38 and set as shown in _FIG . 37 as well.

The AND gate 33 performs the AND operation of the U-phase synchronization signal shown in FIG. 4b and the gate prohibited band signal shown in FIG. A signal is output and inputted to the OR gate 36.

The AND gate 34 performs an AND operation between the gate phase signal shown in FIG. 4 d and the V-phase synchronization signal shown in FIG. γ outputs a pulse signal with a pulse width ranging from 175° to 0°, inputs this to the OR gate 36, and controls the control advance angle γ shown in j in the same figure.
Control advance angle from 175° to 180° over 175° in the next cycle
A signal having a pulse width _of
At the same time as stopping the generation of the width gate signal, the output of the AND gate 34 is inputted to the set terminal S of the flip-flop 39, and set as shown in _n2 in the figure, and the control advance angle γ is set to 175 as shown in o in the figure. 3, the V phase 180° width gate signal is started to be generated.

The AND gate 35 performs an AND operation between the V-phase synchronization signal shown in FIG. 4c and the gate forbidden band signal shown in FIG. 4e, and has a control delay angle α shown in FIG. In addition, a pulse signal having a phase delay of 180° with respect to the output signal of the AND gate 33 shown in FIG.

The OR gate 37 takes the OR between the output of the AND gate 32 shown in FIG. 4 f and the output of the AND gate 35 shown in FIG.
A pulse signal with a width of 180° from 175° to the control advance angle γ175° of the next cycle is input to the reset terminal R of the flip-flop 39, and is reset as shown in _n1 in the same figure, and the V phase is set to 180° as shown in o in the same figure. At the same time as stopping the generation of the width gate signal, the signal from the AND gate 32 is applied to the set terminal S of the flip-flop 38, setting the flip-flop 38 which had been reset up to this point, and setting the U phase as shown in FIG.
Generates a 180° width gate signal.

The U-phase and V-phase 180° width gate signals generated in this manner are input to the thyristor gate of the single-phase pure bridge thyristor circuit to control its conduction.

The 180° width gate signal forming circuit constituting the main part of the present invention described above can be applied to a single-phase pure bridge thyristor circuit or a single-phase mixed bridge thyristor circuit, and the same effects can be achieved in such cases as well. be able to.

(Effects) As explained above, according to the present invention, the 180° width gate signal that controls the conduction of the thyristor of the single-phase bridge thyristor circuit is U-phase with the gate phase signal whose control advance angle γ is from 175° to 0°. A logical signal is generated by the phase signal, and an AND signal of the gate prohibited band signal with a control delay angle α of 0° to 5° and the U-phase synchronous signal, and a logical product signal of the V-phase synchronous signal and the control advance angle γ of 175°. It is obtained by stopping its generation by using the logical sum signal of the logical product signal and the gate phase signal of 0°.
The 180° width gate signal can be generated from a control lead angle γ of 175° to a control lead angle γ of 175° in the next cycle, and unlike the conventional device, the control lead angle γ is 175°.
The rear end of the 180° wide gate signal generated at =0° overlaps the front end of the 180° wide gate signal of the next cycle due to an adjustment error such as the RC time constant of the control circuit device or temperature drift. It is possible to reliably prevent the occurrence of a power supply short circuit by igniting the thyristor, and also to eliminate the occurrence of turn-off of the thyristor due to an external surge.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional single-phase pure bridge thyristor circuit, Fig. 2 is a diagram showing input/output waveforms, control pulses, and 180° width gate waveforms of the circuit shown in Fig. 1. Fig. 3 4 shows an embodiment of the single-phase bridge thyristor circuit of the present invention, FIG. 3 is a circuit diagram of a 180° width gate signal forming circuit which is the main part of the embodiment, and FIG. 4 is a waveform diagram showing input waveforms applied to the circuit shown in FIG. 3 and input/output waveforms of circuit elements constituting the circuit. FIG. In the figure, 31 is a gate phase signal generation circuit, 32,
33, 34, 35 are AND gates, 36, 37 are OR gates, 38, 39 are flip-flops, 4
Reference numeral 1 indicates a U-phase and V-phase full-wave rectified voltage input terminal, 42 a U-phase synchronous signal input terminal, 43 a V-phase synchronous signal input terminal, and 44 a gate forbidden band signal input terminal.

Claims (1)

[Claims] 1. A device that is equipped with a thyristor and applies desired DC power to a load, and has a U-phase synchronization signal and a control advance angle γ of 175° to 0° (corresponding to α = 5° to 180°). a first logical product circuit to which the gate phase signal of the U-phase synchronization signal and a gate forbidden band signal having a control delay angle α ranging from 0° to 5° are inputted; a product circuit; a third AND circuit to which the V-phase synchronization signal and the gate phase signal are input; a fourth AND circuit to which the V-phase synchronization signal and the gate forbidden band signal are input; a first OR circuit to which the outputs of the second AND circuit and the third AND circuit are input; and a first OR circuit to which the outputs of the first AND circuit and the fourth AND circuit are respectively input. a U-phase-Y-phase 180° radiation gate signal generation circuit that is set by the output of the first AND circuit and reset by the output of the first OR circuit; 1. A single-phase bridge thyristor circuit comprising a V-phase to