JPH0564457A - Dead time compensating method in inverter control - Google Patents

Dead time compensating method in inverter control

Info

Publication number
JPH0564457A
JPH0564457A JP3225449A JP22544991A JPH0564457A JP H0564457 A JPH0564457 A JP H0564457A JP 3225449 A JP3225449 A JP 3225449A JP 22544991 A JP22544991 A JP 22544991A JP H0564457 A JPH0564457 A JP H0564457A
Authority
JP
Japan
Prior art keywords
output voltage
voltage command
sine wave
dead time
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3225449A
Other languages
Japanese (ja)
Inventor
Koji Yamada
幸治 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP3225449A priority Critical patent/JPH0564457A/en
Publication of JPH0564457A publication Critical patent/JPH0564457A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To suppress torque ripple due to dead time in low frequency region by deciding the polarity of sine wave at the stage for combining two-phase sine wave output voltage command signals into a three-phase sine wave output voltage command signal and combining a required compensation component into the sine wave. CONSTITUTION:A voltage command V and a square voltage at the joint of resistors RA, RB are combined at a ratio of the resistances RB, RA to produce a compensated output voltage command V' which is then fed to a PWM comparator 4. The compensated output voltage command V' has such waveform as the sine wave of the output voltage command is superposed on a square wave obtained by eliminating the waveform distortion. Consequently, the compensation ratio of the resistor RB with respect to the output voltage command V has high effect on the output voltage command V close to zero whereas the effect is low for a high output voltage command V. According to the invention, torque ripple due to dead time can be suppressed in low frequency region.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、PWMインバータの制
御装置において出力側の短絡防止期間の影響を抑制する
インバータ制御におけるデッドタイム補償方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dead time compensation method in inverter control for suppressing the influence of a short circuit prevention period on the output side in a PWM inverter control device.

【0002】[0002]

【従来の技術】交流電動機を可変速駆動しようとする場
合には、PWMインバータが多く用いられている。この
場合、速度帰還ループなしに電動機を駆動しようとする
ときには、軽負荷時の特定周波数領域で電流のハンチン
グが生じやすくなり、制御不能となる可能性があるこ
と、大きなトルクリップルを生じ易いこと等の大きな問
題がある。
2. Description of the Related Art A PWM inverter is often used to drive an AC motor at a variable speed. In this case, when trying to drive the electric motor without the speed feedback loop, current hunting is likely to occur in a specific frequency region at light load, which may cause uncontrollability, and a large torque ripple is likely to occur. Have a big problem.

【0003】特に、低速駆動では、トルクリップルの影
響が大きくなり、有効可変速範囲は20対1程度の回転
数範囲となり、低速での振動を嫌う用途には適用できな
い。
In particular, in low speed driving, the effect of torque ripple becomes large, and the effective variable speed range becomes a rotation speed range of about 20 to 1, which cannot be applied to applications where vibration at low speed is disliked.

【0004】この原因は、図4に示すインバータ主回路
8を構成するパワースイッチング素子TU〜TZのON/
OFF動作の遅れがあり、各相u,v,wの直列に接続
されたスイッチング素子が同時に僅かな時間でもONす
ると、直流電源短絡を引き起こし、スイッチング素子破
壊を招く。このため各スイッチング素子のOFF状態を
ON状態にするスイッチング指令に遅れを持たせる必要
がある。このOFF状態からON状態への指令の遅れ時
間をデッドタイムと呼び、この影響で図5に示すように
出力電圧に波形歪を引き起こすことにある。
The cause of this is that the power switching elements T U to T Z forming the inverter main circuit 8 shown in FIG.
There is a delay in the OFF operation, and when the switching elements connected in series for each phase u, v, w are turned on at the same time for a short time, a DC power supply short circuit is caused and the switching elements are destroyed. Therefore, it is necessary to delay the switching command for turning the OFF state of each switching element into the ON state. The delay time of the command from the OFF state to the ON state is called dead time, and this influence causes waveform distortion in the output voltage as shown in FIG.

【0005】PWM方式を三角比較方式とした場合のデ
ッドタイムによる波形歪の電圧減少分電圧ΔVは、 ΔV=Ed * Td * Fc ただし、Ed:インバータ主回路直流電圧(V) Td:デッドタイム(S) Fc:三角波周波数(Hz) で示すことができる。
The voltage reduction amount ΔV of the waveform distortion due to the dead time when the PWM method is the triangular comparison method is ΔV = Ed * Td * Fc, where Ed: inverter main circuit DC voltage (V) Td: dead time ( S) Fc: can be represented by triangular wave frequency (Hz).

【0006】最近のPWMインバータは、低雑音化の観
点から、三角波周波数Fcを可聴領域(約10KHz)
より高く設定するものが増加しており、このスイッチン
グ周波数の増加も波形歪の問題を大きなものとしてい
る。
In the recent PWM inverter, the triangular wave frequency Fc is in the audible range (about 10 KHz) from the viewpoint of noise reduction.
The number set higher is increasing, and this increase in switching frequency also makes the problem of waveform distortion a big problem.

【0007】このようなインバータ装置で交流駆動機を
駆動すると、特に低周波領域での振動が多く、振動を嫌
う用途には適用できない。これを解決する方法として以
下の方式が使用されている。
When an AC drive is driven by such an inverter device, there are many vibrations, especially in the low frequency region, and it cannot be applied to applications where vibration is disliked. The following method is used as a method for solving this.

【0008】(1)電流制御ループを持たせ、交流電動
機に流す電流波形を制御することによって低速でのトル
クリップルを低減する方式。
(1) A method of reducing the torque ripple at low speed by providing a current control loop and controlling the waveform of the current flowing through the AC motor.

【0009】(2)出力電圧を検出し、電圧指令と比較
してスイッチング素子の制御信号を決定する電圧制御方
式。
(2) A voltage control system in which the output voltage is detected and compared with the voltage command to determine the control signal for the switching element.

【0010】(3)出力電圧指令信号の極性に応じて、
波形歪の電圧減少分電圧ΔVの補償信号を重畳に出力す
る方法、即ち、正弦波に電圧ΔVの方形波をバイアスと
して加えた図3に示す波形を電圧指令信号として用いる
方法。
(3) Depending on the polarity of the output voltage command signal,
A method of outputting a compensation signal of a voltage ΔV corresponding to a voltage reduction amount of waveform distortion in a superimposed manner, that is, a method of using a waveform shown in FIG.

【0011】[0011]

【発明が解決しようとする課題】上記従来(1),
(2)の方法は共にフィードバック制御を行っているの
で、検出方法と制御ゲインを適切なものに選択すること
により、振動面からみた特性は良好なものとなるが、コ
ストの上昇を引き起こす。
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Since both methods (2) perform feedback control, by selecting an appropriate detection method and control gain, the characteristics seen from the vibrating surface are good, but the cost is increased.

【0012】また(3)の方法は汎用のCPUを用いて
制御を行う場合、インバータのゲート制御信号までをC
PU内のプログラムで演算させるのは演算能力の制約が
大きい(高周波スイッチングになる程大きい)ため、C
PUでは正弦波の2相出力の位相を演算してD/A変換
して得た2相分の出力電圧指令vu*,vV*を図6に示
すように、外部のハードウエアである加算回路1で合成
し3相の電圧指令vu*,vV*,vW*を得て、これを
PWM変調用コンパレータ4U,4V,4Wで三角波vC
比較することによりゲート信号を得ている。
In the method (3), when control is performed using a general-purpose CPU, even the gate control signal of the inverter is C
Since the calculation capacity of the program in the PU is large (the higher the switching frequency, the larger)
In the PU, the output voltage commands v u *, v V * for the two phases obtained by calculating the phase of the two-phase output of the sine wave and performing D / A conversion are external hardware, as shown in FIG. The three-phase voltage commands v u *, v V *, v W * are obtained by combining in the adder circuit 1 and compared with the triangular wave v C by the PWM modulation comparators 4 U , 4 V , 4 W. You are getting a signal.

【0013】この場合、2相の出力電圧指令vU*,vV
*波形にデットタイムによる波形歪の電圧減小分電圧Δ
Vの波形を重畳して合成しても合成相の波形が図7に示
すように、元の波形とならないため、CPUでこの電圧
ΔV演形演算を行う場合にはD/A変換のハードウエア
を増設する必要が生じ、またCPU内の演算処理量の増
大につながる。
In this case, the two-phase output voltage commands v U *, v V
* Voltage reduction of waveform distortion due to dead time
Even if the waveform of V is superimposed and synthesized, the waveform of the synthesized phase does not become the original waveform as shown in FIG. 7. Therefore, when the CPU performs this voltage ΔV operation, the D / A conversion hardware is used. Need to be added, which leads to an increase in the amount of calculation processing in the CPU.

【0014】本発明は、従来のこのような問題点に鑑み
てなされたものであり、その目的とするところは、デッ
ドタイムによる低周波領域のトルクリップルをコストを
上昇させることなく低減させることができるインバータ
制御におけるデッドタイム補償方法を提供することにあ
る。
The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to reduce the torque ripple in the low frequency region due to the dead time without increasing the cost. It is to provide a dead time compensation method in inverter control that can be performed.

【0015】[0015]

【課題を解決するための手段】上記目的を達成するため
に、本発明におけるインバーター制御におけるデッドタ
イム補償方法は、出力電圧指令信号にデッドタイムに起
因する出力電圧減少分を指令信号と同極性で重畳させ、
この合成信号を出力電圧指令とすることによりデッドタ
イムの波形歪を補償するインバータ制御方法において、
2相分の正弦波出力電圧指令信号から3相の正弦波出力
電圧指令信号を合成した段階で、この正弦波の極性を判
定し、必要とする補償分をこの正弦波に合成するもので
ある。
In order to achieve the above object, a dead time compensating method in an inverter control according to the present invention uses an output voltage command signal in which the output voltage decrease due to the dead time has the same polarity as the command signal. Superimpose,
In the inverter control method for compensating for the waveform distortion of the dead time by using this composite signal as the output voltage command,
At the stage where the three-phase sine wave output voltage command signals are combined from the two-phase sine wave output voltage command signals, the polarity of this sine wave is determined and the necessary compensation component is combined with this sine wave. ..

【0016】[0016]

【作用】2相の出力電圧指令波形より3相の出力電圧指
令波形を得た後に、出力電圧指令信号の極性に応じて補
償信号を重畳して出力しているので、CPUの処理の増
大を伴わない。
Since the three-phase output voltage command waveform is obtained from the two-phase output voltage command waveform and the compensation signal is superimposed and output according to the polarity of the output voltage command signal, the processing of the CPU is increased. Not accompanied.

【0017】補償後の出力電圧指令における補償前の出
力電圧指令分に対する補償信号分の比率は、指令電圧が
零に近いときは大きく影響し、指令電圧が高いときには
影響が小さくなるので、デッドタイムによる波形歪を補
償することができる。
The ratio of the compensation signal component to the output voltage command component before compensation in the output voltage command after compensation has a great influence when the command voltage is close to zero, and has a small influence when the command voltage is high. It is possible to compensate the waveform distortion due to.

【0018】[0018]

【実施例】図1は本発明方法を施した汎用CPU制御に
よるPWMインバータ装置を示し、図2は補償後の出力
電圧指令作成回路の1相分を示す。
1 shows a general-purpose CPU-controlled PWM inverter device to which the method of the present invention is applied, and FIG. 2 shows one phase of an output voltage command generating circuit after compensation.

【0019】図1において、vU*,vV*は図示省略の
CPUで3相正弦波のU,V相出力の位相を演算してD
/A変換して得たU,V相の電圧指令、vW*はこの2
相分のデータを加算回路1で合成したW相の電圧指令、
U,2V,2Wは電圧指令vU*,vV*,vW*から補償
後の出力電圧指令を作りPWM変調用コンパレータ
U,4V,4Wに出力する補償後の出力電圧指令作成回
路である。なお、図中5は三角波発生回路6U,6V,6
Wはヒステリシスコンパレータ、7は短絡防止時間作成
・ベースアンプ回路、8はインバータ主回路を示す。各
相の補償後の出力電圧指令作回路2は図2に示すよう
に、各相の出力電圧指令v*(正弦波)が入力し、この
正弦波の波形と同極性の方形波電圧VSを出力するゼロ
クロスコンパレータ3と、出力電圧指令v*とゼロクロ
スコンパレータ3からの方形波電圧VSとを比較する抵
抗RA,RB回路からなり、抵抗RAとRBの接続点から電
圧指令v*と方形波電圧VSを抵抗RBとRAの比で合成
した補正後の出力電圧指令v′*がPWM変調用コンパ
レータ4に出力される。この抵抗RA,RBは下記の関係
により与える。
In FIG. 1, v U *, v V * is a CPU (not shown) that calculates the phases of U and V phase outputs of a three-phase sine wave, and D
U / V phase voltage command obtained by A / A conversion, v W *
A voltage command for the W phase, which is obtained by synthesizing the data for the phases in the adding circuit 1,
2 U , 2 V , 2 W is the output after compensation, which creates the output voltage command after compensation from the voltage commands v U *, v V *, v W * and outputs it to the PWM modulation comparators 4 U , 4 V , 4 W. It is a voltage command generation circuit. In the drawing, 5 is a triangular wave generating circuit 6 U, 6 V, 6
W is a hysteresis comparator, 7 is a short circuit prevention time creation / base amplifier circuit, and 8 is an inverter main circuit. As shown in FIG. 2, the output voltage command generation circuit 2 after compensation of each phase receives the output voltage command v * (sine wave) of each phase, and a square wave voltage V S having the same polarity as the waveform of this sine wave. And a resistor R A , R B circuit for comparing the output voltage command v * with the square wave voltage V S from the zero-cross comparator 3, and a voltage command from the connection point of the resistors R A and R B. The corrected output voltage command v ′ * obtained by combining v * and the square wave voltage V S with the ratio of the resistors R B and R A is output to the PWM modulation comparator 4. The resistances R A and R B are given by the following relationship.

【0020】[0020]

【数1】 [Equation 1]

【0021】補償後の出力電圧指令v′*の波形は図3
に示すような出力電圧指令vの正弦波と電圧△Vの方形
波を重畳した波形となる。このため、出力電圧指令v*
に対する抵抗RBからの補償値の比率は、出力電圧指令
が零に近いときは大きく影響し、出力電圧指令が高いと
きは影響が小さくなるので、デッドタイムによる出力電
圧の波形歪は改善される。
The waveform of the output voltage command v '* after compensation is shown in FIG.
The waveform is such that the sine wave of the output voltage command v and the square wave of the voltage ΔV are superimposed as shown in FIG. Therefore, the output voltage command v *
The ratio of the compensation value from the resistor R B to ## EQU1 ## has a large effect when the output voltage command is close to zero, and has a small effect when the output voltage command is high, so the waveform distortion of the output voltage due to dead time is improved. ..

【0022】[0022]

【発明の効果】本発明は、上述のとおり構成されている
ので、次に記載する効果を奏する。
Since the present invention is configured as described above, it has the following effects.

【0023】(1)コスト上昇を殆んど伴うことなく、
またCPUの処理の増大を伴うことなく、デッドタイム
による低周波領域のトルクリップルを低減させることが
できる。
(1) With almost no increase in cost,
Further, it is possible to reduce the torque ripple in the low frequency region due to the dead time without increasing the processing of the CPU.

【0024】(2)低周波領域での制御安定度が高くな
るため、従来1/20程度の回転数範囲において大きな
回転むらを生じていたものが、1/200程度の回転数
範囲でもほぼ滑らかな回転を得ることが可能になる。
(2) Since the control stability in the low frequency region is high, a large rotational unevenness has conventionally been generated in the rotational speed range of about 1/20, but it is almost smooth even in the rotational speed range of about 1/200. It is possible to obtain a proper rotation.

【0025】(3)フィードバックループを使用しない
ので検出回路やフィードバック制御回路が不要となり信
頼性の向上が図れる。
(3) Since the feedback loop is not used, the detection circuit and the feedback control circuit are unnecessary, and the reliability can be improved.

【0026】(4)インバータの適用全周波数の領域で
一定の補償分を正弦波指令に重畳しているので、インバ
ータを低周波数(低電圧)にて運転した場合に補償量が
大きく影響し、高周波数(高電圧)にて運転したときに
は補償量の影響が殆んどなくなり、トルクリップルの低
減等低周波数領域で動作し、高周波では誤動作の原因と
はならない。
(4) Application of Inverter Since a constant compensation component is superimposed on the sine wave command in the range of all frequencies, the compensation amount greatly affects when the inverter is operated at a low frequency (low voltage), When operated at high frequency (high voltage), the influence of the compensation amount is almost eliminated, it operates in the low frequency region such as reduction of torque ripple, and it does not cause malfunction at high frequency.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例にかかるインバータ装置を示すブロック
回路図。
FIG. 1 is a block circuit diagram showing an inverter device according to an embodiment.

【図2】補償後の出力電圧指令作成回路を示すブロック
回路図。
FIG. 2 is a block circuit diagram showing an output voltage command generation circuit after compensation.

【図3】補償後の出力電圧指令を示す波形図。FIG. 3 is a waveform diagram showing an output voltage command after compensation.

【図4】インバータ主回路を示す回路図。FIG. 4 is a circuit diagram showing an inverter main circuit.

【図5】インバータ出力を示す波形図。FIG. 5 is a waveform diagram showing an inverter output.

【図6】従来2相3相合成した出力電圧指令によるイン
バータ装置を示すブロック回路図。
FIG. 6 is a block circuit diagram showing an inverter device according to a conventional two-phase three-phase combined output voltage command.

【図7】3相合成前に補正した場合の出力電圧指令の波
形図。
FIG. 7 is a waveform diagram of an output voltage command when correction is performed before three-phase synthesis.

【符号の説明】[Explanation of symbols]

1…加算回路、2,2U,2V,2W…補償後の出力電圧
指令作成回路、3…ゼロクロスコンパレータ、4U
V,4W…PWM用コンパレータ、5…三角波発生回
路、6U,6V,6W…ヒステリシスコンパレータ、7…
短絡防止時間作成・ベースアンプ回路、8…インバータ
主回路、TU〜TZ…パワースイッチング素子、M…交流
電動機、RA,RB…抵抗。
1 ... Adder circuit, 2, 2 U , 2 V , 2 W ... Compensated output voltage command generation circuit, 3 ... Zero cross comparator, 4 U ,
4 V , 4 W ... PWM comparator, 5 ... Triangular wave generation circuit, 6 U , 6 V , 6 W ... Hysteresis comparator, 7 ...
Dead time creates based amplifier circuit, 8 ... inverter main circuit, T U through T Z ... power switching elements, M ... AC motor, R A, R B ... resistance.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 出力電圧指令信号にデッドタイムに起因
する出力電圧減少分を指令信号と同極性で重畳させ、こ
の合成信号を出力電圧指令とすることによりデッドタイ
ムの波形歪を補償するインバータ制御方法において、2
相分の正弦波出力電圧指令信号から3相の正弦波出力電
圧指令信号を合成した段階で、この正弦波の極性を判定
し、必要とする補償分をこの正弦波に合成することを特
徴とするインバータ制御におけるデッドタイム補償方
法。
1. An inverter control for compensating for the waveform distortion of dead time by superimposing an output voltage decrease caused by dead time on the output voltage command signal with the same polarity as the command signal, and using the composite signal as an output voltage command. In the method 2
The present invention is characterized in that the polarity of this sine wave is determined at the stage where the three-phase sine wave output voltage command signal is synthesized from the phase sine wave output voltage command signal, and the necessary compensation component is synthesized into this sine wave. Dead time compensation method for inverter control.
JP3225449A 1991-09-05 1991-09-05 Dead time compensating method in inverter control Pending JPH0564457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3225449A JPH0564457A (en) 1991-09-05 1991-09-05 Dead time compensating method in inverter control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3225449A JPH0564457A (en) 1991-09-05 1991-09-05 Dead time compensating method in inverter control

Publications (1)

Publication Number Publication Date
JPH0564457A true JPH0564457A (en) 1993-03-12

Family

ID=16829530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3225449A Pending JPH0564457A (en) 1991-09-05 1991-09-05 Dead time compensating method in inverter control

Country Status (1)

Country Link
JP (1) JPH0564457A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1814215A1 (en) 2006-01-30 2007-08-01 Hitachi, Ltd. Electric power converter and motor driving system
JP2017011800A (en) * 2015-06-17 2017-01-12 シャープ株式会社 Power conditioner and control method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1814215A1 (en) 2006-01-30 2007-08-01 Hitachi, Ltd. Electric power converter and motor driving system
US7541769B2 (en) 2006-01-30 2009-06-02 Hitachi, Ltd. Electric power converter and motor driving system
JP2017011800A (en) * 2015-06-17 2017-01-12 シャープ株式会社 Power conditioner and control method

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