JPH056408A - Multi-stage logic circuit synthesizing device - Google Patents

Abstract

PURPOSE:To provide a multi-stage processing device in a fixed delay time in a device which generates automatically a desired multi-stage logic circuit based on the circuit logical information obtained through a logical formula, a truth table, etc. CONSTITUTION:This device is provided with an input means 1 to input an initial circuit serving as the logical information together with a main storage means 2, and a compiling means 3 which converts the initial circuit into a secondary circuit of an internal data form, a logical optimizing means 4 while deletes the logically redundant parts by a 2-stage logical simplification algorithm and a multi-stage processing means 5 which detects a common partial circuit out of the circuit in consideration of the circuit area and the delay time and performs the binding processing through the common part. Further, a parameter setting means 6 is connected to the means 5 and fetches the largest input number per gate. Then a real circuit conversion means 9 converts a multi-stage logic circuit into a real circuit 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for automatically converting a circuit described in the form of a logical expression, a truth table or the like into a circuit of an actual technology in logic synthesis, and particularly to a logical expression,
The present invention relates to a multi-stage logic circuit synthesizer that generates a desired multi-stage logic circuit from logic information of a circuit given by a truth table or the like.

[0002]

2. Description of the Related Art Generally, the following is known as a multi-stage logic circuit synthesizer for synthesizing a multi-stage logic circuit from given logic information. This will be described with reference to FIG.

An input unit 20 for inputting logical information, a main storage unit 21, a compiling unit 22 for converting the input logical information into an internal data format and expanding it in the main storage unit 21, and a two-stage logic simplification algorithm. A logical optimizing unit 23 for removing a redundant portion, a multi-stage processing unit 24 for concluding a common portion of the circuit portion in consideration of a circuit area and a delay time by using a gate evaluation function based on a 2-input gate, There is known a multi-stage logic circuit synthesizing device including a real circuit conversion unit 25 that converts the multi-staged internal format logic circuit into a real circuit 26.

[0004]

However, in the above-described multi-stage logic circuit synthesizer, in the process of performing the multi-stage processing,
Since a fixed pattern is grouped based on two inputs, the error is large depending on the technology actually used, and there is a problem that the quality of the combined circuit is deteriorated.

Here, as a parameter for measuring quality,
The area and delay time of the generated circuit are used as main parameters. Actually, the processing process for reducing the circuit area is called multistage processing.

When the multi-stage processing is performed in the circuit synthesis process, the circuit area is reduced, but the in-phase logic circuit is
The gates of ND and OR are overlapped in multiple stages, which increases the delay time.

The present invention has been made in view of the above problems, and it is a technical object to provide an apparatus capable of performing multistage processing in order to shorten the delay time, that is, within a certain delay time. .

[0008]

In order to solve the above problems, the present invention is as follows. This will be described based on the principle diagram of FIG.

In a multi-stage logic circuit synthesizer for generating a desired multi-stage logic circuit based on the logic information of the circuit given in the form of a logic formula and a truth table, an input means 1 for inputting an initial circuit which is logic information, and a main A storage means 2, a compile means 3 for converting the logical circuit into a secondary circuit of an internal data format and expanding it in the main storage means 2, and a two-stage logic simplification algorithm for the secondary circuit. And a logic optimizing means 4 for removing a logically redundant part, and a multi-stage for detecting a common part circuit in the circuit in consideration of a circuit area and a delay time and performing a squeezing process by the common part. The processing means 5, the parameter setting means 6 which is connected to the multistage processing means 5 and takes in the maximum number of inputs per gate, and the multistage logic circuit are the actual circuits 10.
And an actual circuit converting means 9 for converting into
The multistage processing unit 5 uses a gate number evaluation function 7 and a gate stage number evaluation function 8 which have the maximum number of inputs per gate set by the parameter setting unit 6 as a parameter,
A multi-stage logic circuit synthesizing device is characterized in that the number of gates and the maximum number of gate stages are evaluated, and based on the evaluation result, the common partial circuits are grouped.

When a plurality of common partial circuits are detected in the secondary circuit, the multistage processing means 5 evaluates the number of gates and the number of gate stages for each of the common partial circuits to determine which common part. It is possible to select whether to tie out with.

[0011]

According to the present invention, a parameter setting unit for setting the maximum number of inputs per gate is added, and the number of gates and the maximum number of gate stages are evaluated by performing the evaluation using the number-of-gates evaluation function in addition to the number-of-gates evaluation function. It is possible to carry out the accurate indexing and the multistage processing based on the indexing result.

[0012]

Embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing the configuration of the multi-stage logic circuit synthesizer in this embodiment.

The multi-stage logic circuit synthesizer according to the present embodiment has an input section 11, a main storage section 12, and a compiling section 13.
And a logic optimizing unit 14, a multistage processing unit 15, a parameter setting unit 16, and an actual circuit converting unit 10.

The input unit 11 is a device for incorporating an initial circuit in the form of a logical expression and a truth table into this device. The compiling unit 13 stores the initial circuit input from the input unit 11, that is, information in the form of a logical expression or a truth table,
This is a device for converting into a secondary circuit 12a of a processing format in this device.

The logic optimizing unit 14 is a device for removing a logically redundant portion of the secondary circuit 12a by using a well-known two-stage logic simplification algorithm.
The multistage processing unit 15 detects a common partial circuit of a circuit part using a gate evaluation function in consideration of a circuit area and a delay time of a logic circuit to be generated, and performs a bundling by the common partial circuit. Is.

The parameter setting device 16 sets the number of inputs per gate within the range of the maximum number of inputs per gate, evaluates the number of gate stages according to the number of inputs, and determines the maximum number of gate stages. It is a device.

The actual circuit conversion unit 19 is a device for converting the multistage logic circuit 12c into the actual circuit 10. here,
In this device, the circuit area is evaluated by the number of gates, and the delay time is evaluated by the number of gate stages. That is, the number of gates is evaluated by the number-of-gates evaluation function 17, and the number of gates is evaluated by the number-of-gates evaluation function 18.

The gate stage number evaluation function 18 is L (n, N) = where n is the number of inputs of the gate of interest and N is the maximum number of inputs per gate (this value is set by the parameter setting unit). 0 (0 ≦ n <2) or L (n, N) = [log _N (n−1)] + 1 (n ≧ 2) ... Equation (1). However, [X] is the maximum integer not exceeding X.

Further, the maximum number of gate stages when squeezing is performed by a certain common partial circuit is D = max (the maximum number of gate stages before squeezing by the common partial circuit, the path affected by the squeezing by the common partial circuit) The maximum number of gate stages of ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ given by equation (2). The formula (1) is used to calculate the number of gate stages in each term of the formula (2).

The processing steps of this apparatus will be described below with reference to specific examples. As an initial circuit, y = a ・ b ・ c ・ e ^* + b ・ c ・ d ・ e ・ f ^*・ g + a ・
Suppose b, c, d, e, and f ^* are given.

Here, the mark " ^* " means inversion. FIG. 3 shows a circuit 12b in which the initial circuit is converted into a secondary circuit 12a of a processing format in the apparatus by the compiling unit 13 and a logically redundant part is eliminated by the logic optimum lower part 14.

Here, when the parameter setting unit 16 substitutes the maximum number of inputs of 2 for the circuit 12b and expands it, the number of gates becomes 15 and the number of gate stages becomes 5. This is shown in FIG.

When the maximum number of inputs per gate is 4, the number of gates is 6 and the number of gate stages is 3. This is shown in FIG. The common part of the initial circuit shown in FIG. 3 is p = a ^* b ^* + b ^* g q = c ^* d ^* e ^* f ^* .

Therefore, in the present apparatus, the parameter setting unit 16 sets the maximum number of inputs per gate (15a in FIG. 2), and the multistage processing unit 15 sets the gate stage number evaluation function based on the maximum number of inputs. The maximum number of gate stages is determined by 18 (15b in FIG. 2).

A case in which the common parts p and q are respectively squeezed out will be described with reference to tables and drawings. The common part p is (2), (3),
(4), and q is a common part that affects (2) and (3) in FIG. Here, FIG. 11 shows a common partial circuit p,
FIG. 13 is a table diagram of the results of calculating the maximum number of gate stages and the number of gate reductions when the values are grouped with q and q for the case of N = 2 and N = 4 (15c in FIG. 2).

For example, when N = 2 and bound with p,
The maximum number of gate stages is: D _p = max (maximum number of gate stages in initial circuit, maximum number of gate stages in path through p) = max {{(2) (or (3)) → (4) number of gate stages}, {( 26) (or (27)) → (28) → (29) → (31) number of gate stages}} = max ((L (6,2) + L (3,2)),
(L (2,2) + L (2,2) + L (5,2) + L
(2,2))) = max ((3 + 2), (1 + 1 + 3 + 1)) = max (5,6) = 6.

FIG. 6 shows a result obtained by wrapping the initial circuit of FIG. 3 by p, that is, y = a.b.c.e ^* + c.d.e.f ^* .pp p = a.b ^* + b.g Is a circuit diagram.

Now, if the constraint on the maximum number of gate stages of the logic circuit to be synthesized is set to 5 stages or less, from FIG. 11 and FIG.
In the case of N = 2 (FIG. 7), the number of gate stages becomes 6, so it is judged that the number of gates can be reduced, but it is impossible to group them.

Further, N = 4 with respect to the case of N = 2.
In the case of (Fig. 8), when pegging with p is performed,
Since the number of gate stages is 5, it is possible to group them. On the other hand, FIG. 9 shows a result of extracting the initial circuit of FIG. 3 by q, that is, y = a ^* b ^* c ^* e ^* + a ^* b ^** q + b ^* g ^* q q = c ^* d ^* ef. ^* Is a circuit diagram.

Similarly to the case of p, from FIG. 11 and FIG. 9, when N = 2 (FIG. 10), the number of gate stages is 6, and the squeezing is impossible. Then, in the case of N = 4 (similar to FIG. 9), the number of gate stages is 3, and the number of reductions is 1 to enable squeezing.

Here, in consideration of the above, the multistage processing unit 15 carries out squeezing with q, which has a large reduction number when N = 4 that can be squeezed. As described above, the value of N set by the parameter setting unit 16 affects the generated multi-stage logic circuit. Therefore, the maximum input number N of the basic gates is set as a parameter depending on the circuit technology at the time of conversion into the actual circuit 10. By setting with the setting unit 16, it is possible to generate a circuit with a small number of gates and a small number of gate stages, and thus the actual circuit conversion unit 19 synthesizes the logic circuit as the actual circuit 10.

[0032]

Therefore, according to the present invention, the number of gates and the maximum number of gate stages are evaluated based on the maximum number of inputs per gate in the process of performing the multi-stage processing, and the circuit area is smaller and the delay is smaller. It is possible to generate a circuit with a short time.

Therefore, the circuit quality of the circuit converted into the actual circuit can be controlled more accurately.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram showing the configuration of a multi-stage logic circuit synthesis device according to this embodiment.

FIG. 3 is a circuit diagram of a secondary circuit

FIG. 4 is a circuit diagram when a secondary circuit is realized with two input gates.

FIG. 5 is a circuit diagram when a secondary circuit is realized with four input gates.

FIG. 6 is a circuit diagram of a multistage logic circuit in which a secondary circuit is grouped with p.

FIG. 7 is a circuit diagram when the circuit of FIG. 6 is realized by a 2-input gate.

FIG. 8 is a circuit diagram when the circuit of FIG. 6 is realized by a 4-input gate.

9 is a circuit diagram of a multi-stage logic circuit in which the circuit of FIG. 6 is grouped by q.

FIG. 10 is a circuit diagram when the circuit of FIG. 9 is realized by a 2-input gate.

11 is a table of the maximum number of gate stages and the number of gate reductions when the common partial circuits p and q are grouped in the circuit of FIG.

FIG. 12 is a block diagram of a conventional multi-stage logic circuit synthesizer.

[Explanation of symbols]

1 ... Input means 2 ... Main memory means 3. Compile means 4 .. Logic optimization means 5 ... Multi-stage processing means 6 ... Parameter setting means 7. Gate number evaluation function 8 ... Gate stage number evaluation function 9 ... Actual circuit conversion means 10 ... Actual circuit 11 ... Input section 12 ... Main memory 13-Compile section 14 ... Logic optimization unit 15 ... Multi-stage processing unit 16 ... Parameter setting section 17 ... Gate number evaluation function 18 ... Gate level evaluation function ..Actual circuit conversion unit

Claims (2)

[Claims] 1. A multistage logic circuit synthesizer for generating a desired multistage logic circuit based on logic information of a circuit given in the form of a logical expression and a truth table, input means (1) for inputting an initial circuit which is logical information. ), A main memory means (2), a compiling means (3) for converting the initial circuit into a secondary circuit in an internal data format and expanding the secondary circuit in the main memory means (2), and the secondary circuit. A logic optimizing means (4) for removing a logically redundant part by a two-step logic simplification algorithm, and a common part circuit in the circuit is detected in consideration of a circuit area and a delay time; A multi-stage processing means (5) for performing a binding process by the common part,
A parameter setting means (6) which is connected to the multistage processing means (5) and takes in the maximum number of inputs per gate, and a real circuit conversion means (conversion of the multistage logic circuit into a real circuit (10) ( 9) and the multistage processing means (5)
Evaluates the number of gates and the number of gate stages by a gate number evaluation function (7) and a gate stage number evaluation function (8) having the maximum number of inputs per gate set by the parameter setting means (6) as a parameter, A multi-stage logic circuit synthesis device, characterized in that a common part is extracted based on an evaluation result. 2. The multistage processing means (5) evaluates the number of gates and the number of gate stages for each of the common partial circuits when a plurality of common partial circuits are detected in the secondary circuit. 2. The multi-stage logic circuit synthesizer according to claim 1, wherein it is possible to select whether to perform squeezing at a common portion.