JPH04282770A - Device for synthesizing multistage logical circuit - Google Patents

Abstract

PURPOSE:To form a multistage logical circuit by evaluating the synthesis of the multistage logical circuit by an input gate having the optional number of inputs in a multistage circuit synthesizing device. CONSTITUTION:The multistage logical circuit synthesizing device for forming a required multistage logical circuit based upon circuit logical information applied by a logical expression, a truth table, etc., is constituted of an input part 1 for inputting the logical information, a main storage device 2, a compiling part 3 for converting inputted logical information into an internal data format and developing the converted result in a main storage device, a logical optimizing part 4 for removing a redundant part by two-stage logical simplified algorithm, multistaging processing part 5 for extracting the common part of circuit parts by using a gate evaluation function in consideration of a circuit area and a delay time, a parameter setting part 6 connected to the processing part 5 to input the maximum number of inputs per gate to be used for the gate evaluation function, and a real circuit conversion part 7 for converting a multistaged logical circuit into a real circuit 8.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-stage logic circuit synthesis apparatus, and more particularly to a multi-stage logic circuit synthesis apparatus for generating a desired multi-stage logic circuit from circuit logic information given by logical formulas, truth tables, etc.

0002

2. Description of the Related Art Generally, there is a multi-stage logic circuit synthesis apparatus for synthesizing a multi-stage logic circuit from given logic information, which has the following configuration. As shown in FIG. 6, this consists of an input section 41 that inputs logical information, a main memory 42, and a compile section 43 that converts the input logical information into an internal data format and develops it in the main memory. a logic optimization unit 44 that removes redundant parts using a stage logic simplification algorithm;
A multi-stage processing unit 45 uses a gate evaluation function based on two-input gates to divide common parts of circuit parts in consideration of circuit area and delay time, and a multi-stage logic circuit is integrated into an actual circuit 4.
7, and a real circuit converting section 56 for converting into 7.

0003

[Problem to be solved by the invention] By the way, in such a conventional multi-stage logic circuit synthesis device, the multi-stage processing section 45 performs fixed grouping based on two input gates. Therefore, there is a problem that the error can be large depending on the technology actually used.

[0004] In the case of CMOS devices, the cell size increases approximately in proportion to the number of inputs, so if you evaluate it in units of 2-input gates and increase the number of stages, the number of gates (cell size) after technology mapping can be reduced. There is not much error between them.

However, when using a technology in which up to 4 inputs are realized using cells of the same size, for example, it is not possible to obtain good results even if technology mapping is performed using multistage results evaluated in units of 2-input gates. You can't get it.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a multistage logic circuit synthesis device that can perform evaluation using input gates having an arbitrary number of inputs and can be multistaged.

[0007]

[Means for Solving the Problems] In the present invention, the means for solving the above problems is as shown in FIG. A multi-stage logic circuit synthesis device that generates
An input unit 1 that inputs logical information, a main memory 2, a compile unit 3 that converts the input logical information into an internal data format and expands it to the main memory, and a two-stage logic simplification algorithm that removes redundant parts. A logic optimization unit 4 that performs gate evaluation; A parameter setting unit 6 that inputs the maximum number of inputs per gate used for a function, and a real circuit conversion unit 7 that converts a multistage logic circuit into a real circuit 8.
It is composed of

[0008]

[Operation] According to the present invention, since the maximum number of inputs per gate used in the gate evaluation function is input from the parameter input section to the multistage processing section as a parameter, the maximum number of inputs per gate used in the gate evaluation function is inputted to the multistage processing section. It is possible to perform optimization processing according to the desired circuit technology.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a multi-stage logic circuit synthesis apparatus according to the present invention will be described with reference to the drawings. 1 to 5 show an embodiment of a multi-stage logic circuit synthesis apparatus according to the present invention.

In this embodiment, the multi-stage logic circuit synthesis apparatus includes an input section 1 for inputting logic information, a main memory device 2, and a compiler for converting the input logic information into an internal data format and developing it in the main memory device. 3, a logic optimization unit 4 that removes redundant parts using a two-stage logic simplification algorithm, and a multistage processing unit that uses a gate evaluation function to divide common parts of circuit parts in consideration of circuit area and delay time. 5, a parameter setting unit 6 which is connected to the multi-stage processing unit 5 and inputs the maximum number of inputs per gate used for the gate evaluation function, and a real circuit conversion unit which converts the multi-stage logic circuit into an actual circuit 8. It consists of 7.

[0011] The initial circuit given in the form of logical formulas and truth tables inputted from the input section is converted into an internal data format by the compiling section and expanded into the main memory. The logic optimization unit that incorporates this internal data removes logically redundant parts using a known two-stage logic simplification algorithm.

Next, the multi-stage processing section finds a common partial circuit in the circuit, taking into account the circuit area and delay time, and performs grouping based on this. At this time, in order to determine which common partial circuit should be divided, the number of gates to be reduced in each common partial circuit existing in the circuit is determined.

In this embodiment, the number of gates to be reduced is calculated using a known gate evaluation function that calculates the number of gates to be reduced by inputting the maximum number of inputs per gate from the parameter setting section. As a result, for actual circuit conversion to any circuit technology,
It is assumed that an optimal circuit can be generated.

Here, in the gate evaluation function, n is the number of inputs of the gate of interest, and N is 1 input from the parameter setting section.
Assuming the maximum number of inputs per gate, G(n.N) = (n+(N-3))/(N-1)...Equation 1
is given by However, n≧2 and N≧2.

For example, when n=10 and N=4, the gate evaluation function becomes G(10,4)=3.

[0016] Furthermore, the number of gates to be reduced when a certain common subcircuit is grouped is M = (the number of gates before grouping in the part affected by the grouping by the common subcircuit) - (the number of gates before grouping in the part affected by the grouping by the common subcircuit). (number of gates added) is given by Equation 2. Note that to calculate the number of gates for each term in Equation 2, Equation 1 is used.

Next, this will be explained using a specific example. As the initial circuit, Y=a・b・c・e* +b・c・d・e・f* ・g
Suppose that +a, b*, c, d, e, f* are given. However, "*" means inversion.

If this is expressed in a logic circuit, as shown in FIG. The second AND gate 12, the third AND gate 13 inputting a, b*, c, d, e, f*, and the three outputs of the first to third AND gates 11, 12, 13. This can be realized with one OR gate 14 as input. If this initial circuit is implemented using 2-input gates, 15 gates will be required, and if implemented using 4-input gates, 6 gates will be required.

Therefore, the number of gates is reduced by optimizing the logic. The common part for this initial circuit is p=a・b*
There is +b・g q=c・d・e・f*.

Here, p corresponds to the first to third gates 11, 12, 13 in FIG. 2, and q corresponds to the second and third gates 12, 13.
This is a common partial circuit that affects 13. Table 1 shows the reduction number of gates for two common subcircuits p and q, N=2, N=4.
It shows the results obtained for the case of

[0021]

[Table 1]

For example, when N=2 for p, the number of gates to be reduced is Mp = (number of gates of AND gate 12 +
Number of gates of AND gate 13 + O
Number of gates of Agate 14)
−(Number of gates of p + Number of gates of gates that take p as input + Gate of gates that take output of gate that takes p as input
number) = (G(6,2)+G(6,2)
+ G(3,2)) −(G
(2,2)×3+G(5,2)+G(2,2))
=(5+5+2)-(3+4+1)
It can be calculated as =4.

From Table 1, when N=2, p and N=
In the case of 4, it can be seen that the number of gates can be reduced by dividing by q.

The results of dividing the initial circuit in FIG. 2 into p and q are y=a, b, c, e* + c, d, e, f*, pp=, respectively.
a・b* +b・g and y=a・b・c・e* +a・b* ・q+b・g・q
q=c・d・e・f*. These are shown in circuit diagrams in FIGS. 3 and 4, respectively.

In FIG. 3, the circuit includes an AND gate 21 to which a and b* are input, an AND gate 22 to which b and g are input, an OR gate 23 to which the outputs of both of these AND gates are input, and an OR gate 23 to which the outputs of both AND gates are input. The outputs p, c, d
, e, f*, and the AND gate 24 which inputs a, b,
It consists of an AND gate 25 to which c and e* are input, and an OR gate 26 to which the outputs of both AND gates are input. If this circuit is implemented using 2-input gates, there will be 11 gates, and if it is implemented using 4-input gates, there will be 7 gates.

The circuit shown in FIG. 4 has c, d, e, f*
an AND gate 31 that inputs the output of the AND gate 31, an AND gate that inputs the output of this AND gate 31, b, g, and an AND gate 3 that inputs the output of the AND gate 31, a, b*
3, and the AND gate 34 that inputs a, b, c, e*
and an OR gate 35 into which the outputs of the three AND gates 32, 33, and 34 are input, and when realized with 2 input gates, there are 12 gates, and when realized with 4 input gates, there are 5 gates. Become.

In the case of N=2, that is, in FIG. 3, r=a·b·e* +d·e·f*·p exists as a common partial circuit. When calculating the reduction number of gates for r in the same way as for p, Mr = (number of gates of AND gate 24 +
Number of gates of AND gate 25 + O
Number of gates of Agate 26)
−(Gate of r + Number of gates whose input is r + Number of gates whose input is the output of the gate whose input is r
=(G(5,2)+G(4,2)+G(2,
2) −((G(4,2)+G
(3,2)+G(2,2))
+G(2,2)+0) =(4+3
+1)-(6+1+0)=1. FIG. 5 shows this in the form of a circuit diagram.

This circuit consists of an AND gate 31 to which a and b* are input, an AND gate 32 to which b and g are input,
An OR gate 33 inputs the outputs of both AND gates 31 and 32, and outputs p, e, d, f* of this OR gate 33.
an AND gate 34 that inputs a, b, e*, an OR gate 36 that inputs the outputs of both AND gates 34 and 35, and an AND gate 36 that inputs a, b, e*.
and an AND gate 37 into which the outputs r and c of are input, and if realized with two input gates, there will be 10 gates, and if realized with four gates, there will be seven gates.

Therefore, in order to realize the initial circuit shown in FIG. 2 using a two-input gate circuit technology, the circuit shown in FIG. It can be seen that this can be realized using the minimum number of gates, 5, according to the circuit shown in FIG.

As described above, according to this embodiment, the multi-stage logic circuit generated changes depending on the value N set in the parameter setting section, so it is only necessary to give the maximum number of basic gates in the circuit technology of the actual circuit as N. Then, it is possible to generate an optimal multi-stage logic circuit based on the circuit technology of the actual circuit.

[0030]

[Effects of the Invention] As explained above, according to the present invention,
Since the multi-stage processing section of the multi-stage logic circuit synthesis device is equipped with a parameter setting section for inputting the maximum number of inputs per gate used in the gate evaluation function, multi-stage processing can be performed with the number of input gates as required. It is possible to perform optimization according to a desired circuit technology, and it is possible to more accurately control the circuit quality of a circuit converted into an actual circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the invention.

FIG. 2 is a logic circuit diagram showing an initial circuit processed in the embodiment.

FIG. 3 is a logic diagram showing a multi-stage logic circuit obtained by evaluating the circuit shown in FIG. 2 in units of two-input gates.

FIG. 4 is a logic diagram showing a multi-stage logic circuit obtained by evaluating the circuit shown in FIG. 2 using a 4-input gate as a unit.

FIG. 5 is a logic diagram showing a multi-stage logic circuit obtained by evaluating the circuit shown in FIG. 3 in units of two-input gates.

FIG. 6 is a block diagram showing a conventional multi-stage logic circuit synthesis device.

[Explanation of symbols]

1 Input section 2 Main memory 3 Compilation part 4 Logic optimization section 5 Multi-stage processing section 6 Parameter setting section 7 Actual circuit conversion section 8 Actual circuit

Claims (1)

[Claims] 1. A multistage logic circuit synthesis device that generates a desired multistage logic circuit from logic information of a circuit given by a logical formula, a truth table, etc., comprising an input section (1) for inputting logic information;
A main memory (2) and a compile unit (3) that converts input logical information into an internal data format and expands it to the main memory.
), a logic optimization unit (4) that removes redundant parts using a two-stage logic simplification algorithm, and a multi-stage processing that uses a gate evaluation function to separate common parts of circuit parts by considering circuit area and delay time. A parameter setting section (6) connected to the multi-stage processing section (5) and inputting the maximum number of inputs per gate used for the gate evaluation function, 8).
) A multi-stage logic circuit synthesis device.