JPH0564080A - Image processor - Google Patents

Abstract

PURPOSE:To provide the titler which deals with all kinds of broadcasting television system for commonizing and to facilitate mass-production by providing a first and a second window pulse generators and an address counter. CONSTITUTION:The first window pulse generator 202 which receives a horizontal address and if its value is within the first specified range, generates the first window pulse and the second window pulse generator 203 which receives a vertical address and if its value is within the second specified range, generates the second window pulse are provided. In addition, an address counter 205 which is initialized when a vertical synchronization signal is given and generates the address to be given to an SRAM 14 by counting a dot clock only when both the first and the second window pulses are inputted is provided. As a result, all kinds of broadcasting television systems are dealt with by using the same circuit configuration, and a common titler and circuit are permitted to be shared, and so, a titler IC and a device can be mass-produced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to an image processing apparatus (camera integrated type video) for synthesizing (superimposing) a title image on a background image and recording (or monitoring, displaying). Device, as a generic name for video movies, title editing machines, etc.), regarding the improvement of Titler's address generation circuit.

[0002]

2. Description of the Related Art FIG. 2 is an overall block diagram of a camera-integrated video device 1 which is a specific example of an image processing device, and is a diagram mainly showing a titler 15 which processes and controls a title image. In the camera-integrated video device 1, two types of methods are mainly put into practical use as a method of combining the title image 2 with a general image (background image) 3.
In the first method, the image 3 is recorded on the video tape by the recording circuit 13, the video tape is rewound and reproduced, and the image 3
The title image 2 is photographed while checking the reproduced image of, and the title image 2 is combined with the image 3. This method
It has the advantage that you can superimpose and edit the appropriate title image at any time after you have shot and checked the recorded contents, but at the moment it is expensive, so it is limited to devices for enthusiasts. Has been done. Also,
Similarly, a title editing machine having no camera but having a title editing input device can also compose and edit a title image on a recorded video tape later.

In the second method, first, in the title storage mode, the title image 2 is photographed, digitized as a still image, temporarily stored in the SRAM 14, and later, the image 3 is displayed.
When a recording mode with a title is set by the photographer while shooting the image, the title image stored in the SRAM 14 is read out and superimposed on the image 3 for recording. Although this method reduces editing flexibility but does not cost much, it is becoming popular in almost all devices for general users. Therefore, the following description will be given with reference to FIG. 2 by taking a camera-integrated video device (hereinafter referred to as a video camera) adopting the second method as a concrete example.

This video camera 1 has a control circuit 12 for monitoring and controlling the entire video camera. Under this control, a video signal generating circuit 11, a recording circuit 13, and a titler 15 are provided.
And a SRAM 14 for storing the title image 2 under the control of the titler 15. Video signal generation circuit 11
Converts a captured image, for example, a title image 2 or an image 3 into a video signal Va and sends the video signal Va to the control circuit 12 and the titler 15. The control circuit 12 receives a switch input to generate a signal for controlling the entire video camera and various clocks, and also receives a video signal Va and outputs it as a video signal Vb in the recording mode. A vertical synchronizing signal or the like is generated and output as a control signal C to the titler 15.

The titler 15 receives the control signal C from the control circuit 12, and accordingly, in the title storage mode, sends the write data W and the address signal A to the SRAM 14 and writes the data of the title image 2 to the SRAM 14. .. In the recording mode with title, the control signal C
According to the above, the address signal A is sent to the SRAM 14, the data of the title image 2 is read from the SRAM 14, and this is output as the video signal Vc. If there is a video signal Vc (stored title image 2), the recording circuit 13 records the video signal Vd, which is a composite of this with the video signal Vb (background image 3 being captured), on a video tape.

The video camera 1 having such a configuration is set to the title storage mode by the switch operation, and once the title image 2 is stored, thereafter, the switch operation is performed at any time while the image 3 is being photographed and recorded. When the recording mode with a title is set, the title image 2 can be superimposed on the background image 3. The titler 15 is usually supplied as a one-chip IC, which helps to reduce the size and weight of the device.

Next, of the Titler 15, especially SRA
The configuration and operation of the circuit centering on the address generation circuit for M14 will be described with reference to FIG. This address generation circuit has a binarization circuit 101, a horizontal counter 102, and a vertical counter 103. Binarization circuit 10
1 receives the video signal Va, binarizes it, converts it into a digital value, and sends it as the write data W to the SRAM 14.

The horizontal counter 102 has a horizontal synchronizing signal HD.
Is received by the reset terminal RST to initialize the count value, and the dot clock CK is received by the clock input single terminal CLK to count it.
Output as H. The vertical counter 103 receives the vertical synchronizing signal VD at the reset terminal RST, the count value is initialized, and the horizontal synchronizing signal HD receives the clock input single terminal CLK.
In response to this, it is counted and the count value is output as the vertical address QV. The address signal A is configured by using the vertical address QV as the upper bit (see the broken line B in the figure) and the horizontal address QH as the lower bit.
4 is output.

The address signal A thus generated
In the title storage mode, the write data W is stored in the SRAM 14, and in the title-attached recording mode,
The data recorded as the read data R is read and output as a video signal Vc. Here, the dot clock CK, the horizontal synchronizing signal HD, and the vertical synchronizing signal VD are individual signals included in the control signal C as a generic name and given from the control circuit 12. Further, the following scroll start signal CS and wipe start signal CW are also the same.

Although the basic parts are as described above, since the video camera 1 also has a vertical scroll function and a vertical wipe function, the address generation circuit of the titler 15 is a scroll circuit which realizes these functions. It has a circuit 170 and a wipe circuit 160. The scroll circuit 170 includes a scroll counter 104, a window pulse generation circuit 109, and an adder 110, and adds a scroll address QS to the vertical address QV via the adder 110.
Is added to correct the address signal A. The scroll counter 104 resets the scroll start signal CS to a reset terminal R
The count value is initialized in response to ST, and the vertical synchronization signal V
The clock input single terminal CLK receives D, counts it, and outputs the count value as the scroll address QS.

Therefore, when the scroll start signal CS is received, the address signal A is corrected thereafter, so that the entire superimposed title image moves up or down (that is, scrolls). Here, the window pulse generation circuit 109 generates a window pulse indicating that the corrected address signal A is valid, and masks the read data R with this window pulse (AND gate 108) to display an undesired image. The suppressed signal is the video signal Vc.

Further, the wipe circuit 160 has a wipe counter 105 and a comparison circuit 106, and a wipe function in which the entire superimposed title image is displayed while stopped and partially disappears in order from the top or bottom. I do. For that purpose, the wipe counter 105 determines the wipe start signal C.
The count value is initialized by receiving W at the reset terminal RST, the vertical synchronizing signal VD is received at the clock input terminal CLK, and is counted, and the count value is determined by the wipe address QS.
Output as. The wipe circuit QS and the vertical address QV are compared by the comparison circuit 106, and the read data R is masked according to the comparison result and the signal Vc (AN
Output of the D gate 108), the title images are erased in order.

[0013]

As described above, in video cameras, a title image inserting function for superimposing a title image on a general image is rapidly spreading. However, the broadcasting television system (NTSC / PAL /
Since the number of vertical and horizontal data on the screen differs for each SECAM), a titler having an integrated title image insertion function needs to have different specifications for each method. To facilitate this understanding, NTSC 3 lines 4
The column and PAL are simplified to a system of data of 4 rows and 3 columns, which will be specifically described with reference to FIG.

First, with NTSC compatible Titler 15,
When the NTSC title image is stored in the SRAM 14 (see FIG. 3A), the horizontal counter value, that is, the horizontal address while the vertical counter value, that is, the vertical address QV is counted as “0”, “1”, and “2”. When QH is the vertical counter value, the count of "0" to "3" is repeated. Further, since the address signal A is formed by combining the vertical address QV and the horizontal address QH, it changes from “0” to “11”. Then, the values “a” to “l” of the data W of the title image are the address signals A
Is stored in the SRAM 14 at the corresponding address.

Next, this NTSC compatible Titler 15
Then, when the PAL title image is stored in the SRAM 14 (see FIG. 3B), while the vertical counter value, that is, the vertical address QV is counted as “0”, “1”, “2”, “3”, the horizontal Counter value, horizontal address QH
However, at each vertical counter value,
Repeat the count of "2". Further, the address signal A
Is generated by combining the vertical address QV and the horizontal address QH, so that "0" to "2", "4" to
It changes to "6", "8" to "10", "12" to "14". Then, the value “a” of the data W of the title image is
“1” is stored in the corresponding address of the SRAM 14 according to the address signal A. However, since the value of the address signal A is discontinuous, the addresses "3", "7", "11" of the SRAM 14 are not used, and the SR
Since the addresses “12” to “14” of the AM 14 are out of the range, the values “j” to “l” of the data W of the title image are not stored and are lost.

As is apparent from the above description, in the conventional image processing apparatus using the titler, it is necessary to adopt a different titler and a different memory configuration for each broadcasting television system. It is also inconvenient for set makers. Furthermore, as a matter of course, neither scroll nor wipe, which is an important function of the image processing apparatus, can be shared. The object of the present invention is to solve the above-mentioned drawbacks of the prior art, and to realize a titler capable of supporting all broadcasting television systems and to make it common, thereby contributing to mass production of image processing devices. It is a thing.

[0017]

To achieve this object, an image processing apparatus according to the present invention has a horizontal counter, a vertical counter, an SRAM, a first window pulse generating circuit, a second window pulse generating circuit, It is provided with an address counter (see FIG. 1). Horizontal counter (1
02) is initialized by receiving the horizontal synchronizing signal (HD),
The horizontal clock (QH) is generated by counting the dot clock (CK). The vertical counter (103) is initialized by receiving the vertical synchronizing signal (VD), counts the horizontal synchronizing signal (HD), and generates a vertical address (QV). The SRAM (14) receives the address signal (A), stores the data (W) of the digital image of the title image at this address in the write mode, and in the read mode.
The data (R) of this address is output.

First window pulse generation circuit (20
2) receives the selection signal (CP) of the broadcasting television system,
According to the selection signal (CP), the first predetermined range is changed to a value adapted to the selected broadcasting television system, the horizontal address (QH) is received, and when the value is within the first predetermined range, the first predetermined range is received. Generates a window pulse. The second window pulse generation circuit (203) receives a selection signal (CP) for the broadcasting television system, and according to the selection signal (CP), a value for adapting the second predetermined range to the selected broadcasting television system. Instead, a vertical address (QV) is received, and when this value is within a second predetermined range, a second window pulse is generated.

The address counter (205) is initialized by receiving the vertical synchronizing signal (VD) (see the broken line in FIG. 1), and when both the first window pulse and the second window pulse are input ( For example, the gate 204
Only when the gate input terminal G is received via the), the dot clock (C) received by the clock input terminal (CLK)
K) is counted and the address signal (A) to the SRAM (14) is generated. Then, the video camera of the present invention writes the title image to the SRAM (14) according to the address signal (A) in the title storage mode, and writes the title image to the address signal (A) in the title-attached recording mode.
The title image is read out from the SRAM (14) and superimposed on the background image.

[0020]

As described above, the window pulse corresponding to the television system is generated in the horizontal direction and the vertical direction, and the AN
Since the SRAM is accessed by sequentially updating the address under the D condition, it is possible to support all broadcasting television systems by using the same titler and memories of almost the same size.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of a titler address generation circuit in the image processing apparatus of the present invention, and corresponds to FIG. 4 showing a conventional example. The basic part will be described with reference to FIG. 3, but for the sake of easy understanding, the contents are simplified and, like the conventional example, NTSC is composed of 3 rows and 4 columns, and PAL is composed of 4 rows and 3 columns. Further, it is assumed that the SRAM has a configuration including a 12-bit memory, and that the effect of the titler of the present invention can be applied to PAL. Furthermore, it will be explained that the present invention can be used in common even when it has a vertical scroll function and a vertical wipe function.

First, the NTSC title image is transferred to the SRAM.
When the data is stored in (14) (see FIG. 3A), the selection signal (CP) selects NTSC, and the first window pulse generation circuit (202) receiving this selects the first predetermined range as "1". It is set to 0 ”to“ 3 ”. Similarly, the selection signal (CP)
Received second window pulse generation circuit (203)
Sets the second predetermined range to "0" to "2". further,
The vertical counter, that is, the vertical address (QV) is "0",
While counting "1" and "2", when the horizontal counter value, that is, the horizontal address (QH) is the vertical counter value, the count of "0" to "3" is repeated.

The address signal (A) has the vertical address (QV) within the first predetermined range, and
Since the count value of the address counter (205) advances only when the horizontal address (QH) is within the second predetermined range, it continuously changes from “0” to “11”. As a result, the values “a” to “l” of the title image data (W) are
It is stored in the corresponding address of the SRAM (14) according to the address signal (A).

Next, the PAL title image is transferred to the SRAM (1
4) (see FIG. 3C), the selection signal (CP) selects PAL, and the first window pulse generation circuit (202) which receives this selects the first predetermined range as “0”. "-" 2 ". Similarly, the second window pulse generation circuit (203) receiving the selection signal (CP) sets the second predetermined range to "0" to "3". Further, the vertical counter, that is, the vertical address (QV) is "0",
While counting "1", "2", "3", when the horizontal counter value, that is, the horizontal address (QH) is the vertical counter value, the count of "0" to "2" is repeated.

The address signal (A) has the vertical address (QV) within the first predetermined range, and
Since the count value of the address counter (205) advances only when the horizontal address (QH) is within the second predetermined range, the value in the range of "0"- It changes continuously with "11". As a result, the values “a” to “l” of the title image data (W) are stored in the corresponding addresses of the SRAM (14) according to the address signal (A) regardless of the broadcasting television system.

As described above, the model has been simplified to a size of 3 to 4 rows (columns), but in reality, it is usually 256 or 512, and the squared memory size is by no means negligible. Absent. In particular, for video cameras in which there is an urgent need for downsizing, weight reduction, and low power consumption of devices, it is extremely effective to use almost the same size of memory in each system without waste.

Although the data W has been described as 1-bit data, it may be a plurality of bits according to the data width of the SRAM. In this case, a serial-parallel conversion circuit mainly composed of a shift register is provided in the signal line portion of the signals W and R, and instead of the dot clock CK,
Since the clock divided by the number of bits may be used, the difference in data width does not impair the present invention. Further, although the case of NTSC and PAL has been described as an example, the same applies to the case of SECAM, so that the present invention is effective in this case as well, without needing to describe in detail. ..

The titler address generation circuit of this embodiment is a scroll circuit 27 which can be made common as the respective circuits having a vertical scroll function and a vertical wipe function.
0 and wipe circuit 160. Scroll circuit 27
0 has a scroll counter 104, a window pulse generation circuit 209, and a comparison circuit 206. The scroll counter 104 receives the scroll start signal CS at the reset terminal RST to initialize the count value, receives the vertical synchronization signal VD at the clock input single terminal CLK, counts it, and outputs the count value as the scroll address QS. ..

The comparison circuit 206 receives the vertical address QV and the scroll address QS, compares these values,
Output signal when equal. Moreover, when it has a scroll function, the address counter 205 outputs the output of the comparison circuit 206 instead of the vertical synchronization signal VD to RST.
It is received by the input terminal. The window pulse generation circuit 209 has a vertical address QV and a scroll address Q.
Upon receiving S and the selection signal CP, the window pulse is generated only when the value of the vertical address QV is within the range between the predetermined value selected by the selection signal CP and the value of the scroll address QS.

In the scroll circuit 270 having such a structure, the scroll counter 104 is initialized when the scroll start signal CS is received, and the address signal QS advances (or decreases) each time the vertical synchronizing signal VD is received thereafter.
The signal from the comparison circuit 206 is gradually delayed (or advanced) from the vertical synchronization signal VD. Therefore, the initialization timing of the address counter 205 is also gradually delayed (or advanced), and the address signal A is gradually delayed (or advanced) from the vertical synchronizing signal VD, so that the entire superimposed title image is superimposed. Moves down (or up) (ie scrolls). Here, the window pulse generation circuit 209 generates a window pulse indicating that the address signal A is valid, and masks the read data R with this window pulse (AND gate 108) to suppress an undesired image, The video signal is Vc. Moreover, since the width of the window pulse changes according to the selection signal CP, it is possible to support all broadcasting television systems.

Further, the wipe circuit 160 has a wipe counter 105 and a comparison circuit 106, which are the same as those in the conventional case. As in the conventional case, the wipe counter 105 outputs the wipe address QS, and the wipe address QS and the vertical address QV. Are compared by the comparison circuit 106, and the read data R is masked according to the comparison result, whereby the title images are erased in order and the wipe function is performed. As described above, the address generation circuit of the present invention can cooperate with the wipe circuit 160 having the same configuration as the conventional one. Although the case where the title image is stored in the title storage mode and superimposed on the background image in the title recording mode has been described as a specific example, the background image is first recorded on the videotape. From the above description, it is apparent that the titler of the present invention can be applied to a video camera or a title editing machine that synthesizes and edits a title image on the video tape.

[0032]

As described above, in the image processing apparatus using the titler of the present invention, the same circuit configuration (control circuit, titler, memory) must be compatible with all broadcasting television systems. Is possible. As a result, a common titler and circuit can be realized, and a titler IC
Also, it can contribute to mass production of the device.

[Brief description of drawings]

FIG. 1 is a block diagram of a titler address generation circuit in an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of the entire video device with integrated camera.

FIG. 3 is an example of a simplified case of 4 rows and 3 columns in order to explain the storage state of each counter value and title image data. (A) is an example in which NTSC is processed by an NTSC compatible circuit. (B) is an example when PAL is processed by an NTSC-compatible circuit. (C) is an example when PAL is processed by an NTSC / PAL compatible circuit.

FIG. 4 is a block diagram of a titler address generation circuit in a conventional image processing apparatus.

[Explanation of symbols]

1 ... video camera, 2 ... title image, 3 ... image, 11 ...
Video signal generation circuit, 12 ... Control circuit, 13 ... Recording circuit 14 ... SRAM, 15 ... Titler, C ... Control signal, V
a, Vb, Vc, Vd ... video signal, W ... write data, A ... address signal, R ... read data, 101 ... binarization circuit, 102 ... horizontal counter, 103 ... vertical counter, 104 ... scroll counter, 105 ... Wipe counter, 106 ... Comparison circuit, 107 ... OR gate, 108
... AND gate, 109 ... Window pulse generation circuit,
110 ... Adder, 160 ... Wipe circuit, 170 ... Scroll circuit, CK ... Dot clock, HD ... Horizontal sync signal, VD ... Vertical sync signal, CS ... Scroll start signal,
CW ... wipe start signal, QH ... horizontal address, QV ... vertical address, QS ... scroll address, QW ... wipe address, 202, 203 ... window pulse generation circuit, 204 ... AND gate, 205 ... address counter, CP ... selection signal, 206 ... Comparison circuit, 209 ... Window pulse generation circuit.

Claims (2)

[Claims] 1. A horizontal counter that is initialized by receiving a horizontal synchronizing signal, counts a dot clock, and generates a horizontal address, and a horizontal counter that is initialized by receiving a vertical synchronizing signal, counts the horizontal synchronizing signal, and outputs a vertical address. And a SRAM which receives an address signal composed of the vertical address and the horizontal address and holds data of a title image of a digital value. In the title storage mode, the title image is stored according to the address signal. In the recording mode with writing in the SRAM, the title image is read from the SRAM according to the address signal, and the title image is superimposed on the background image. According to the selection signal, the selection signal indicates the first predetermined range. A first window pulse generating circuit for receiving the horizontal address and generating a first window pulse when the value is within a first predetermined range; and receiving the selection signal, According to this selection signal, the second predetermined range is changed to one corresponding to the television system indicated by the selection signal, the vertical address is received, and when this value is within the second predetermined range, a second window pulse is generated. A second window pulse generation circuit, which is initialized by receiving the vertical synchronizing signal, counts the dot clock only when both the first window pulse and the second window pulse are input, and outputs the dot clock to the SRAM. An image processing apparatus comprising: an address counter for generating an address. 2. A horizontal counter which is initialized by receiving a horizontal synchronizing signal, counts a dot clock, and generates a horizontal address, and a vertical counter which is initialized by receiving a vertical synchronizing signal, counts the horizontal synchronizing signal, and outputs a vertical address. A vertical counter for generating a scroll start signal, which is initialized by receiving a scroll start signal, counts the vertical synchronizing signal, and generates a scroll address, receives the vertical address and the scroll address, and outputs these values as a first value. A first window pulse generation circuit for generating a first window pulse when within a predetermined range of, and an address signal composed of the vertical address to which the scroll address is added and the horizontal address, SRA that holds the data of the title image
In the title storage mode, a title image is written to the SRAM in accordance with the address signal, and in the title-added recording mode, the title image is read from the SRAM in accordance with the address signal and receives a first window pulse. An image processing apparatus that superimposes the title image on a background image only when receiving a selection signal of a broadcasting television system, and according to the selection signal, a second predetermined range corresponding to the television system indicated by the selection signal. Alternatively, a second window pulse generation circuit that receives the horizontal address and generates a second window pulse when the value is within a second predetermined range; and receives the selection signal and outputs a third signal in accordance with the selection signal. The predetermined range is changed to one corresponding to the television system indicated by the selection signal, and the vertical address A third window pulse generating circuit for generating a third window pulse when this value is within a third predetermined range; and a initialization result in response to a result of comparison between the vertical synchronizing signal and the scroll address. 2 window pulse and 3rd
An address counter that counts the dot clock and generates an address to the SRAM only when both window pulses are input. The first window pulse generation circuit receives the selection signal, and selects the selection signal. An image processing apparatus, characterized in that the first predetermined range is changed in accordance with a signal to one corresponding to a television system indicated by the selection signal.