JPH0563756A - Communication protocol controller - Google Patents

Abstract

PURPOSE:To process generation and check of an error check code at a high speed in a header added at data transfer in a data communication system. CONSTITUTION:The controller is provided with an error check code generating circuit check circuit 4, and when data are transferred from a terminal equipment 8 to a memory 3 via a terminal interface 1 and a local bus 6 at the transmission processing, the error check code is generated in a header in parallel and the data are sent to a communication line 11. Moreover, when a PDU(protocol data unit) is transferred from the communication line 11 via a communication control access control section 5 and the local bus 6 to the memory 3, an error check code in the header is checked in parallel simultaneously as the transfer of the PDU. Thus, the error check code is generated and checked at a high speed in the transmission reception of the PDU and about 20% of the transmission processing time and the reception processing time is saved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication protocol control device in a data communication system.

[0002]

2. Description of the Related Art When performing data communication between a plurality of terminal devices, data error checking is indispensable. Therefore, conventionally, a system of a method of performing data communication using a protocol data unit composed of a header section including an error check code and a data section is known,
An example thereof is shown in FIG.

The data communication system shown in FIG. 2 comprises a plurality of communication terminals 10 and a communication line 11, and the communication terminals 10 are provided with a terminal device 8 and a communication protocol control device 7. FIG. 3 shows a protocol data unit (hereinafter abbreviated as PDU) 12 transmitted by a communication line 11 in this data communication system. As shown in the figure, this PDU 12 is a start delimiter indicating the beginning of the protocol delimiter. , A destination address, a source address, and a header including protocol control information such as an error check code, and an end delimiter indicating the end of the data and the PDU 12, with the start delimiter at the beginning.
The data is transmitted between the terminal devices 8 through the communication line 11 in FIG.

By the way, as the communication protocol control device 7 in such a data communication system, the one shown in FIG. 4 has been conventionally used. In this FIG.
Reference numeral 1 is a terminal interface, 2 is a processor 2, 3 is a memory, 5 is a communication line access control unit, and 6 is a local bus.

Next, the operation of this conventional example will be described. The transmission process is executed according to the flowchart of FIG. First, in the memory transfer process 13, the data sent from the terminal device 8 is transferred to the memory 3 via the terminal interface 1 and the local bus 6. Then, in the header generation processing 14, the processor 2 generates a header excluding the error check code and adds it to the data in the memory 3. Then, in the error check code generation processing 15, the processor 2 generates an error check code and writes it in the header in the memory 3. Then, the transmission preparation process 16
By the communication line sending processing 17, the data and the header in the memory 3 are sent to the communication line 11 via the communication line access control unit 5. At this time, when transmitting the PDU to the communication line 11, the communication line access control unit 5 adds a start delimiter and an end delimiter.

Next, the reception process is executed according to the flowchart of FIG. First, in the communication line receiving process 18 and the memory transfer process 19, the P received from the communication line 11 is received.
The DU is transferred to the memory 3 through the communication line access control unit 5. When passing through this communication line access control unit 5,
The starting and ending delimiters are removed. After that, in the error check code checking process 20, the processor 2
The error check code is inspected by the method, the header is analyzed and removed in the header analysis process 21, and then transferred to the terminal device 8 via the local bus 6 and the terminal interface 1.

By the way, in such a data transmission system, the reduction of the time required for the generation and analysis of the header of the PDU described above greatly contributes to the improvement of the transmission efficiency in the data communication. Therefore, for example, in JP-A-63-308444, the protocol control information in the header is registered in advance in a memory or the like, and when a request for transmission or the like appears, the registered protocol control information is stored. A method has been proposed in which a header is generated by referring to and directly adding the referred protocol control information to the data to shorten the header generation time.

Other related devices of this type are disclosed in JP-A-60-264143 and JP-A-61.
-64447, JP-A-62-105554, and JP-A-2-190064 can be mentioned.

[0009]

The above-mentioned conventional technique can deal with protocol control information such as a source address whose pattern is relatively easy to fix, but especially data patterns of header and data. No consideration is given to handling protocol control information in which it is difficult to fix a pattern, such as an error check code generated more. Therefore, in the conventional technique, for example, an error occurs in the program by the processor 2 each time transmission is performed. It is necessary to generate a check code, which takes a lot of processing time and causes a decrease in transmission efficiency.

As described above, in data communication,
From the viewpoint of guaranteeing the reliability of data, the use of error check code is indispensable, and speeding up the processing is a major issue.

Regarding the processing of the error check code, there is another problem in addition to the difficulty in fixing the pattern. Since the error check code for the header and data is included in the header that is the beginning of the PDU, the error check code must be generated and added to the header while sending the data to the communication line. It is a point that can not be done. In other words, since the error check code can be generated only at the end of the data, the header to which the error check code should be added has already been sent to the communication line at the time when the error check code can be generated. This is because addition becomes impossible.

Therefore, in the prior art, before sending to the communication line, the processor 2 generates an error check code for the header and data in the memory 3, adds the error check code in the header, and then sends it to the communication line. However, the transmission efficiency has been reduced because the method that has been used has been used.

An object of the present invention is to provide a communication protocol control device capable of sufficiently speeding up error check code processing and suppressing a decrease in transmission efficiency to a minimum.

[0014]

The above-mentioned object is to perform protocol control in a header of a PDU in parallel with a process of transferring data from a terminal device to a memory for storing data or a process of transferring a PDU to a memory from a communication line. This is achieved by providing means for generating and checking an error checking code which is information.

In the above means, when the PDU is transmitted, the data is transferred from the terminal device to the data storage memory at the same time as the data is transferred from the terminal device to the data storage memory, and is generated by the processor. The error check code is generated by the header and the error check code is inserted in the header at the time of transmission to the communication line, and the PDU received from the communication line at the time of reception.
While being stored in memory, the error checking code in the header of the PDU is monitored and checked.

[0016]

With the above structure, when the transmission or reception of the PDU occurs, the above-mentioned means generates and checks the error check code which is the protocol control information in the header of the PDU.
It functions to transfer data from the terminal device to the data storage memory or transfer PDU from the communication line to the memory in parallel with processing. Therefore, the processing time required to generate and inspect the error check code is shortened, and high-speed protocol processing is possible.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The communication protocol control device according to the present invention will be described in detail below with reference to the illustrated embodiments. Figure 1
4 is an embodiment of the present invention. In the figure, 4 is an error check code generation / inspection circuit, and the rest of the configuration is the same as the prior art of FIG. The terminal device 8 generates and interprets data, the terminal interface 1 controls input / output of data between the terminal device 8 and the communication protocol control device 7,
The processor 2 controls commands and status of the terminal device 8 and generates and interprets a header. The memory 3 stores the transmission / reception data, the communication line access control unit 5 controls the transmission / reception of the PDU with the communication line, and the error check code generation / inspection circuit 4 functions to generate or inspect the error check code of the transmission / reception data. .. And local bus 6
Is the path for data and control signals.

Next, regarding the operation of the embodiment shown in FIG.
The operation during transmission and the operation during reception will be described separately. First, FIG.
7 shows a PDU transmission processing procedure in this embodiment. In FIG. 7, a memory transfer processing 13, a header generation processing 14, a transmission preparation processing 16, and a communication line transmission processing 1 are shown in FIG.
7 is the same as the transmission processing procedure in the conventional technique of FIG. 4 shown in FIG. 5, although the expression is partially different.

On the other hand, the processes 22, 23 and 24 are executed by the error check code generation / inspection circuit 4 in parallel with the processes 13, 14 and 16 of the above processes. In FIG. 1, when the data is transferred from the terminal device 8 through the terminal interface 1 and the local bus 6 to the memory 3, that is, when the process 13 is executed, the error check code generation / check circuit 4 , A process of generating a data error check code while monitoring the data on the local bus 6.

Next, in process 14, the processor 2 generates a header part excluding the error check code, transfers it to the memory 3 via the local bus 6, and adds it to the front part of the already transferred data. At this time, at the same time, in process 23, the error check code generation / inspection circuit 4 monitors the header information on the local bus 6, and adds the header information to the error check code of the generated data. As a result, an error check code that combines the header and the data is generated.

After that, in process 16, when the PDU in which the header and the data transferred in the memory 3 are transferred to the communication line access control unit 5, an error check code is generated.
A process 24 for inserting the error check code generated by the inspection circuit 4 into the designated portion in the header is executed.

FIG. 8 is a time chart showing the transmission processing shown in FIG. 7. The transmission processing time t of the PDU is plotted on the horizontal axis, and the transmission processing time according to the prior art and the transmission processing according to the embodiment of the present invention are shown. It is shown in contrast to time. Here, the transmission processing time is the time until the data sent from the terminal device 8 in FIGS. 1 and 4 is processed in the communication protocol control device 7 and sent to the communication line 11.

In FIG. 8, the memory transfer processing time 26 is the time required for data to be transferred from the terminal device 8 in FIG. 1 to the memory 3 via the terminal interface 1 and the local bus 6, and the header generation processing. The time 27 is the header generation time by the processor 2 excluding the error check code, the error check code generation processing time 28 by the processor is the header and data error check code generation time by the processor 2, and the communication line transmission. The processing time 29 means PD from the memory 3 to the communication line 11 via the local bus 6 and the communication line access control unit 5.
Each represents the time to transmit U.

From FIG. 8, it can be seen that the transmission processing time in the embodiment of the present invention is shortened by the error check code generation processing time 28 by the processor 2 as compared with the processing time of the prior art. .. In addition, in FIG. 7, the error check code generated in the process 24 can be written in the error check code area of the header in the memory 3 instead of being inserted in the header.

Next, FIG. 9 shows a PDU reception processing procedure in this embodiment. In FIG. 9, the communication line reception processing 18, the memory transfer processing 19, and the header analysis processing 21 are partially expressed. 4 is the same as the reception processing procedure in the related art of FIG. 4 shown in FIG.

The error check code checking process 25 is shown in FIG.
The PDU received from the communication line 11 shown in FIG. 2 passes through the local line 6 from the communication line access control unit 5 and is executed by the error check code generation / inspection circuit 4 in parallel with the process 18 stored in the memory 3. This is a process of monitoring a PDU on the local bus 6, generating an error check code, and inspecting the result. By thus processing the error check code check in parallel with the data transfer from the communication control access unit 5 to the memory 3, the error check code check time can be shortened.

FIG. 10 is a time chart showing the reception processing operation shown in FIG. 9. The reception processing time t of the PDU is shown in FIG.
Is a horizontal axis, and shows the reception processing time of the prior art and the reception processing time according to the embodiment of the present invention in comparison.
Here, the reception processing time is the time until the PDU received from the communication line 11 in FIG. 1 is processed in the communication protocol control device 7 and transferred to the terminal device 8.

In FIG. 10, the communication line and memory transfer processing time 30 is the time until the PDU is transferred from the communication line 11 in FIG. 1 to the memory 3 through the communication control access unit 5 and the local bus 6. The error check code check processing time 31 in the processor means the processor 2
The time required for checking the error check code in the header by the header and the header analysis processing time 32 is the processor 2
Represents the parsing time of the header.

As is apparent from FIG. 10, the reception processing time according to the embodiment of the present invention is shortened by the inspection processing time 31 of the error check code by the processor 2 as compared with the reception processing time of the prior art. You can see that

Next, details of the error check code generating / checking circuit 4 in FIG. 1 will be described. FIG. 11 shows an embodiment of the error check code generating / checking circuit 4, which includes an input / output interface section 33, an arithmetic section 34, a result storage register 35, a counter section 36, an input / output control line 37, an arithmetic control line 39, and It is composed of a register control line 40.

The input / output interface unit 33 functions to control the input / output of data transferred on the local bus 6, and the arithmetic unit 34 functions to calculate an error check code. The result storage register 35 functions to store the result calculated by the calculation unit 34. Further, the counter unit 36 has a function of instructing start and end of error check code generation / inspection, generation of data transferred on the local bus 6, and control of an inspection range by an instruction of the processor 2,
The input / output control line 37 controls the input / output interface, and the arithmetic control line 39 controls the arithmetic unit. And
The register control line 40 controls the result storage register.

Next, the operation of the error check code generating / checking circuit 4 shown in FIG. 11 will be described. First,
At the time of data transmission processing, the input / output interface unit 33 fetches the data transferred on the local bus 6 into the arithmetic unit 34. On the other hand, the processor 2 gives the generation start information to the counter unit 36, whereby the counter unit 36 instructs the arithmetic unit 34 via the arithmetic control line 39 to generate an error check code.

The arithmetic unit 34 adds data for each arithmetic unit and stores the arithmetic result in the result storage register 35. At this time, the generation range is given in advance from the processor 2 to the counter unit 36, and based on the information, the counter unit 36
The generation range is counted with and the counter section 3 is generated when the generation is completed.
6 sends it to the result storage register 35 via the register control line 40, sends the stored error check code to the local bus 6 via the input / output interface 33, and is transferred on this local bus 6. The PDU is inserted at a predetermined position in the header of the PDU.

Next, during the data receiving process, when the received data is transferred from the communication line access control unit 5 in FIG. 1 to the memory 3, the PDU is fetched from the input / output interface 33 to the arithmetic unit 34 and transmitted from the local bus 6. Similar to the time, the processor 2 supplies information such as the inspection range to the counter unit 36, and the counter unit 36 controls the arithmetic unit 33 via the arithmetic control line 39 to inspect the error check code.

As a second embodiment, when transmission and reception of PDUs occur in an overlapping manner, the result storage register 3 in the error check code generation / inspection circuit 4 shown in FIG.
5 and the counter unit 36 are provided as separate registers for transmission and reception, and when data of the transmission PDU is transferred on the local bus 6, the data is monitored and the arithmetic unit 34 is supplied through the input / output interface 33. Take in,
The calculation result is stored in the register for transmission, and in the case of reception, the data of the reception PDU on the local bus 6 is stored.
Similar to the transmission, it is taken into the arithmetic unit 34 and the arithmetic result is stored in the reception register.

Therefore, according to the second embodiment, it is possible to generate and inspect the error check code of the transmission PDU and the reception PDU by alternately repeating the above-mentioned transmission and reception operations. As a result, it becomes possible to transmit and receive PDUs in parallel, and the same effect as the embodiment of FIG. 11 can be obtained.

As a third embodiment, the error check code generation / check circuit 4 shown in FIG. 11 may be separately provided for transmission and reception. In the case of this embodiment, error check code generation of the transmission PDU and reception PDU
By individually performing the error check code inspection of (1), it is possible to perform PDU transmission and reception in parallel, and again, the same effect as the embodiment of FIG. 11 can be obtained.

Further, as a fourth embodiment, the processing of generating the header, which is performed after the data transfer from the terminal device 8 in FIG. 1 described in the procedure of the transmission processing, is not performed by the processor 2 in the communication protocol control device 7. In addition, the terminal device 8 may previously generate the header portion excluding the error check code. In the case of this embodiment, the header and data, that is, the PDU, is sent from the terminal device 8 to the terminal interface 1
And to the memory 3 via the local bus 6. At this time, the error check code generation / inspection circuit 4 monitors the header and data on the local bus 6, and the error check code of the PDU is once transmitted in parallel with the data transfer. To generate
When the PDU in the memory 3 is transferred to the communication line access control unit 5, the error check code is inserted in the designated portion in the header.

This operation will be described with reference to FIG.
A memory transfer process 41 of PDU is provided in place of the memory transfer process 13 of data in FIG. 10, the header generation process 14 is removed, and an error check code generation process 22 of the data part and an error check code generation process 23 with a header are replaced. The error check code generation process 42 of the PDU is provided, and the transmission preparation process 16 and the communication line transmission process 1 are performed.
7, and the error check code insertion processing 24 is left as it is.

The processing operation according to the embodiment of FIG. 12 is shown by the transmission processing time chart of FIG. 8. In the prior art and the embodiment of the present invention, the header generation processing time 27 in the processor 2 is calculated from the entire transmission processing time. In comparison with the prior art, the transmission processing time in the embodiment of the present invention is shortened by the error check code generation processing time 28 by the processor 2, Therefore, it is understood that the same effect as that of the embodiment shown in the flowchart of FIG. 7 can be obtained also by the embodiment of FIG.

[0041]

According to the present invention, a PDU to be transferred in a communication protocol control device in a data communication system
The error check code can be generated / inspected at high speed, and the transmission processing time and the reception processing time can be reduced by about 20%, which has the effect of sufficiently improving the transmission efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a communication protocol control device according to the present invention.

FIG. 2 is a configuration diagram showing an example of a data communication system to which a communication protocol control device according to the present invention is applied.

FIG. 3 is an explanatory diagram of a protocol data unit used in a data communication system to which the communication protocol control device according to the present invention is applied.

FIG. 4 is a block diagram showing a conventional example of a communication protocol control device.

FIG. 5 is a flowchart for explaining a data transmission operation in the conventional example of the communication protocol control device.

FIG. 6 is a flowchart for explaining a data receiving operation in the conventional example of the communication protocol control device.

FIG. 7 is a flowchart illustrating a data transmission operation according to an embodiment of the present invention.

FIG. 8 is a characteristic diagram for explaining a data transmission operation in the embodiment of the present invention.

FIG. 9 is a flowchart illustrating a data receiving operation according to an embodiment of the present invention.

FIG. 10 is a characteristic diagram for explaining a data receiving operation in the embodiment of the present invention.

FIG. 11 is a detailed block diagram of an embodiment of a communication protocol control device according to the present invention.

FIG. 12 is a flow chart for explaining a data transmission operation in another embodiment of the present invention.

[Explanation of symbols]

 1 Terminal Interface 2 Processor 3 Memory 4 Error Check Code Generation / Inspection Circuit 5 Communication Line Access Control Unit 6 Local Bus 7 Communication Protocol Control Device 8 Terminal Equipment 10 Communication Terminal 11 Communication Line 12 PDU (Protocol Data Unit) 13 Memory Transfer Processing 33 Input / output interface 34 Error check code operation unit 35 Operation result storage register 36 Counter unit 37 Input / output control line 39 Operation control line 40 Register control line

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Nao Ogawa 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Omika factory (72) Inventor Tatsuya Yokoyama 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Hitachi, Ltd. System Development Laboratory

Claims (3)

[Claims] 1. A communication protocol control device in a data communication system of a system in which data transmission between a plurality of terminal devices is performed using a protocol data unit including a header part including an error check code and a data part. An error check code generation / inspection unit that operates independently of the processing processor is provided, and in parallel with the process of transferring the data section to the data storage memory, an error check code corresponding to the data section is generated. A communication protocol control device characterized by being configured to perform an inspection. 2. The invention according to claim 1, wherein the error check code generating / inspecting means calculates an error check code, a register section for storing an operation result, and a counter section for controlling a generation range of the error check code. And a communication protocol control device comprising an input / output interface unit for controlling the input / output of the data that is the target of the error check code. 3. The invention according to claim 2, wherein the processing for controlling the generation range of the error check code in the counter section sends the generation range of the error check code and start / end information of the processing to the counter section. A communication protocol control device comprising: a giving process and a process in which the counter section gives an instruction of generation to the arithmetic section based on these pieces of information.