JP2002183072A - Interface controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To carry out data transfer by maximum performance by performing the SB-CRC calculation of IU extending to plural frames asynchronously with data transfer with the request of data transfer as an opportunity so as to eliminate the overhead of the SB-CRC calculation. SOLUTION: An interface controller is provided with a transmission/reception buffer capable of reading at a speed of at least two times that of a data transfer rate to asynchronously generate/check FCS and read data by data transfer and to generate and check FCS by a private circuit to reduce the overhead of the generation and check of FCS in data transfer. Furthermore, starting of data transfer and the initial value and the calculation result of FCS can be processed by a micro-program within the interface controller and data transfer can be requested plurally and simultaneously to flexibly cope with protocol multiplex operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control method of an input / output interface connected between processing devices such as a central processing unit and an input / output device. One FCS (Frame C
The present invention relates to an interface control method for efficiently generating and checking an FCS in a data transfer protocol to which a heck sequence is attached.

[0002]

2. Description of the Related Art OSI (Open System Interconnection)
As typified by the model, the structure of the network architecture is hierarchized by function, and realizing various protocols in each layer has enabled a highly flexible network construction. ANSI (Ameriacan National Standard
Similarly, Fiber Channel standardized by the Institute is also hierarchized, using Fiber Channel media, and IP (Interlayer Protocol) as ULP (upper layer protocol).
t Protocol) and SCSI (Small Computer System Interface)
ace), FC-SB2 (Single-Byte Command Code Sets)
Various protocols such as Mapping Protocol-2) can be executed.

However, if the amount of data to be transmitted by the upper layer protocol is larger than the amount of data that can be transmitted at one time by the lower layer protocol due to such layering, processing such as data division / assembly becomes necessary. .

For example, in a physical interface represented by an optical fiber in a fiber channel, FIG.
As shown in FIG. 2B, data transfer is performed in units of frames 200. In FC-SB2 which is a UL of Fiber Channel, information unit IU (Information
Since the data transfer is performed by the (Unit) 201, processing such as division of the IU into frames and assembly of the frames into IUs are required.

The frame 200 has a 4-byte start code.
(SOF), 24 bytes of header information and up to 2,
A 112-byte data, a 4-byte CRC (hereinafter referred to as a frame CRC) is added as an FCS for detecting header information and data errors, and finally a 4-byte end code (E
OF). Information unit 2
01 is a 32-byte header information and a maximum of 8,160 bytes of data, and if necessary, a 4-byte CRC (hereinafter referred to as SB_
(CRC), and the information unit 201
The header information and data of the
The data is divided into 0 data and mapped. SB_CRC
Is added for error detection of the data portion of the SB data 202 composed of one or a plurality of IUs, as shown in FIG.

Conventionally, in an interface control device represented by a fiber channel, a portion for performing processing in a frame unit of a lower layer and a portion for mainly performing processing in accordance with ULP are divided into input / output devices such as a PCI bus and a micro channel. Data transfer is often realized by connecting to a bus. That is, by dividing the lower layer and the upper layer, the change accompanying the improvement of the bit rate of the optical fiber and the U
It has a flexible structure for changing LP, and various data transfer systems can be constructed. FIG. 8 shows a conventional example of an interface control device.

The interface controller can be divided into a lower interface controller 700 for controlling the lower layer of the fiber channel and an upper interface controller 701 for performing other controls including ULP.
They are connected by an input / output bus 702.

The lower interface controller 700 converts and controls an optical signal on the optical fiber cable 703 and a transmission / reception frame, a link controller 704, a transmission buffer 705 for storing the transmission / reception frame, and a reception buffer 706.
And an FC protocol control unit 707 for performing a frame transfer control and the like of the Fiber Channel by a microprogram, and an input / output bus control unit 708.

The upper interface controller 701 includes a main memory 709 and a central processing unit 710 via an input / output bus controller 711.
And a personal computer as an example of the higher-level interface control device 701.

[0010] The operation of the conventional example regarding frame transmission will be briefly described below with reference to the flowchart of FIG.

The central processing unit 710 stores the transmission data in the main memory 709 (800), and instructs the lower interface controller 700 to transmit (801). FC of the lower interface controller 700 that received the transmission instruction
The protocol control unit 707 instructs the input / output bus control unit 708 to store the transmission data from the main memory 709 in the transmission buffer 705 (802). Upon receiving the instruction, the input / output bus control unit 708 stores the transmission data in the main memory 70.
9 to the transmission buffer 705 (803), and upon detecting the end of the storage, the FC protocol control unit 707 instructs the link control unit 704 to transmit a frame of the transmission buffer.
(804). Link control unit 70 receiving frame transmission instruction
4 generates and adds the header information and the frame CRC of the frame from the transmission buffer 705, and transmits the frame (8).
05).

The operation of the conventional example relating to frame reception will be briefly described below with reference to the flowchart of FIG.

The frame received by the lower interface controller 700 is checked for the frame CRC by the link controller 704 and stored in the reception buffer 706 (810). Further, the FC protocol control unit 707 receiving the frame storage notification from the link control unit 704
The input / output bus control unit 708 analyzes the frame and stores the frame data in the main memory 709 if necessary.
(811). Input / output bus control unit 7 receiving the instruction
08 stores the frame data from the reception buffer 706 into the main memory 709 (812), and upon detecting the end of storage, the FC protocol control unit 707 requests the central processing unit 710 to process the stored data (813). Finally,
The stored data is processed by the central processing unit 710 (81
4).

In the above interface control device,
When the FC-SB2 is operated, generation and checking of an IU composed of a plurality of frames and an SB_CRC added to data composed of one or a plurality of IUs are processed by the central processing unit 710 of the higher-level interface control device 701. The lower interface controller 700 divides the IU on the main memory 709 into frames and transmits the frame, assembles the received frame from the header information into an IU, and stores the frame in the main memory 709. FIG. 11 shows IU transmission, FIG.
FIG. 2 shows a flowchart of a control example of the conventional apparatus regarding IU reception.

However, as described above, in addition to the IU processing, the SB
If the generation and checking of _CRC are also processed by the central processing unit 710, the load on the central processing unit 710 increases, and the ULP control performance may be reduced due to the overhead of program execution.

Therefore, a method for improving the ULP control performance without adding a special mechanism such as a dedicated control mechanism for the SB_CRC to the upper interface controller 701 by generating and checking the SB_CRC in the lower interface controller 700 is provided. Think.

As described above, performing a part of the ULP processing in the lower layer means that the upper and lower layers are bound and processed, which contradicts the versatility and flexibility of the protocol based on the original layer structure. However, SAN (Storage Are
a) If the combination of upper and lower layer protocols can be limited within a specific range such as Network or Internet, it is considered to be a useful method for improving performance.

Data division / assembly and accompanying FC
Japanese Patent Application Laid-Open Nos. 9-149080 and 10-303945 disclose conventional examples of S, but do not describe processing of FCS in which upper and lower layers are bound.

[0019]

However, as described above,
If the generation and checking of the SB_CRC are processed by a microprogram, the load on the central processing unit 710 increases, and the ULP control performance may be degraded due to the overhead of executing the program. It is considered that the versatility of the host interface control device 701 is maintained while maintaining the ULP control performance by performing the process at 700.

When the SB_CRC is generated and checked by the lower interface control device 700, there are the following problems.

The first problem is that when the SB_CRC is processed by the FC protocol control unit 707, the data of the transmission / reception buffer is stored in the local memory 712 and calculated by a microprogram. What is needed is that the overhead of program execution is large. FIG. 13 shows the IU transmission,
FIG. 14 shows a flowchart of a control example of the conventional apparatus regarding IU reception.

The second problem is that a dedicated control mechanism for generating and checking the SB_CRC is used for transmitting and receiving buffers 705 and 706.
When adding before and after, considering the simultaneous operation of multiple ULPs, which is one of the features of Fiber Channel, and the fact that multiple data including SB_CRC can be transferred simultaneously, simply adding a circuit to generate and check That is, we can't cope.

The third problem is that since the lower interface controller 700 transmits and receives frames at a high bit rate of several gigabits / second, the processing time required for SB_CRC generation and checking cannot be ignored.

A first object of the present invention is to overcome the above first and second problems and to provide a method of generating and checking an SB_CRC which can flexibly cope with multiple operations of a data transfer protocol. It is in.

A second object of the present invention is to provide a method of generating and checking an SB_CRC which overcomes the above first and third problems and can reduce or ignore the processing time of the SB_CRC.

[0026]

The above object is achieved by combining microprogram processing and a dedicated control mechanism in a lower-level interface control device.

The lower-level interface control device of the present invention comprises:
Extend the data storage unit of the transmission buffer to the IU unit,
It is possible to request transmission of a microprogram in IU units. Further, the SB_CRC generation is triggered by the IU transmission trigger, and the SB_C
An SB_CRC calculation circuit for generating an RC, and an SB_CRC generation circuit including an SB_CRC generation register which holds a generation initial value and a generation result and which can be read and written by a microprogram, are performed asynchronously with IU transmission. The SB_CRC check is performed by an SB_CRC calculation circuit for checking the SB_CRC, and an SB_CRC check circuit including an SB_CRC check register that holds a check initial value and a check result and can be read and written by a microprogram. When transferring the configured IU to the main memory, the IU transfer is performed asynchronously with the IU transfer. That is, by simultaneously generating and checking the SB_CRC while transmitting and transferring the IU, the overhead related to the processing is reduced.

Further, by preparing a plurality of registers for storing information necessary for an IU transmission request of the microprogram and an IU transfer request to the main memory, a plurality of registers can be requested at the same time. It flexibly copes with the case where the transfer is executed in a multiplex manner.

Also, an IU is assembled from the received frame,
When transferring to the main memory, it is possible to indicate by the chain information of the reception buffer address of the frame,
No special memory is required for IU transfer, that is, the overhead of transferring to the same memory can be reduced.

The SB_CRC generation will be described briefly. In order to transmit frames correctly, the data read speed from the transmission buffer must be higher than the bit rate on the link. However, in this method, the transmission buffer that can read at twice or more the bit rate on the link is used. To reduce the overhead of SB_CRC generation. That is, while reading out the data of the transmission frame according to the bit rate on the link, the SB_CR
The C-generated data read is performed asynchronously, and the SB_CRC is generated by the dedicated control mechanism. In addition, as shown in FIG. 2A, a start and an end code (SOF, EOF), header information, a frame CRC, and the like are attached to a frame, and a predetermined interval must be provided between frames. If the transmission frame and the SB_CRC generation data are read asynchronously, the SB_CRC generation is completed first. Using this,
When the SB_CRC generation extends over a plurality of IUs, the result of the previously completed SB_CRC generation is set as an initial value of the SB_CRC generation in the next IU transmission, and the IU
Issuing a transmission request enables IU transmission without the overhead of SB_CRC generation.

The SB_CRC check will be described briefly. The frame stored in the reception buffer is assembled into the IU by the microprogram from the header information. The assembled IU is transferred to the higher-level interface control device via the input / output bus. Here, as in the case of the SB_CRC generation, the received IU can be read at twice or more the data transfer speed of the input / output bus. A buffer is mounted, and while reading data to the input / output bus, S
Data read of B_CRC check is performed asynchronously,
The SB_CRC is checked by the dedicated control mechanism. In this case as well, the SB_CRC calculation is completed earlier than the data transfer on the I / O bus due to the overhead of the data transfer protocol on the I / O bus. By setting an initial value of the SB_CRC check in the IU transfer of the
IU transfer becomes possible without the overhead of B_CRC check. Also, the IU transfer request at this time can be instructed in association with a frame position constituting the IU such as the reception buffer address ABEG.

As described above, the lower-level interface control device of the present invention uses the SB_
By performing a part of the ULP processing such as CRC generation and checking, the control performance of the ULP is improved.

FIG. 3 shows a control example of the above-mentioned SB_CRC check. Here, the data read speed of the receiving buffer is four times the data transfer speed of the input / output bus, and
Shows an example in which 4 frames and SB_CRC covers 2 IUs.

[0034]

Embodiments of the present invention will be described below in detail with reference to the drawings.

This embodiment is an example of a preferred embodiment of the fiber channel interface control in the present invention.
The present invention is not limited to this.

FIG. 1 is a block diagram of an interface control device showing an example of the interface control method of the present invention.
This configuration employs a 4-port memory that can be independently read and written by two ports for the transmission / reception buffer,
It is characterized in that read ports are allocated for data transfer and for generating and checking the SB_CRC, and each can operate asynchronously.

As shown in FIG. 1, the interface device controller is a lower interface controller 100 for controlling the lower layer of the fiber channel, as in the conventional example (FIG. 8).
And an upper interface control device 101 that performs other control including ULP, and both are connected by an input / output bus 102.

The lower interface controller 100 converts and controls the optical signal on the optical fiber cable 103 and the transmission / reception frame, a link control unit 104, stores the transmission / reception frame, and stores the transmission buffer 10 composed of a 4-port memory.
5. Receive buffer 106, SB_C attached to IU unit
SB_CRC generation circuit 11 for generating and checking RC
3. An SB_CRC check circuit 114, a FC protocol control unit 107 having a local memory 112 therein, which performs a lower layer protocol control of the Fiber Channel such as a frame transfer control of the Fiber Channel and an IU assembly by a microprogram; 108.

The transmission / reception buffers 105 and 106 are shown in FIG.
As shown in (a) and (b), the transmission buffer 105
The reception buffer 106 is divided into frames in units of U, and each area can be designated by a transmission buffer # and a reception buffer #.

The link control unit 104 has a link control register 115 for the FC protocol control unit 107 to store IU transmission control information. As shown in FIG. 5A, the link control register 115 includes transmission control information, start and end codes, frame header information, and transmission IU length, and further includes four link control registers corresponding to the transmission buffer #. Information can be stored. Upon receiving the IU transmission request from the FC protocol control unit 107, the link control unit 104 refers to the link control unit register 115, divides the IU into frames while reading data from the transmission buffer 105, and performs frame transmission. If the transmission control information of the link control register 115 has instructed the generation of the SB_CRC, the SB_CRC generation circuit 113 generates the SB_CRC of the IU. This frame transmission and S
B_CRC generation is performed from different read ports of the transmission buffer, and the operations of both are performed asynchronously.
If a plurality of link control registers 115 are set up, frame transmission, S
B_CRC generation is performed independently and continuously.

The input / output bus control unit 108 includes an FC protocol control unit 107,
Main memory 109 and transmission / reception buffers 105 and 106
There is a data transfer control register 116 for storing data transfer control information between them. The data transfer control register 116 stores, as shown in FIG.
The data transfer control register for the transmission buffer used to transfer the data 09 in the transmission buffer 105 and the data transfer control register for the reception buffer used to transfer the data in the reception buffer 106 to the main memory 109 can be divided. it can. For transmission buffer, transfer control information, transfer source (main memory) address, transfer length, transfer destination (transmission buffer address) offset, transmission buffer #, transfer control information, transfer destination (main memory) address for reception buffer , Transfer length, transfer source (address of the receiving buffer) offset, and receiving buffer # -chain information, each of which can store four data transfer control register information. The reception buffer # -chain information referred to here is information for performing data transfer from the reception buffer 106 to the main memory 109 in IU units, and can set up to four reception buffers #. For example, when the frames constituting the IU are stored in the order of the receiving buffers # 5, # 7, # 8, and # 0, the chain information # 5- # 7- # 8- # 0 may be set. The input / output bus control unit 108 transfers the IU to the main memory 109 while assembling the IU according to the chain information. As described above, in the present invention, the reception IU is handled by the chain information of the reception buffer # in which the frames constituting the IU are stored, and the IU transfer is enabled by the chain information. unnecessary. If the calculation of SB_CRC has been instructed by the transfer control information of the data transfer control register for the reception buffer, the SB_CRC check circuit 114 checks the SB_CR of the IU.
If the C calculation is further instructed and the SB_CRC check is instructed, the SB of the IU is checked. At this time, the data transfer and the SB_CRC check are executed from different read ports of the reception buffer, and the operations of both are performed asynchronously. When a plurality of reception buffer data transfer control registers are set up, data transfer and SB_CRC check are executed independently and continuously according to their priorities.

SB_CRC generation circuit 113, SB_CRC
The check circuit 114 includes four SB_CRC generation initial registers 117 and SB_CRC check initial registers 118 corresponding to the link control register 115 and the data transfer control register 116, respectively.
4 and the instruction from the input / output bus control unit 108, the SB_CRC calculation is started from the initial register value, and the calculation result is stored in the register. Further, this register can be read and written by a microprogram of the FC protocol control unit 107, and can flexibly cope with a change in the specification of the initial value of the SB_CRC. Further, when the calculation of the SB_CRC is performed a plurality of times,
The previous SB_CRC calculation result is temporarily stored in the local memory 11.
When the data that needs to be calculated is ready, the SB_CRC calculation result can be substituted into the initial register and the subsequent SB_CRC calculation can be performed. Can be handled.

The upper interface controller 101 has a structure in which the main memory 109 and the central processing unit 110 are connected to the lower interface controller 100 via the input / output bus controller 111, as in the conventional example (FIG. 8). ing.

Hereinafter, the data flow and the SB_CRC generation method in IU transmission will be described in detail with reference to the flowcharts of FIGS.

First, the upper interface controller 101
Prepared IU to be transmitted to the main memory 109 of (6)
00) The central processing unit 110 reports, via the input / output bus 102, to the FC protocol control unit 107 of the lower-level interface control device 100 that the IU transmission is ready (601).

Next, F which receives the report of the completion of the IU transmission preparation is received.
The C protocol control unit 107 secures an empty transmission buffer # from the transmission buffer 105 and stores the transmission buffer # and the offset address, the data transfer source address of the main memory 109, the data transfer length, and the transfer in the data transfer control register 116. The control information is set, and a data transfer request is made to the input / output bus control unit 108 (602). Upon receiving the data transfer request, the input / output bus control unit 108 controls the main memory 109 according to the data transfer control register 116.
And stores the data in the transmission buffer.
An end report is sent to the protocol control unit 107 (603). When the IU transmission preparation completion is continuously received, regardless of whether or not the previously requested data transfer is completed, the next transmission buffer # is secured, the register is set, and the next data transfer is requested. .

Next, upon generation of the data transfer completion report, the FC protocol control unit 107 stores the SB_CRC initial value in the SB_CRC generation initial register 117 corresponding to the transmission buffer # for which data transfer has been completed, if the generation and addition of the SB_CRC is necessary. Start of frame in link control register 115,
An end code, header information, IU length, transmission control information such as SB_CRC generation and addition are set, and an IU transmission request is made to the link control unit 104 (604). Upon receiving the IU transmission request, the link control unit 104 sets the link control register 1
According to No. 15, the IU is divided into frames and transmitted.
(605) Further, the SB_CRC is generated asynchronously with the frame transmission (606). In this embodiment, the transmission buffer 10
5, data is read from one port in accordance with the link bit rate, frame transmission is performed, and a frame CRC to be added for each frame is generated.
Reads data for B_CRC generation, SB_CRC
The generation circuit 113 generates SB_CRC.

When the addition of the SB_CRC to the transmission IU is requested, it is necessary to add the generated SB_CRC to the data portion of the last divided frame. As described in the section of the means for solving the problem, Because of the frame structure and the overhead of the frame transmission protocol, the generation of the SB_CRC ends before the frame transmission.
CRC can be added.

When the SB_CRC is generated across two IUs, the FC protocol control unit 107 transmits the first IU to the SB_CRC generation initial register 11.
7 and the link control register 115.
, The SB_CRC generation and the post-generation report are set in the transmission control information, and an IU transmission request is made to the link control unit 104. IU
Upon receiving the transmission request, the link control unit 104 asynchronously performs frame transmission and SB_CRC generation, and
When the CRC generation is completed, the FC protocol control unit 1
07 reports the generated SB_CRC. SB_CRC
FC protocol control unit 107 receiving the report of the generation end
Before the completion of the previously requested IU transmission, the SB_CRC corresponding to the transmission buffer # in which the next IU is stored.
The SB_CRC value reported to the generation initial register 117 is added to the transmission control information of the link control register 115 as SB_CRC.
CRC generation and addition are set, and I
A U transmission request is made. In the link control unit 104, although the previously requested IU transmission has not been completed, the next SB_C
Since the RC generation can operate asynchronously, the SB_CRC generation circuit 113 generates the next SB_CRC. When the previous IU transmission is completed, the link control unit 104 subsequently starts the next IU transmission, and the frame is transmitted without interruption on the link.

As described above, when the SB_CRC is generated by the lower-level interface control device and the IU is transmitted, the data constituting the SB_CRC and the IU transmission are asynchronously read from the transmission buffer so that the frame constituting the IU can be generated without the overhead of the SB_CRC generation. Can be sent.

Next, using the flowcharts of FIGS. 1 and 7, the IU is constructed from the reception of the frame, and further, the flow of data for transferring the IU to the higher-level interface control device and the SB.
The _CRC check method will be described in detail.

The signal input from the optical fiber cable 103 to the lower-level interface control device 100 is constructed into a frame by the link control unit 104, and the reception buffer 106
Is stored in Further, the reception buffer # is reported to the FC protocol control unit 107. When stored in the reception buffer 106, the frame CRC added in frame units is checked by the link control unit 104 (61).
0). Upon receiving the frame reception report, the FC protocol control unit 107 refers to the header part, the start and end codes of the frame stored in the reported reception buffer #, and the pass / fail of the frame CRC checked by the link control unit 104. And the correctness, type and structure of the frame,
The LP is determined (611). If the received frame is one of the frames constituting the IU, the FC protocol control unit 107 stores the reception buffer # of the frame in the local memory 112 and keeps the upper interface controller 101 until all the frames constituting the IU are received. (612). Since the above determination is made by the microprogram of the FC protocol control unit 107, the UL
It is possible to flexibly respond to a change in the specification of P or a new ULP.

When all the frames constituting the IU are received, and the IU includes the SB_CRC, the FC protocol control unit 107 stores the reception buffer stored in the local memory 112 in the reception buffer data transfer control register 116. # Chain information and offset address,
The data transfer destination address, the data transfer length, and the transfer control information of the main memory 109 are set in the corresponding SB_CRC check initial register 118 with the SB_CRC initial value,
A data transfer request is made to the input / output bus control unit 108 (61
3).

Upon receiving the data transfer request, the input / output bus control unit 108 chains the reception buffer # according to the data transfer control register 116 to assemble the IU,
Is transferred to the main memory 109 (614), and SB_C
The RC calculation is performed asynchronously with the IU transfer (615). In the present embodiment, data is read from one port of the reception buffer 106 in accordance with the transfer rate of the input / output bus, IU transfer is performed, and data for SB_CRC calculation and check is read from the other port, and an SB_CRC check circuit is read. At 114, the SB_CRC is calculated and checked.

If the SB_CRC extends over two IUs, the FC protocol control unit 107 receives all frames constituting the first IU, and
The initial value of the SB_CRC is set in the RC check initial register 118, the chain information of the reception buffer #, the SB_CRC calculation, and the transfer control information of the post-calculation report are set in the data transfer control register 116, and an IU transfer request is made to the input / output bus control unit 108. . I / O bus control unit 1 receiving an IU transfer request
In 08, the IU transfer and the SB_CRC calculation are performed asynchronously, and when the SB_CRC calculation of the IU is completed, F
The calculated SB_CRC is reported to the C protocol control unit 107. The FC protocol control unit 107, having received the report of the completion of the SB_CRC calculation, returns the SB_CRC check initial register 11 if the reception of all the frames constituting the next IU has been completed, even if the previously requested IU transfer has not been completed.
8 is set in the data transfer control register 116 with the transfer information of the reception buffer # constituting the next IU and the transfer control information of the SB_CRC calculation and check in the data transfer control register 116, and the IU transfer request is sent to the input / output bus control unit 108. I do. In the input / output bus control unit 108, the previously requested IU
Although the transfer has not been completed, the next SB_CRC calculation can operate asynchronously, so the SB_CRC check circuit 1
At 14, the next SB_CRC calculation and check are performed.
When the previous IU transfer is completed, the I / O bus control unit 108 subsequently starts the next IU transfer, and
2 can efficiently transfer data.

As described above, when the SB_CRC check is performed in the IU transfer of the lower interface controller, the IU transfer is performed asynchronously with the SB_CRC check data and the IU transfer read from the reception buffer. Can be forwarded to

The case where the IU (control unit of the upper protocol) is composed of a plurality of frames (control unit of the lower protocol) like SB_CRCB2 has been described in detail, but the present invention is not limited to this. It goes without saying that the present invention can be applied to a data transfer system in which the control unit of the upper protocol is constituted by a plurality of control units of the lower protocol.

[0058]

[Effect of the Invention] SB_CRC of IU over a plurality of frames
By performing the calculation asynchronously with the data transfer when the data transfer request is triggered, the overhead of the SB_CRC calculation can be eliminated, and the data transfer can be performed at the maximum performance.

Further, by allowing a plurality of data transfer requests to be set, the IU chain and its SB_CR
Even when C calculation is required, data transfer can be performed with maximum performance.

By making it possible to write and read the initial value and the result of the SB_CRC calculation by a microprogram,
It is also possible to flexibly cope with a change in the specification of the SB_CRC calculation and a case where the SB_CRC calculation needs to be multiplexed.

When an IU assembled from a received frame is processed, the IU can be processed using the chain information of the storage buffer # of the received frame, so that a dedicated memory for assembling the IU is not required.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of an interface control device of the present invention.

2A is a diagram illustrating a frame structure of an interface according to the present invention, FIG. 2B is a diagram illustrating an information unit structure of an interface according to the present invention, and FIG. 2C is a diagram illustrating an SB data structure of the interface according to the present invention; FIG.

FIG. 3 is a diagram illustrating an example of an interface control method according to the present invention.
FIG. 7 is a diagram illustrating an operation example of RC check control.

FIG. 4A is a configuration diagram of a transmission buffer according to the embodiment, and FIG. 4B is a configuration diagram of a reception buffer according to the embodiment.

5A is a configuration diagram of a link control register according to the embodiment, FIG. 5B is a configuration diagram of a data transfer control register according to the embodiment, and FIG. 5C is an SB_CRC according to the embodiment;
FIG. 9D is a configuration diagram of a generation initial register, and FIG.
It is a block diagram of a B_CRC check initial register.

FIG. 6 is a flowchart illustrating a method of transmitting an IU and generating an SB_CRC in the embodiment.

FIG. 7 is a flowchart illustrating an IU reception and an SB_CRC check method according to the present embodiment.

FIG. 8 is a configuration diagram showing a conventional example of an interface control device according to the present invention.

FIG. 9 is a flowchart showing a frame transmission control method in FIG.

FIG. 10 is a flowchart showing a frame reception control method in FIG.

FIG. 11 is a flowchart showing an IU transmission control method when SB_CRC generation is realized by a central processing unit in FIG.

FIG. 12 is a flowchart showing an IU reception control method when the SB_CRC check generation is realized by the central processing unit in FIG.

FIG. 13 is a flowchart showing an IU transmission control method when SB_CRC generation is realized by the FC protocol control unit in FIG.

FIG. 14 is a flowchart showing an IU reception control method when the SB_CRC check generation is realized by the FC protocol control unit in FIG.

[Explanation of symbols]

100: lower interface control device, 101: upper interface control device, 102: input / output bus, 103:
Optical fiber cable, 104 ... Link control unit, 105 ...
Transmission buffer, 106: reception buffer, 107: FC protocol control unit, 108: input / output bus control unit, 109 ...
Main memory, 110 central processing unit, 111 input / output bus control unit, 112 local memory, 113 SB_
CRC generation circuit, 114 ... SB_CRC check circuit,
115: link control register, 116: data transfer control register, 117: SB_CRC generation initial register, 1
18: SB_CRC check initial register, 200: frame, 201: information unit, 202: SB data,
700: lower interface controller, 701: upper interface controller, 702: input / output bus, 703
Optical fiber cable, 704 ... link control unit, 705 ...
Transmission buffer, 706: reception buffer, 707: FC protocol control unit, 708: input / output bus control unit, 709 ...
Main memory, 710: central processing unit, 711: input / output bus control unit, 712: local memory.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B014 GA02 GA17 GC22 GC28 5B077 AA24 DD01 DD22 MM03 5K034 AA11 BB01 DD01 EE02 FF01 GG05 HH10 HH21 KK07 MM08

Claims (9)

[Claims] 1. An interface control device capable of performing a data transfer operation in a multiplex manner on a frame basis, comprising an interface for controlling a data transfer protocol in which one check code is attached to data information composed of a plurality of frames. In the control device, the interface control device includes: a transmission buffer for storing transmission data information; a protocol control unit operable by a microprogram;
A first counting circuit for generating the check code, a check code generation circuit configured to hold a generation initial value and a generation result, and include a first register readable and writable by the microprogram. Interface controller. 2. An interface control device for controlling the data transfer protocol, wherein the interface control device checks a reception buffer for storing a reception frame, a protocol control unit operable by a microprogram, and the check code. And a check code check circuit which holds a check initial value and a check result and comprises a second register readable and writable by the microprogram. . 3. An interface control device for controlling the data transfer protocol, wherein the interface control device is operable by a microprogram, a transmission buffer for storing transmission data information, a reception buffer for storing a reception frame. A protocol control unit, a first counting circuit for generating the check code, holding a generation initial value and a generation result, a check code generation circuit including a first register readable and writable by the microprogram, A second counting circuit for checking the check code, a check code check circuit for holding a check initial value and a check result, and including a second register readable and writable by the microprogram. Interface controller. 4. The interface control device according to claim 1, further comprising a third register which stores information necessary for performing data transmission from said transmission buffer and is readable and writable by a microprogram. An interface control device, wherein a microprogram sets the first and third registers and requests data transmission, so that check code generation and data transmission are performed asynchronously. 5. The interface control device according to claim 2, further comprising a fourth register that stores information necessary for performing data transfer from said reception buffer and is readable and writable by a microprogram. An interface control device characterized in that a microprogram sets the second and fourth registers and requests data transfer, so that check code check and data transfer are performed asynchronously. 6. The interface control device according to claim 3, wherein information necessary for performing data transmission from the transmission buffer is stored, and a third register readable and writable by a microprogram, and the reception buffer. A fourth register that stores information necessary to perform data transfer from and is readable and writable by a microprogram, the microprogram sets the first and third registers,
By requesting data transmission, the check code generation and data transmission are performed asynchronously, the microprogram sets the second and fourth registers, and requests data transfer, thereby checking the check code and performing data transfer. The interface control device performs asynchronously and operates independently. 7. The interface control device according to claim 4, further comprising a plurality of said first registers and said third registers for continuously transmitting data from said transmission buffer. An interface control device that performs check code generation and data transmission independently and continuously in accordance with information stored in the register by requesting a plurality of check codes. 8. The interface control device according to claim 5, further comprising a plurality of said second registers and said fourth registers in order to continuously transfer data from said reception buffer. An interface control device, wherein a check code check and a data transfer are independently and continuously processed in accordance with information stored in the register by requesting a plurality of commands. 9. The interface control device according to claim 5, wherein the frame forming data information is stored when the fourth register is set by a data transfer request from the reception buffer. An interface control device for setting a plurality of addresses of the reception buffer described above.