JPH05347650A - Data reception system and communication controller - Google Patents

Abstract

PURPOSE:To reduce a reception processing time at the reception of a frame by starting protocol processing and transfer of received data to a computer in response to a coincidence signal between a predicted header and a received header from a comparator circuit. CONSTITUTION:Plural prediction headers of a frame expected for succeeding reception are registered to a communication controller 2 and data received from a network 3 are fetched in real time. Then a comparator circuit 100beta compares the plural fetched prediction headers with the received data simultaneously to discriminate whether or not the received data are registered in the prediction headers. Protocol processing and the transfer of the received data to a computer 1 are started in response to a coincidence signal between the prediction header and the received header outputted from the comparator circuit 100beta. Thus, three ways of processing such as frame reception from the network 3, protocol processing and transfer processing of the received data to the computer 1 are overlapped respectively to reduce the entire reception processing time of the controller 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving system and a communication control device, and more particularly to a high speed data receiving process in a communication control device for connecting a device such as a computer to a communication network.

[0002]

2. Description of the Related Art In a data communication system, as a method for speeding up communication protocol processing at the time of data reception, there is, for example, "protocol high speed processing method and network system" described in Japanese Patent Application No. 1-57701. In the invention described in the above publication, when a frame is received, the protocol header composed of a plurality of header elements is not sequentially analyzed for each header element, but the header of a frame previously transmitted by the local station or the local station Based on the header of the frame received in, the header of one or multiple layers for the frame that will be received next is collectively predicted, and when the frame is actually received, the received header and the predicted header are collectively By comparing, the header analysis process for the received frame is speeded up (hereinafter, the conventional invention is referred to as a header prediction method).

Further, as another technique for accelerating the protocol processing at the time of receiving data, there is a "communication control device" described in JP-A-62-164345. The invention described in the above publication does not start the protocol processing after the frame reception from the network is completed, but detects the reception completion of a fixed length of data (header portion) by hardware, and detects the timing. It is considered that the reception of the protocol header is completed, and the protocol header analysis process by the microprogram is started before the completion of the frame reception, so that the protocol processing time at the time of frame reception is shortened.

[0004]

In an environment in which a computer communicates with a plurality of computers at the same time, a plurality of prediction headers will exist. For example, when header prediction is performed for each connection set in the transport layer, there are prediction headers for the number of connections. In such a case, according to the header prediction method described in Japanese Patent Application No. 1-57701, when a frame is received, the connection identifier is extracted from the transport header in the received frame, and the prediction header to be compared is extracted. Need to be identified.

In addition, the transport protocol class 4 (TP) of the OSI protocol used in the LAN environment
4), connectionless network protocol (C
LNP), Logical Link Control Type 1 (L
In the combination of LC type 1), the header of the network layer preceding the transport header has a variable length, and the header analysis of the network layer is essential to extract the connection identifier. That is, in order to specify a prediction header to be compared from a plurality of prediction headers, there is a problem that the protocol header must be sequentially analyzed from the lower layer.

That is, in the header prediction method described in Japanese Patent Application No. 1-57701, when a plurality of headers to be predicted are present, the target prediction header is specified by sequentially comparing the plurality of prediction headers. Must be
There is room for improvement in terms of speeding up.

On the other hand, the method disclosed in Japanese Patent Laid-Open No. 62-164345, which starts the analysis processing of the protocol header before the completion of the frame reception, does not analyze the protocol header for the protocol whose header is variable length. , It is difficult to accurately extract the reception completion timing of the protocol header by hardware, and since the protocol header once stored in the buffer memory is analyzed by the microprogram, it is possible to improve the speedup. There is room for it.

It is an object of the present invention to provide a frame reception system and a communication control device in which protocol processing at the time of frame reception is speeded up.

Another object of the present invention is to provide a frame reception system and a communication control device in which the protocol header analysis processing is speeded up regardless of the number of predicted headers.

[0010]

In order to achieve the above object, according to the present invention, three processes, that is, frame reception from a network, protocol processing, and transfer processing of received data to a computer are overlapped, and communication is performed. It is characterized in that the reception processing time of the entire control device is shortened.

Another aspect of the present invention is to predict the header of the frame that will be received next based on the header of the frame that the station has previously transmitted or the header of the frame that the station has previously received. When a frame is actually received, a plurality of predicted headers that match the received header are searched at high speed to speed up the protocol header analysis processing regardless of the number of predicted headers.

According to another aspect of the present invention, when a protocol having a variable length or a plurality of protocols having different header lengths is handled, the reception completion timing of the protocol header is accurately extracted and the protocol header is temporarily stored in the buffer memory. This is to speed up the protocol processing at the time of frame reception by analyzing the protocol header being received by hardware in real time without storing it. More specifically, the communication control device according to the present invention includes a microprocessor for executing communication control processing, a buffer memory for temporarily storing transmission / reception data, a main memory in a computer, and a data transfer between the buffer memory. A DMA controller for controlling the transfer of
It has a LAN controller for controlling connection with a LAN and a computer interface circuit. Further, in order to increase the speed, the internal bus has a bus for transferring the transmission / reception data and a bus used by the microprocessor for the communication control processing, and is provided with the following means.

(A): A frame (predicted header) and a predicted header length which are created based on the header of a frame previously transmitted by the self station or the header of a frame previously received by the self station and are expected to be received next. Multiple registered headers can be registered, and while simultaneously capturing the received data received from the network, the means for simultaneously comparing the registered predicted headers and the received data, and the predicted header lengths and the number of received data at the time of comparison can be A means to compare.

(B): Based on the comparison result of the means (a),
Means for outputting a signal indicating a match between the predicted header and the received header and an identifier of the matched predicted header.

(C): Means for activating the DMA controller and starting the transfer of the received data to the computer in response to the coincidence signal and the header identifier output from the means (b).

(D): When the reception of the frame from the network is completed, the reception abnormality is checked, and if the reception abnormality occurs, the reception frame is discarded and the state of the communication control processing is returned to the state before the frame reception. means.

[0017]

By means of the means (a), by simultaneously comparing the received header and a plurality of prediction headers, the protocol header analysis processing can be speeded up regardless of the number of prediction headers. Further, by comparing the predicted length of the header and the number of received data, the reception completion timing of the protocol header can be accurately extracted by hardware even for a protocol having a variable length protocol header. Furthermore, by comparing the predicted header with the received data received from the network, the protocol header being received can be analyzed in real time without temporarily storing the protocol header in the buffer memory.

By means (b) and (c), frame reception from the network and transfer of the received data to the computer can be performed in an overlapping manner.

By means (a), (b), and (c), the three processes of frame reception from the network, protocol processing, and transfer processing of received data to the computer that occur in the communication control device are made to overlap. Therefore, the reception processing time of the entire communication control device can be shortened.

By the means (d), it is possible to prevent the trouble caused by the start of the protocol processing before the frame reception is completed.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment 1] First, an outline of a system on which the present embodiment is based will be described.

FIG. 2 shows an example of a communication network system according to the present invention, which comprises a plurality of computers 1 (1A-1D).
Are respectively connected to the network 3 via the communication control devices 2 (2A to 2D).

FIG. 3 is a block diagram showing an example of the configuration of the communication control device 2 when a local area network (LAN) is applied as the network 3.

The communication controller 2 is connected to the system bus 6 in the computer 1. The computer 1 comprises a main processor 4 and a main memory 5 connected by the system bus 6.

The communication control device 2 includes a microprocessor 10 for executing communication control processing and a program memory 20.
A local memory 30, a header prediction circuit 100α which is a main part of the present invention, a buffer memory 40 for temporarily storing transmission / reception data, a main memory 5 in the computer 1,
A DMA controller 50 (hereinafter, referred to as a DMAC 50) that controls data transfer with the buffer memory 40.
And a LAN controller 6 for controlling connection with the LAN
0 and a computer interface circuit 70.

The internal bus of the communication control device 2 is composed of two internal buses. One is a data bus 90 (90A, 90B) to which transmitted / received data is transferred, and the other is
A control bus 80 to which the microprocessor 10 is connected and which performs communication control processing.

The header predicting circuit 100α is a circuit for rapidly searching a plurality of predictive headers which are expected to be received next, for a match with the actually received header. The buffer memory 40 forms a 3-port memory, and the DMAC5
0, LAN controller 60, microprocessor 10
It is configured so that they can be accessed simultaneously from. The header prediction circuit 100α, the DMAC 50, and the LAN controller 60 are controlled by the microprocessor 10.

When the microprocessor 10 receives the data transmission request from the computer 1, the microprocessor 10 transfers the transmission data stored in the main memory 5 to the buffer memory 40 by using the DMAC 50, performs the protocol processing, and then the LAN controller 60. It is activated and sends a frame to the network 3. On the other hand, when the data reception notification is received from the LAN controller 60, protocol processing is performed and then the DMAC 50
To transfer the received data to the main memory 5 and notify the computer of the data reception.

FIG. 4 is a diagram showing a hierarchy of communication protocols executed by the computer 1 and the communication control device 2. In this embodiment, with respect to the OSI protocol consisting of 7 layers, layers 5 (presentation layer) and above are executed by the main processor of the computer, and layers 4 (transport layer) to layer 2 (LLC sublayer) are communication control devices. Two
It is executed by the microprocessor 10 in the layer 2 (MA
C sublayer) The following is executed by the LAN controller 60 in the communication control device 2.

FIG. 5 is a diagram showing a format of a frame exchanged between the communication control devices 2. The data 46 transferred between the computers 1 includes headers below the layer 4 (TL header 45, NL header 44, LLC header 4).
3, MAC header 42, PHY header 41) and trailer 47 are added to form one frame 48.

TL header 45, NL header 44, LLC
The header 43 is processed by the microprocessor 10 in the communication control device 2, and the MAC header 42, the PHY header 41, and the trailer 47 are processed by the LAN controller 60.

FIG. 6 shows the main header formats of TP4, CLNP, and LLC type 1, which are mainly used in the LAN environment among the layers 4 to 2 (LLC sublayer) of the OSI protocol processed by the microprocessor 10. It is the figure which showed (a)-(h).

FIG. 7 is a diagram showing an example of a communication sequence of the OSI transport protocol (TP4) and a header prediction procedure in the data receiving station (communication control device 2B). The communication control device 2 performs the C
The R packet 500, the CC packet 501, and the AK packet 503 are transmitted and received to set the connection. D which will be received first when connection setting is completed
The headers from layer 4 to layer 2 (LLC sublayer) of the T packet 502 are collectively predicted, and when the DT packet 502 is received, the predicted header and the received header are collectively compared. If the received header and the predicted header match, the received packet is a normal packet.

That is, according to the header prediction method of the present invention, the received header can be analyzed by comparing the predicted header with the received header. If the received header matches the predicted header, AK packet 503 is sent if necessary.
Is returned, and the prediction header is updated in preparation for the next data reception. For example, the sequence number indicating the packet transfer order is updated. When the data transfer is complete,
The DR packet 504 and the DC packet 505 are transmitted and received to release the connection.

FIG. 8 is a block diagram showing an example of the structure of a header predicting circuit 100α having a function of rapidly searching a plurality of predictive headers that match the received header. The header prediction circuit 100α is composed of a plurality of entries and a registration / search control circuit 160, and each entry is
An n-byte wide prediction header register 110 (110A, 110B) for storing a prediction header and an n-byte width reception header register 150 for storing a reception header
(150A, 150B) and a header comparator 120 (120A, 120) for comparing the predicted header with the received header.
B) and an n-byte width mask register 140 (140) for holding mask data designating an area (a portion that cannot be predicted, a padding portion for a prediction header of n bytes or less, etc.) that is not a target for comparison in the header comparison.
A, 140B) and a mask circuit 130 (130A, 130B) for supplying the data obtained by masking the contents of the reception header with the mask data to the header comparator 120.

In response to a command from the microprocessor 10, the registration / retrieval control circuit 160 registers the predicted header, retrieves the registered predicted headers that match the received header, and registers the predicted header. Delete the prediction header that exists.

FIG. 9 is a block diagram showing an example of the configuration of the registration / search control circuit 160.

The registration / search control circuit 160 has a command register 160-1 for holding a command for the header prediction circuit 100α and a prediction header registration register 160-2 for temporarily holding a prediction header to be registered.
A mask data registration register 160-3 for temporarily holding the mask data to be registered, a header identifier register 160-4 for holding a prediction header identifier for identifying the prediction header, and received data (header) Header input register 160 for temporarily holding the
5 and status register 1 for holding search results
60-6 and an entry selected based on the contents of the header identifier register 160-4 are added to the comparison permission signal 162.
(162A, 162B) and prediction header 161 (161
A, 161B) and mask data 164 (164A, 16A)
4B), an OR circuit 160-12 for taking the logical sum (OR) of the match signals 163 (163A, 163B) of the predicted header and the received header output from each entry, and A coder 160 that encodes the match signal 163 and converts it into the number of the matched entry.
-13, and a matching header notification register 160-7 that holds the number of the matching entry as a predicted header identifier,
The microprocessor 10 includes an interrupt generation circuit 160-14 for generating an interrupt and a controller 160-8 for controlling the above hardware.

In this embodiment, the registration / retrieval control circuit 160
Is configured so that the predicted header identifier is equal to the entry number.

FIG. 10 shows a flowchart relating to the header prediction process performed by the communication control device 2.

After setting up the connection between the communication control devices 2, the microprocessor 10 predicts the header, the mask data and the above-mentioned predictive header for the layer 4 to the layer 2 (LLC sublayer) of the data packet to be received first for the connection. A prediction header identifier for the prediction header is created (step 200), and the header prediction circuit 100 is created.
Register to α (201). Next, in the reception processing definition table 31 shown in FIG. 11 defined in the local memory 30, reception processing other than the above-mentioned predicted header identifier and header analysis processing is registered (202), and the reception of a frame is awaited (20).
3).

When the frame reception completion notification is received from the LAN controller 60, it is checked whether there is any reception abnormality (204). If there is no reception abnormality, data of n bytes from the head of the data received in the reception buffer 40 is checked. The data is read, set in the reception header input register 160-5 in the header prediction circuit 100α, and a search command is issued (205).

If the search results match, the predicted header identifier is fetched from the matched header notification register 160-7, and the reception processing corresponding to the predicted header is set to the reception processing definition table 3
It is calculated from 1 and executed (207). When the protocol processing is completed, the prediction header is updated in preparation for the next data reception,
It is again registered in the header prediction circuit 100α (21
0). Next, the DMAC 50 is activated to transfer the received data to the computer 1 (211), and when the data transfer to the computer 1 is completed (212), the computer is notified of the data reception (213).

On the other hand, if there is an abnormal reception in step 204, the received frame is discarded (208). In step 206, if the search results do not match, that is, if the received header does not match any predicted header, the received header is sequentially analyzed and protocol processing is performed (209).

FIG. 12 is a flowchart showing the operation of the header prediction circuit 100α.

The registration / retrieval control circuit 160 judges the contents of the command register 160-1 (step 220),
If it is a prediction header registration request, the prediction header and mask data are transferred to the prediction header register 110 and the mask register 140 in the entry designated by the header identifier register 160-4, and the comparison permission signal 162 is turned on ( 227). If it is a request to delete the prediction header (22
1), the comparison permission signal 162 of the specified entry is OF
Set to F (228). If it is a search request (222), the contents of the reception header input register 160-5 are transferred in parallel to the reception header register 150 of each entry, and the comparison request signal 166 is turned on to the header comparator 120 (22).
3).

The header comparator 120 masks the contents of the reception header register 150 with the contents of the mask register 140, and compares the masked value with the contents of the prediction header register 110 (224). The match signal 163 from the header comparator 120 is checked by the OR circuit 160-12 (225). If there is an entry for which the match signal 163 is output, a code indicating the match is set in the status register 160-6, and the coder is set. A prediction header identifier is generated from the match signal 163 by 160-13 and set in the match header notification register 160-7.
An interrupt is generated for 0 (226). On the other hand, if there is no matching entry, the status register 1
A code indicating a mismatch is set in 60-6, and an interrupt is generated (229).

According to the above operation flow chart, the frame receiving operation in the communication control device 2 is performed as shown in the time chart of FIG.

In the above embodiment, the header prediction circuit 1
The timing at which the predicted header is first registered with 00α is after the connection is set, but this may be predicted based on any rule.

Regarding the registration / retrieval of the prediction header, the prediction header registered in the header prediction circuit 100α does not need to be the header itself. For example, when the packet including the header is encrypted and transferred, the encryption is performed. The predicted header may be registered and the encrypted received header may be compared without being decrypted.

According to this embodiment, even when the number of prediction headers is large, the header prediction circuit 100α can speed up the matching of the received headers from the plurality of prediction headers regardless of the number of prediction headers. Since the search can be performed, the header prediction process can be speeded up.

[Embodiment 2] In Embodiment 1 described above, FIG.
As can be seen from the operation sequence shown in FIG. 3, the frame reception from the network, the protocol process, and the transfer process of the received data to the computer performed by the communication control device 2 are sequential, and there is room for further improvement.

The second embodiment of the present invention is characterized in that the above-mentioned three processes which occur in the communication control unit 2 at the time of frame reception are overlapped with each other to further shorten the reception processing time of the entire communication control unit. ..

FIG. 1 is a block diagram showing the configuration of the communication control device 2 having the overlap execution function. In this embodiment, the header prediction circuit 100β is arranged between the two internal buses 80 and 90 so that the received data transferred from the LAN controller 60 to the buffer memory 40 can be fetched in real time. The header prediction circuit 100β starts capturing the received data in response to the frame receiving signal 61 output from the LAN controller 60.

FIG. 14 is a block diagram showing the structure of the header prediction circuit 100β. Header prediction circuit 100β
Has a configuration in which a reception header transfer control circuit 170 is further added to the configuration of the header prediction circuit 100α shown in FIG. The reception header transfer control circuit 170 responds to the in-frame receiving signal 61 obtained from the LAN controller 60, and the LAN controller 60 causes the buffer memory 40
Received data transferred to the real time is received, and the received data is received header register 1 in each entry.
It has a function of parallel transfer to 50.

15 and 16 are flow charts showing the operation of the communication control device 2 in this embodiment. Figure 15
In, the process of predicting the received frame and registering the predictive header in the header predicting circuit 100β (step 20
0 to 201) are the same as in the first embodiment.

When the registration of the prediction header is completed, the microprocessor 10 receives the reception process definition table 3 shown in FIG.
In 1α, after registering the predictive header identifier and the corresponding receiving process in preprocessing and postprocessing separately (step 300), the predictive header match interrupt from the header predicting circuit 100β,
Alternatively, it waits for a reception completion interrupt from the LAN controller 60 (301, 203).

When an interrupt is received from the header prediction circuit 100β, a preprocess corresponding to the matching predicted header is obtained from the reception process definition table 31α and executed (30).
2). In the next step, in the prediction completion frame registration table 32 shown in FIG.
The prediction header identifier is registered (303), the prediction header is updated in preparation for the next data reception, and it is registered again in the header prediction circuit 100β (210). Next, the DMAC 50 is activated and the transfer of the received data to the computer 1 is started (21
1), wait for the completion of frame reception (203).

When a frame reception completion interrupt is received,
In step 204 of FIG. 16, it is checked whether there is any abnormal reception. If there is no reception abnormality, it is checked whether or not the received frame is registered in the prediction completion frame registration table 32 (305). If registered, post-processing for the received frame is performed from the reception process definition table 31α. More requested and executed (306). Next, the received frame is deleted from the prediction completion frame registration table 32 (307), and the completion of the transfer of the received data to the computer 1 by the DMAC 50 is waited (212). When the transfer to the computer 1 is completed, the computer 1 is notified of the data reception (213).

In step 204, if there is an abnormal reception, it is checked whether the received frame is registered in the prediction completion frame registration table 32 (308), and if it is registered, it is already executed. The pre-processing is returned to the state before execution (309), and the received frame is deleted from the prediction completion frame registration table 32 (310). Next, the received abnormal frame is discarded (208).

In step 308, if the received abnormal frame is not registered in the prediction completion frame registration table 32, the received frame is discarded without doing anything (2
08). In step 305, if the received frame is not normally registered in the prediction completion frame registration table 32 despite normal reception, the received frame is sequentially analyzed and protocol processing is performed as usual (209).

FIG. 19 shows a flowchart of the operation executed by the header prediction circuit 100β in this embodiment. Operation related to registration / deletion of prediction header (step 220,
221, 227, 228) are the same as in the first embodiment.

The reception header transfer control circuit 170 is a LAN
Frame receiving signal 6 output from the controller 60
When the reception start of the frame is detected by 1 (320),
Takes in one word of data flowing on the data bus 90B and transfers it in parallel to the reception header register of each entry,
When the size of the reception header register reaches n bytes, the reception of the reception data is stopped, and the comparison request signal 166 is output to the header comparator 120 of each entry (321).

The header comparator 120 of the entry in which the prediction header is registered has data obtained by masking the contents of the reception header register 150 with the contents of the mask register 140,
The contents of the prediction header register 110 are compared (22
4).

The registration / retrieval control circuit 160 checks the match signal 163 from each entry (225), and if there is an entry in which the predicted header and the received header match, a code indicating the match is sent to the status register 160-6. After setting and setting the prediction header identifier in the match header notification register 160-7, an interrupt is generated in the microprocessor 10 (226).

FIG. 20 shows a reception header transfer control circuit 170.
3 is a block diagram showing the configuration of FIG.

The reception header transfer control circuit 170 receives the reception data flowing through the data bus 90B from the header prediction circuit 100.
a data fetch circuit 170-1 for fetching into β,
The frame reception start timing generation circuit 170-6 for extracting the frame reception start timing from the frame receiving signal 61, the reception data counter 170-5 for counting the number of words of the reception data, and the header prediction circuit 100β. Reception header register length 170-4 for designating the number of data to be fetched, and reception data counter 1
70-5 and a reception header register length 170-4, a comparator 170-3 for comparing the data, an OR circuit 170-7 for generating a timing of the end of data acquisition, and a comparison for the header comparator 120 of each entry. Request signal 16
6 is formed by the comparison request signal generation circuit 170-2.

FIG. 21 shows the reception header transfer control circuit 1 described above.
7 is a flowchart showing a detailed operation of 70.

Frame reception start timing generation circuit 17
When the reception start of the frame is detected from the frame reception signal 61 (330), 0-6, the reception data counter 17
Clear 0-5 (331). The comparison request signal generation circuit 170-2 turns off the comparison request signal 166 (3
32). The data fetch circuit 170-1 fetches one word of received data flowing through the data bus 90B and transfers it in parallel to the receive header register 150 of each entry (3
33).

The reception data counter 170-5 counts up the number of reception data (334). Steps 333 and 334 are repeated until the number of received data reaches the reception header register length (n) or the reception of the frame is completed. The comparator 170-3 receives the contents of the reception data counter 170-5 and the reception header register length 170-
4 is compared (335), and when the number of received data reaches the received header register length, the reception of the received data is stopped (339), the comparison request signal 166 is issued to the header comparator 120 (340), and the frame Wait for reception completion (3
41). If the reception of the frame is completed even before the number of received data reaches the length of the received header register, the reception of the received data is stopped (337) and the header comparator 120
A comparison request signal 166 is issued to (338).

FIG. 22 is a time chart showing the operation of the header prediction circuit 100β based on the above flow. Figure 2
2, when the number of received data reaches the reception header register length (n), the reception header transfer control circuit 170
Outputs a comparison request signal 166 to the header comparator 120, outputs a match signal 163 from an entry in which a predicted header that matches the received header is registered, and the analysis processing of the predicted header is completed.

FIG. 23 shows a time chart when the communication control device 2 in the present embodiment receives a frame.

According to this embodiment, the reception protocol header can be analyzed in real time by the header prediction circuit 100β without storing the protocol header in the buffer memory once. In addition, the communication control device 2
Since the three processes of the data reception from the network, the protocol process, and the transfer of the received data to the computer that occur in 1) can be processed by overlapping with each other, there is an effect that the reception processing time of the entire communication control device can be shortened.

[Third Embodiment] The header prediction circuit 100β described in the second embodiment has a length (n) of the reception header register 150.
Since the comparison with the predicted header is started after the received data of (bytes) has been fetched, in a protocol with a variable header length, if the predicted header is n bytes or less, it becomes n bytes. It is necessary to make the header analysis process wait until it reaches.

The third embodiment described below is characterized in that, in a protocol having a variable length header, the timing when the reception of the protocol header is completed is accurately extracted by hardware, and the header analysis process can be started. And

FIG. 24 is a block diagram showing the structure of the header prediction circuit 100γ in this embodiment. The blocks forming the header prediction circuit 100γ are the same as those in the second embodiment, but are different in that the reception data count 167 is input from the reception header transfer control circuit 170γ to the header comparator 120.

FIG. 25 is a diagram showing a method of comparing the predicted header and the received header by the header comparator 120 in this embodiment. When registering the prediction header, the microprocessor 10 also registers the prediction header length in addition to the prediction header.

The header comparator 120 is configured to simultaneously compare the data obtained by masking the contents of the reception header register 150 with the mask register 140 and the prediction header, and compare the prediction header length with the reception data count 167. There is. That is, the reception completion timing of the predicted header is extracted by comparing the predicted header length with the received data count.

FIG. 26 is a flow chart showing the operation of the header prediction circuit 100γ in this embodiment. FIG. 26
The flow until the reception of the frame is started (steps 220, 221, 227, 228, 320)
Is the same as in the second embodiment.

When the frame reception is started, the reception header transfer control circuit 170γ takes in one word of reception data flowing through the data bus 90B, transfers it in parallel to the reception header register of each entry, and turns on the comparison request signal 166.
(350).

The header comparator 120 simultaneously compares the predicted header and the received header and the predicted header length and the received data counter (351).

The registration / retrieval control circuit 160 checks whether there is a matching entry (225), and if there is a matching entry, it notifies the microprocessor 10 (226). If there is no matching entry, steps 350, 351 and 225 are repeated until the reception of n bytes is completed or the reception of the frame is completed (352).

FIG. 27 is a block diagram showing the structure of the reception header transfer control circuit 170γ in this embodiment. The blocks constituting the reception header transfer control circuit 170γ are
Same as the second embodiment, except that the reception data counter 170-
5, the received data count 167 which is the output signal of No. 5 is input to the header comparator 120, and the signals input to the set terminal S and the reset terminal R of the comparison request signal generation circuit 170-2 are reversed. However, it differs from the second embodiment.

FIG. 28 is a flow chart showing the operation of the reception header transfer control circuit 170γ in this embodiment. 28, a flowchart of the second embodiment (see FIG.
The part different from 1) is the comparison request signal generation circuit 170-2.
When the frame reception starts, the comparison request signal 166 is turned on (step 360), and when the data acquisition is stopped, the comparison request signal 166 is turned off (361,
362) point. That is, in the second embodiment, the comparison request signal 166 is turned on when the n-byte data is received, but in the present embodiment, the comparison request signal 166 is turned on from the time when the one-word received data is fetched. I am trying to do it.

FIG. 29 is a time chart showing the operation of the header prediction circuit 100γ in this embodiment. FIG. 29
As shown in, when the predicted header length is m bytes,
When reception of m bytes is completed, a match signal 163 with the predicted header is output, and the microprocessor 10 is notified.

When the data being received is fetched in real time and compared with the predicted header, the data part being received coincidentally with the predicted header, and the data part may be erroneously interpreted as the reception completion of the protocol header. Although conceivable, the present embodiment is configured so that erroneous header analysis does not occur by comparing the predicted header length with the received data taunt at the time of comparison.

According to the present embodiment, even in a protocol in which the header length is variable, the header predicting circuit 100γ can accurately extract the timing at which the predicted header has been received, and the protocol header is temporarily stored in the buffer memory. There is an effect that analysis can be performed in real time without storing.

[0089]

As is apparent from the above description, according to the present invention, the next reception is performed based on the header of the frame previously transmitted by the local station or the header of the frame previously received by the local station. By predicting the header of a deaf frame and comparing the received header with a plurality of predicted headers at once when the frame is received, the header analysis processing of the received frame can be speeded up. By simultaneously comparing a plurality of prediction headers and reception headers by hardware, the protocol header analysis processing can be speeded up regardless of the number of prediction headers.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a configuration of a communication control device according to the present invention.

FIG. 2 is a diagram showing a configuration of a network system to which the present invention is applied.

FIG. 3 is a block diagram showing another configuration example of the communication control device according to the present invention.

FIG. 4 is a diagram showing a protocol hierarchy.

FIG. 5 is a diagram showing a frame format exchanged between communication control devices.

FIG. 6 is a diagram showing main packet formats of layer 4, layer 3, and layer 2;

FIG. 7 is a diagram showing an outline of a communication sequence and header prediction processing in the OSI protocol (layer 4).

FIG. 8 is a block diagram showing the configuration of a header prediction circuit.

FIG. 9 is a block diagram showing the configuration of a registration / search control circuit.

FIG. 10 is a flowchart showing an example of the operation of the communication control device.

FIG. 11 is a diagram showing the configuration of a reception processing definition table.

FIG. 12 is a flowchart showing the detailed operation of the header prediction circuit.

FIG. 13 is a time chart showing the operation of the communication control device during frame reception.

FIG. 14 is a block diagram showing another configuration of the header prediction circuit.

FIG. 15 is a first half of a flowchart showing another embodiment of the operation of the communication control device.

FIG. 16 is the latter half of a flowchart showing another embodiment of the operation of the communication control device.

FIG. 17 is a diagram showing another configuration of a reception process definition table.

FIG. 18 is a diagram showing the configuration of a prediction completion frame registration table.

FIG. 19 is a flowchart showing another embodiment of the operation of the header prediction circuit.

FIG. 20 is a block diagram showing the configuration of a reception header transfer control circuit.

FIG. 21 is a flowchart showing the operation of the reception header transfer control circuit.

FIG. 22 is a time chart showing the operation of the header prediction circuit.

FIG. 23 is a time chart showing another embodiment of the operation of the communication control device.

FIG. 24 is a block diagram showing another configuration example of the header prediction circuit.

FIG. 25 is a block diagram for explaining a header comparison method.

FIG. 26 is a flowchart showing another embodiment of the operation of the header prediction circuit.

FIG. 27 is a block diagram showing another embodiment of the configuration of the reception header transfer control circuit.

FIG. 28 is a flowchart showing another embodiment of the operation of the reception header transfer control circuit.

FIG. 29 is a time chart showing another embodiment of the operation of the header prediction circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Computer 2 ... Communication control device 3 ... Network 10 ... Microprocessor 40 ... Buffer memory 50 ... DMAC 60 ... LAN controller 61 ... Frame receiving signal 100 ... Header prediction circuit 110 ... Prediction header register 120 ... Comparator 130 ... Mask circuit 140 ... Mask register 150 ... Reception header register 160 ... Registration / search control circuit 170 ... Reception header transfer control circuit 180 ... Reception data length counter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04L 12/40

Claims (8)

[Claims] 1. A computer interface circuit, a microprocessor for executing communication control processing, a buffer memory for temporarily storing transmission / reception data, and data transfer control between a main memory and a buffer memory in the computer. In a communication control device having a DMA controller for performing the above and a LAN controller for controlling the connection with the network, the communication controller is created based on the header of the frame previously transmitted by the local station or the header of the frame previously received by the local station. Means for holding multiple headers (predicted headers) of the frame expected to be received, means for capturing the received data received from the network in real time, multiple comparison means for simultaneously comparing the predicted header and the received data, When the data and the prediction header match, the matching signal and the prediction header are paired. A communication control device comprising means for outputting a corresponding identifier. 2. A computer interface circuit, a microprocessor for executing communication control processing, a buffer memory for temporarily storing transmission / reception data, and a data transfer control between a main memory and a buffer memory in the computer. In a communication control device having a DMA controller for performing the above and a LAN controller for controlling the connection with the network, the communication controller is created based on the header of the frame previously transmitted by the local station or the header of the frame previously received by the local station. To hold multiple headers (predicted headers) of the frame that are expected to be received, to receive the received data from the network in real time, to compare the predicted header and received data at the same time, When headers match, match signal and prediction header The method for receiving data is characterized in that it has a step of outputting an identifier corresponding to. 3. Communication characterized by having a comparing means for comparing the predicted header and received data, and analyzing the header while receiving the protocol header without temporarily storing the protocol header in a receiving buffer. Control device. 4. The analysis of the protocol header is started before the reception of the frame is completed by the comparison means for comparing the predicted header with the received data.
The communication control device according to. 5. The communication control device according to claim 4, wherein the comparison means for comparing the predicted header with the received data analyzes the received protocol header without intervention of software. 6. A computer for communication protocol processing corresponding to the identifier and received data in response to a match signal output from a comparing means for comparing the predicted header and the received header and an identifier corresponding to the predicted header. The communication control device according to claim 4, wherein transfer to the communication device is started. 7. An interface circuit with a computer, a microprocessor for executing communication control processing, a buffer memory for temporarily storing transmission / reception data, and data transfer control between a main memory and a buffer memory in the computer. In a communication control device having a DMA controller for performing the above and a LAN controller for controlling the connection with the network, the communication controller is created based on the header of the frame previously transmitted by the local station or the header of the frame previously received by the local station. Means for holding a plurality of headers (predicted headers) of frames expected to be received and mask data indicating an area not to be compared, means for fetching received data received from the network in real time, and the received header for the mask Means for masking with data, data output from the masking means, and A communication control device comprising a plurality of comparing means for comparing the measurement header. 8. A computer interface circuit, a microprocessor for executing communication control processing, a buffer memory for temporarily storing transmission / reception data, and data transfer control between a main memory and a buffer memory in the computer. In a communication control device having a DMA controller for performing the above and a LAN controller for controlling the connection with the network, the communication controller is created based on the header of the frame previously transmitted by the local station or the header of the frame previously received by the local station. Header of frame expected to be received by (predicted header)
A means for holding a predicted header length and mask data indicating an area not to be compared, a means for fetching received data received from a network in real time, a means for masking the received header with the mask data, A communication control device comprising: means for comparing the data output from the mask means with a prediction header; and means for comparing the prediction header length with the received data length.