JP2848370B2 - Communication line monitoring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a B-ISDN
(Broadband aspects of Integrated Services Digital
The present invention relates to a communication line monitoring device that connects to a high-speed communication line such as a network) and continuously records the contents of online monitoring.
The present invention relates to a communication line monitoring apparatus capable of performing a recording operation and a reference operation using DMA transfer for each protocol unit of an upper layer of a TM (Asynchronous Transfer Mode).

[0002]

2. Description of the Related Art In diagnosis and analysis of a protocol of an ATM line on a public network, on-line recording in units of cells passing through the ATM line is performed in units of an ATM adaptation layer (AAL layer) which is a higher layer, that is, in units of cells. Protocol data unit (PDU)
Online recording by unit may be performed. The protocol architecture used for this ATM line is a hierarchical protocol, in which the physical layer and A
It is classified into a TM layer, an AAL layer, and an upper layer. Generally, from a cell acquired from a circuit under test, A
Assemble AL layer frame format (PDU),
The reproduction operation is performed by the PDU frame assembly circuit. This assembly circuit is generally realized by a commercially available communication LSI or the like.

[0003] The PDU assembly of the AAL layer is performed using a primary buffer memory which is a work memory provided around the PDU frame assembly circuit. During online recording, a plurality of PDUs are stored on the primary buffer memory. PDUs
It is possible to assemble the frames simultaneously. Also,
The primary buffer memory stores the next new PDU as described above.
Since it is necessary to minimize the loss of recording of PDU frames to be used for frame assembly, the PDU frame assembling circuit is a recording area as early as possible in the order of completion of each PDU frame assembled on the primary buffer memory. It is necessary to transfer the data to the secondary buffer memory and record it.

For this reason, the AAL PDU assembled in the primary buffer memory by the PDU frame assembling circuit.
The frames need to be sequentially transferred to the secondary buffer memory each time one PDU frame is completed. As described above, the communication line monitoring device converts the data obtained from the measured line into
The operation of continuously recording on a storage medium such as a memory while monitoring is called online monitor recording. During the online monitor recording, the request for recording the PDU frame in the secondary buffer memory at the transfer destination after the assembly of the PDU frame is completed,
Since the frame write request is randomly generated depending on the state of the monitor line, the secondary buffer memory at the recording transfer destination is usually used exclusively for writing.

[0005]

By the way, since the contents of the real-time PDU frame information during the execution of online monitor recording can be known only after the received cell is assembled, the contents of the PDU frame information can be obtained after the assembly. PDU frames are the only source. This PDU frame exists only in the primary buffer memory used for assembling or the secondary buffer memory that is the transfer destination.

Therefore, if an operation such as analysis or display is performed in real time using the assembled PDU frame in parallel with the online recording of the PDU frame, the primary buffer memory or the secondary buffer memory is read in between the online recording. PDU from the next buffer memory by some means
The frame needs to be read.

In this case, the PDU to the secondary buffer memory
Since the time allocation for the frame transfer is relatively reduced, there is a problem that the recording efficiency is significantly reduced and the danger of missing the recording of the PDU frame is increased. Further, when writing and reading for data acquisition are used in the same memory resource by DMA transfer recording in a time-separated manner, there is a problem that an algorithm and a control circuit for contention control become complicated. .

The present invention has been made in view of the above circumstances, and a PDU frame that can be used for purposes other than online recording in parallel with the PDU frame recording operation without significantly lowering the transfer efficiency of online recording. An object of the present invention is to provide a communication line monitoring device that can be acquired during online monitor recording.

[0009]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a communication system using a protocol architecture having at least a physical layer and at least one upper layer located above the physical layer. An extraction unit for extracting a cell of the physical layer from the communication line, and adapting the cell extracted by the extraction unit to the data format of the at least one upper layer. Assembly means for assembling the assembled unit, first storage means for recording the unit assembled by the assembly means, and second storage means for recording the unit assembled by the assembly means. I do. Further, the present invention is characterized in that a storage device for temporarily storing the units assembled by the assembling means and for temporarily storing the units being assembled is provided. Further, the present invention is characterized by comprising a transfer means for transferring the assembled unit stored in the storage device to the first storage means and the second storage means. Also, the present invention provides a first control unit for controlling whether or not the transfer unit transfers the unit to the first storage unit and whether or not to transfer the unit to the second storage unit. It is characterized by having. Also,
The present invention is characterized by comprising second control means for controlling the second storage means and reading out the unit. Further, the present invention includes a conflict avoiding means for temporarily interrupting the reading of the unit by the second control means when the unit is transferred from the storage device to the second storage means. Features. Further, the present invention is characterized in that the first control means temporarily suspends the operation of the transfer means when the assembling means stores the assembled unit in the storage device.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a communication line monitoring device according to an embodiment of the present invention. In FIG. 1, a cell extraction circuit 10 is used to extract a cell and a clock from a line to be monitored. The cell extraction circuit 10 is connected to a PDU frame assembling circuit 12 via a cell data bus 10a, and extracts the extracted cells from a PDU. Output to the frame assembly circuit 12. This cell extraction circuit 10
Is a commercially available IC (Integrated Cir
cuit). Each time the cell extracting circuit 10 receives one cell, it outputs data constituting the cell to the PDU frame assembling circuit 12 via the cell data bus 10a. The cell has a data length of 53 bytes and is roughly composed of 5 bytes of header information and 48 bytes of payload information. The header information includes information such as a pointer and HEC (Header Error Control) information, and the payload information includes pure data.

The PDU frame assembling circuit 12 determines the contents of the header information of each received cell sent from the cell data bus 10a, and uses the upper layer protocol A
TM adaptation layer (AAL) protocol
It has a function to assemble it into a data unit (PDU) format. In the present embodiment, the PDU frame assembly circuit 12 is realized by a commercially available communication LSI. The PDU frame assembling circuit 12 is connected to a primary buffer memory 14, a selector 28, which will be described later, via a payload data bus 12a, a primary buffer write address signal line 12b, a primary buffer access signal line 12c, and a transfer request signal line 12d.
It is connected to the DMA transfer control circuit 20 and the first CPU 24, respectively.

The primary buffer memory 14 is a working memory of the PDU frame assembling circuit 12. During the online monitor recording, the PDU frame assembling circuit 12 communicates with the primary buffer memory 14 and the payload information via the payload data bus 12a. The PDU frame is assembled by performing the exchange. During online monitor recording, the primary buffer memory 14 usually stores the PD being assembled.
One or a plurality of U frame data are stored simultaneously.

The primary buffer memory 14 is connected to a secondary buffer memory 16 and a tertiary buffer memory 18 via a transfer data bus 14a, and serves as a data transfer source of the secondary buffer memory 16 and the tertiary buffer memory 18. Function. Data transfer to the secondary buffer memory 16 and the tertiary buffer memory 18 is performed at the same timing. The secondary buffer memory 16 is an online recording memory for recording data of a PDU frame, and is set to write only during online recording. Also, the tertiary buffer memory 18 is
Similarly to the above, it is a memory for recording PDU frame data, but recording and reading are performed even during online recording.

The DMA transfer control circuit 20 transfers the data of the PDU frame from the primary buffer memory 14 to the secondary buffer memory 16 as the first transfer destination and to the tertiary buffer memory 18 as the second transfer destination. Performs DMA transfer control. That is, the DMA transfer control circuit 20 accesses the primary buffer memory 14 as the transfer source via the transfer destination address bus 20a and the selector 28, and obtains a transfer source address bus signal for reading data to be transferred. Further, the secondary buffer memory 16 and the tertiary buffer memory 1, which are the first or second destination, are transferred via the destination address bus 20b, the destination address bus 20c, and the selector 30.
8 is accessed, and a transfer destination address bus signal for writing transfer data is output to each. Also,
It is connected to a selector 30 and an arbiter device 22 described later via a tertiary buffer access signal line 20d, and is connected to a first CPU 24 via a transfer end interrupt signal line 20e.

The arbiter device 22 has a read request signal line 22
a, a second CPU to be described later via the weight signal line 22b.
26, and is output via the tertiary buffer access signal line 20d and indicates that the tertiary buffer memory 18 is being accessed.
P by DMA transfer from 4 to tertiary buffer memory 18
This prevents contention between the writing of DU data and the reading of PDU data from the tertiary buffer memory 18 by the second CPU 26.

The second CPU 26 is connected to the second CPU data bus 2
This device is connected to the tertiary buffer memory 18 and the selector 30 via the 6a and the second CPU address bus 26b, respectively, and controls reading of PDU frame data transferred to the tertiary buffer memory 18 during online recording. The PDU frame data read from the tertiary buffer memory 18 by the second CPU 26 is used for analyzing and displaying the line status.

The first CPU 24 is connected to the first CPU data bus 2
4a and the PDU via the first CPU address bus 24b.
It is connected to the frame circuit 12 and the DMA transfer control circuit 20, and controls the PDU frame assembly circuit 12 and the DMA transfer control circuit 20 to perform data transfer control. This first C
The PU 24 has a register for storing a data write position (hereinafter, referred to as a pointer) in the secondary buffer memory 16 and the tertiary buffer memory 18 to which the PDU frame data is transferred. Has a function of updating this pointer.

Although not shown, a selection for selecting whether to transfer PDU frame data from the primary buffer memory 14 to one or both of the secondary buffer memory 16 and the tertiary buffer memory 18 is made. A switch is provided, and information according to the operation content of the operator is stored in the first CPU.
24 and the second CPU 26.

The selector 28 is connected to the PDU frame assembly circuit 12 and the DMA transfer control circuit 20 via the primary buffer write address signal line 12a and the transfer destination address bus 20a, respectively. This selector 28
In response to the primary buffer accessing signal transmitted from the DU frame assembling circuit 12 via the primary buffer access signal line 12c, the primary buffer memory 14 receives the primary buffer write address signal line 12b and the transfer source address bus 20a. Connect either one. That is, when the primary buffer access signal is being output from the PDU frame assembly circuit 12, the primary buffer write address signal line 12b is connected to the primary buffer memory 14, and the primary buffer access signal is being output. If not, the transfer source address bus 20a is connected to the primary buffer memory 14.

The selector 30 has a transfer destination address bus 20c.
And D via the second CPU address bus 26b.
The MA transfer control circuit 20 and the second CPU 26 are connected. The selector 30 stores the transfer destination address bus 20c and the second CPU address bus 26b in the tertiary buffer memory 18 according to the tertiary buffer access signal transmitted from the DMA transfer control circuit 20 via the tertiary buffer access signal line 20d. Is connected. That is, DMA
When the tertiary buffer access signal is output from the transfer control circuit 20, the transfer destination address bus 20c is connected to the tertiary buffer memory 18, and when the tertiary buffer access signal is not output, the second The CPU address bus 26b is connected to the tertiary buffer memory 18.

The configuration of the communication line monitoring apparatus according to one embodiment of the present invention has been described above. Next, referring to FIG.
One configuration example of the A control circuit will be described. FIG. 2 is a block diagram showing an example of the configuration of the DMA transfer control circuit 20 shown in FIG. 1, and the same components as those shown in FIG. 1 are denoted by the same reference numerals. The DMA transfer control circuit 20 shown in FIG. 2 performs a transfer operation with a single system clock input from a terminal SC in the figure.

In FIG. 2, reference numeral 50 denotes an address decoder connected to the first CPU address bus 24b, which is used to select address data transmitted from the first CPU 24 (for selecting an input port of the DMA transfer control circuit 20 and for controlling DMA transfer). Circuit 20) is decoded and output to output lines 50a to 50f. A system clock is input to a clock terminal of the address decoder 50, and the address decoder 50 operates in synchronization with the system clock.

Reference numerals 50a to 50e denote registers, each having a clock terminal and a data input terminal. Register 52a
Output lines 50a to 50e of the address decoder 50 are connected to clock terminals of .about.52e, respectively, and a first CPU data bus 24a is connected to each data input terminal. The register 52e has a reset input terminal, and is connected to an output line 50f of the address decoder 50.

The register 50a is a register in which a read start address of the primary buffer memory 14 (see FIG. 1) as a transfer source is written, and the register 50b is a secondary buffer memory 16 (see FIG. 1) as a first transfer destination. ) Is a register in which the start address is written.
c is a tertiary buffer memory 18 (FIG. 1
Is the register where the start address of the
The register 50d is a register in which a transfer word count is written, and the register 50e is a transfer control register in which a DMA transfer instruction code indicating whether or not to transfer data is written.

The two output terminals Q1 and Q2 of the register 52e
Are connected to the D input terminals of D flip-flops 66 and 68, respectively. D flip-flop 66,
A system clock is input to a clock input terminal 68, and each D flip-flop operates in synchronization with the system clock. The reset input terminals of the D flip-flops 66 and 68 are connected to the output line 50 of the address decoder 50.
f is connected.

Numerals 54a to 54d denote counters, each having a data input terminal, a clock terminal, an enable terminal EN, and a load signal input terminal LD (the load signal input terminal LD is an inverting input terminal). An output line 50e of the address decoder 50 is connected to a load signal input terminal LD of each of the registers 54a to 54d, and a system clock is input to a clock terminal. The data input terminals of the counters 54a to 54d are connected to the data output terminals of the registers 52a to 52d, respectively.
Read from d.

The counters 54a to 54c are registers 52a
To 52c, and read the initial values from the counter 54.
a generates an address for accessing the primary buffer memory 14, the counter 54b generates an address for accessing the secondary buffer memory 16, and the counter 54c generates an address for accessing the tertiary buffer memory 18.
The counter 54d reads the total number of words of data to be transferred at one time from the register 52d, and decrements each time one word is transferred.

The output end of the counter 54a is connected to the transfer source address bus 20a, and the counters 54b and 54c are connected to the transfer destination address bus 20b and the transfer destination address bus 20c via D flip-flop groups 75 and 76, which will be described later. ing. The output terminal of the counter 54d is connected to the comparator 56. The comparator 56 monitors the count value of the counter 54d, determines whether or not all output bits of the counter 54d are "0", and outputs from the output terminal A or the output terminal B. When all the output bits of the counter 54d are "0", the output value to the output terminal A is "1" and the output value to the output terminal B is "0". The output value is “0” and the output value to the output terminal B is “1”.

The interrupt generating circuit 58 is connected to the output terminal A of the comparator 56. This interrupt generation circuit is realized by a D flip-flop. That is, the level of the D input terminal of the interrupt generation circuit 58 is always set to “1”, and the output terminal A of the comparator 56 is connected to the clock terminal of the interrupt generation circuit 58. When the level rises, an interrupt signal is output from the output terminal Q of the interrupt generation circuit 58. This output terminal Q is NO
It is connected to the transfer end interrupt signal line 20e via the T circuit 60. The output terminal 50f of the address decoder 50 is connected to the reset input terminal of the interrupt generation circuit 58.

Also, AND circuits 62a to 62d (these AND circuits) are connected to enable terminals EN of the registers 54a to 54d.
One input terminals of the circuits 62a to 62d are connected to output terminals of NOT input terminals. These AND circuits 62a to 62a
A primary buffer access signal line 12c is connected to one input terminal (NOT input terminal) of 2d. AND circuit 6
The output terminal B of the comparator 56 is connected to the other input terminal of 2a. AND circuits 64a and 64b and an OR circuit 65 are connected to the other input terminals of the AND circuits 62b to 62d, respectively.
Output terminals are connected.

A signal output from the output terminal B of the comparator 56 and a register 52 are connected to two input terminals of the AND circuit 64a.
e and the signal output from the D flip-flop 66 connected to the output terminal Q1 of the e. A signal output from the output terminal B of the comparator 56 and a signal output from the D flip-flop 68 connected to the output terminal Q2 of the register 52e are input to two input terminals of the AND circuit 64b. The two input terminals of the OR circuit 65
The signal output from the D flip-flop 66 and the signal output from the D flip-flop 68 are respectively input. The D flip-flop 68
Is connected to a tertiary buffer access signal line 20d.

In the figure, reference numerals 70, 72, and 74 denote timing generation circuits, and a system clock S input to a clock terminal.
A timing signal is generated based on C. Outputs of the timing generation circuits 70, 72, and 74 are connected to the primary buffer memory 14, the secondary buffer memory 16, and the tertiary buffer memory 18, respectively. It is used to determine the timing at the time of write access to the secondary buffer memory 16 and the timing at the time of write access to the tertiary buffer memory 18, respectively. Further, the timing generation circuits 70, 72, 74 are provided with an enable terminal EN. Enable end E of timing generation circuit 70
The output of the AND circuit 62a is input to N, and the AND terminal 62b is connected to the enable terminal EN of the timing generation circuit 72.
And the output of the AND circuit 62c is input to the enable terminal EN of the timing generation circuit 74.

Reference numerals 70 and 72 denote D flip-flop groups, which operate in synchronization with the system clock SC and delay the transfer destination addresses output from the counters 54b and 54c by one clock of the system clock SC. The signals are output to the bus 20b and the transfer destination address bus 20c, respectively.

In the above configuration, the operation of the communication line monitoring apparatus according to one embodiment of the present invention will be described with reference to the drawings. The communication line monitoring device according to an embodiment of the present invention has a D
Whether to perform MA transfer, whether to perform online recording,
And whether or not to perform online reference can be selected. This selection is made by writing D into the register 52e shown in FIG.
It can be selected according to the contents of the MA transfer instruction code.

FIG. 3 is a diagram showing the contents of the register 52e. Although the register 52e can be designed from several bits to tens of bits, the bits related to the DMA transfer instruction code are only the least significant two bits, that is, bit 0 and bit 1, as shown. Bit 0 is a signal from the primary buffer memory 14 to the secondary buffer memory 16 in FIG.
This bit sets whether or not to perform a DMA transfer. When bit 0 is “1”, a DMA transfer to the secondary buffer memory 16 is performed. When bit 0 is “0”, a secondary buffer is set. No DMA transfer to the memory 16 is performed. Bit 1
1 is a bit for setting whether or not to perform a DMA transfer from the primary buffer memory 14 to the tertiary buffer memory 18 in FIG. 1. When bit 0 is “1”, the DMA is transferred to the tertiary buffer memory 18. Transfer is performed, and if it is “0”, DMA transfer to the tertiary buffer memory 18 is not performed.

FIG. 4 is a table showing a DMA transfer instruction code and execution contents in a table format. As shown, D
The following four execution contents are selected by the MA transfer instruction code. (1) When both the contents of bit 0 and bit 1 in FIG. 3 are “0”, that is, when the DMA transfer instruction code is “0”
000H ", the DMA transfer from the primary buffer memory 14 to the secondary buffer memory 16 or the tertiary buffer memory 18 is not performed. (2) When only bit 0 in FIG. 3 is “1”, that is, when the DMA transfer instruction code is “0001H”, the primary buffer memory 14 to the secondary buffer memory 16
DMA transfer is performed to perform online recording.
The online recording is to record the contents of the online monitoring. (3) When only bit 1 in FIG. 3 is “1”, that is, when the DMA transfer instruction code is “0002H”, the primary buffer memory 14 to the tertiary buffer memory 18
DMA transfer is performed to make online reference.
The online reference is to perform analysis and display of the line status in real time. (4) When both the contents of bit 0 and bit 1 in FIG. 3 are “1”, that is, when the DMA transfer instruction code is “0”
In the case of "003H", the DMA transfer from the primary buffer memory 14 to the tertiary buffer memory 18 is performed to perform online recording and to perform online reference.

Hereinafter, each operation described above will be described with reference to FIGS.
It will be described in detail with reference to FIG. (1) When the DMA transfer instruction code is "0000H" In this case, the PDU frame data assembled in the primary buffer memory 14 is not transferred to either the secondary buffer memory 16 or the secondary buffer memory 18. The first CPU 24 in FIG. 1 sends out data for selecting an input port of the register 52e in FIG. 2 via the first CPU address bus 24b, and transmits a DMA transfer instruction code “ 0000
H ". When these are input to the DMA transfer control circuit 20, the DMA transfer instruction code "0" is stored in the register 52e.
000H ”is written. This DM is stored in the register 52e.
When the A transfer instruction code is written, both the outputs Q1 and Q2 of the register 52e become "0".
b, 54c and 54d are all disabled,
Therefore, the DMA transfer from the primary buffer memory 14 to the secondary buffer memory 16 and the tertiary buffer memory 18 is not performed.

(2) When the DMA transfer instruction code is "0001
H "In this case, the PDU frame data assembled in the primary buffer memory 14 is transferred to only the secondary buffer memory 16. That is, online recording is performed.

First, the cell extraction circuit 10 extracts a clock and data from a signal on the monitor line, and extracts a cell having a data format of the ATM layer. The cells are input to the PDU frame extraction circuit 2 via the cell data bus 10a. The PDU frame assembling circuit 12 uses the primary buffer memory 14 as an assembling work area, reads the header information of the received cell, and reads the ATM upper layer AAL.
An operation for assembling PDU frame data is performed according to the layer format. Specifically, this assembly work
Each time a valid cell is received, the PDU frame assembling circuit 12 reads the information of the header information included in the cell, and classifies the payload information of the cell excluding the header information for each of the determined PDU frames, and stores it in the primary buffer memory. 1
No. 4 refers to an operation of sequentially storing the data in the middle of assembly. Writing to the primary buffer memory 14 for the assembling operation is performed through the payload data bus.

The PDU frame assembly circuit 12
During a period in which the DU frame data is written to the primary buffer memory 14, a signal indicating that the primary buffer memory is being accessed is output to the DMA transfer control circuit 20 via the primary buffer access signal line 12c. This is to prohibit reading from the primary buffer memory 14 for DMA transfer. The PDU frame assembly circuit 12
Outputs a transfer request signal to the first CPU 24 via the transfer request signal line 12d every time one PDU frame assembly is completed. This transfer request signal is issued once for one PDU frame data transfer.

The first CPU 24 receiving the transfer request signal
Knows that the assembling of one PDU frame data has been completed on the primary buffer memory 14, and from the PDU frame assembling circuit 12, the start address at which the PDU frame data is stored in the primary buffer memory 14 and the PDU frame data , That is, the number of words required for transfer.

As described above, the first CPU 24 has registers for storing the pointers of the secondary buffer memory 16 and the tertiary buffer memory 18 to which the PDU frame data is transferred, and transfers the values. Update by the number of words. Therefore, the first CPU 24
Every time a transfer request interrupt is received from the U frame assembling circuit 12, all the information necessary for DMA transfer is prepared by simply obtaining from the PDU frame assembling circuit 12 only the transfer source pointer position and the number of words to be transferred. It will be.

Next, the first CPU 24 transfers a read pointer of the primary buffer memory 14, a write pointer of the secondary buffer memory 16, and a write pointer of the tertiary buffer memory 18 via the first CPU address bus 24a. Number of words of PDU frame data, and DMA
The transfer instruction codes are sequentially sent to the DMA transfer control circuit 20. At the time of this transfer, the first CPU address bus 24
A signal for selecting the input port of the DMA control circuit 20 is also transmitted via b. PDU frame assembly circuit 1 described above
When the transmission of the pointer and the like from the first CPU 24 which has received the transfer request from the second CPU 2 is completed, processing for masking the next transfer request interrupt is internally performed. This mask is not released until the DMA transfer for the currently accepted transfer request is completed.

The above pointers are used by the DMA transfer control circuit 20.
, The data is written into the registers 52a to 52c, the number of words to be transferred is written into the register 52d, and the
The A transfer instruction code is written into the register 52e. Since the DMA transfer instruction code is “0001H”,
"1" is output from the output terminal Q1 of the register 52e, and "0" is output from the output terminal Q2. Therefore, “1” is output from the D flip-flop 66, and “0” is output from the D flip-flop 68. D flip-flop 6
6 and 68 are output from an AND circuit 64a and an OR circuit 65a.
To the AND circuit 64b and the OR circuit 65, respectively, and the counters 54b and 54d, the timing generation circuit 7
0 and the comparator 56 are enabled and the counter 54c
And the timing generation circuit 74 is disabled.
Next, the counters 54a, 54b, 54d
The data written to a, 52b, and 52d are read, respectively.

When the above processing is completed, the DMA transfer control circuit 20 starts DMA transfer of PDU frame data from the primary buffer memory 14 to the secondary buffer memory 16. The PDU frame data is read from the read pointer position of the primary buffer memory 14 held by the counter 54a, and the PDU frame data is transferred to the write pointer position of the secondary buffer memory 16 held by the counter 54c via the transfer data bus 14c. Data is transferred word by word.

During transfer, the counters 54a and 54b
Increments the current value each time one word is transferred, and decrements the counter 54d each time one word is transferred. The DMA transfer control circuit 20 receiving the DMA transfer instruction code continues the DMA transfer until the value of the counter 54d becomes 0.

When the PDU frame assembling circuit 12 needs to access the primary buffer memory 14 while the DMA transfer is being performed, the PDU frame assembling circuit 12 sends the data through the primary buffer access signal line 12c. 1
A next buffer access signal is sent to the DMA transfer control circuit 20. When the primary buffer access in-progress signal is transmitted, even if the DMA transfer
Even during the transfer of the frame data, the reading of the PDU frame data from the primary buffer memory 14 is interrupted, and the work of the PDU frame assembling circuit 12 assembling other PDU frame data is given priority. That is, the PDU frame assembly circuit 12 has a higher priority than the DMA transfer control circuit 20 for accessing the primary buffer memory 14.

The counters 54a to 54d in the DMA transfer control circuit 20 are disabled immediately when the primary buffer access signal is received via the primary buffer access signal line 12c during the DMA transfer, and the value held therein is maintained. Updates are frozen. That is, the increment and decrement of the count value are temporarily stopped. When the reception of the primary buffer accessing signal ends, the counter 5
4a to 54d are enabled, and the DMA transfer is restarted.

The DMA transfer operation is continued as long as the value held in the counter 54d is 1 or more. When the transfer is continued and the value held in the counter 54d becomes 0, DMA transfer, that is, online recording from the primary buffer memory 14 to the secondary buffer memory 16 is completed.
Completion of this online recording is indicated by the comparator 56
This is performed by determining whether the output value of 4d is 0 or not.

The comparator 56 sets the output value of the counter 54d to 0.
If it is determined that the output signal is “1”, an output signal “1” is output from the output terminal A. This output signal is transferred to the transfer end interrupt signal line 2 via the D flip-flop 58 and the NOT circuit 60.
0e, and received by the first CPU 24. Upon receiving this signal, the first CPU 24 determines that the transfer of the PDU frame data has been completed, accesses the input port of the DMA transfer control circuit 20, and clears the DMA transfer instruction code. Next, the first CPU 24 releases the mask of the transfer request interrupt from the PDU frame assembly circuit 12. Thus, a new PD from the PDU frame assembly circuit 12 is output.
U frame data transfer requests can be accepted.

As described above, the first CPU 24 temporarily stores the PD
When one PDU frame transfer request is received from the U frame assembling circuit 12, the D
Until the MA transfer end interrupt is received, a new transfer request from the PDU frame assembly circuit 12 is not accepted. Further, the first CPU 24 executes the DMA
By completing the clearing of the transfer end interrupt and releasing the mask of the transfer request interrupt from the PDU frame assembly circuit 12, the reception of the next transfer request is started.

The PDU frame data on the secondary buffer memory 16 on which the online recording has been performed is
It is read out after online recording is stopped, and is used as a data file for offline analysis processing such as display and analysis by the system software of the protocol analyzer, and translation by the upper layer protocol.

(3) The DMA transfer instruction code is "0002"
In this case, the PDU frame data assembled in the primary buffer memory 14 is transferred to only the tertiary buffer memory 18. That is, online reference is made. D from the first CPU 24 to the DMA transfer control circuit 20
When the MA transfer instruction code “0002H” is transmitted, D
The data is written to the register 52e of the MA transfer control circuit 20. Since this DMA transfer instruction code is "0002H", "0" is output from the output terminal Q1 of the register 52e, and "1" is output from the output terminal Q2. Therefore, "0" is output from the D flip-flop 66, and "1" is output from the D flip-flop 68. Since the outputs of the D flip-flops 66 and 68 are input to the AND circuit 64a and the OR circuit 65 and the AND circuit 64b and the OR circuit 65, the counters 54c and 54d, the timing generation circuit 74, and the comparator 56 are enabled. ,
The counter 54b and the timing generation circuit 72 are disabled.

Next, the counters 54a, 54c and 54d read the data written in the registers 52a, 52c and 52d. The output terminal Q of the D flip-flop 68 is connected to the tertiary buffer access signal line 20d.
When the DMA transfer to the tertiary buffer memory 18 is performed, a tertiary buffer accessing signal is input to the arbiter device 22.

The operation of DMA transfer of PDU frame data from the primary buffer memory 14 to the tertiary buffer memory 18 is performed in the secondary buffer memory 16 described in (2).
Is similar to the DMA transfer to the third buffer memory 18 except that the contention problem is avoided when the second CPU 26 reads the tertiary buffer memory 18 during the DMA transfer.

That is, the DMA is transferred to the tertiary buffer memory 18.
When the transfer is being performed, a tertiary buffer access in-progress signal is input to the arbiter device 22. In the arbiter device 22, the DMA transfer control circuit 20 controls the tertiary buffer memory 1
8 during the DMA transfer to the second CPU 26
From the second CPU 2 via the wait signal line 22b immediately when reading from the
6, a wait is issued, and the reading is forcibly extended.

When the second CPU 26 is reading PDU frame data from the tertiary buffer memory 18 and receives a tertiary buffer access signal to the arbiter device 22, the arbiter device 22 outputs CPU
26, the reading of the PDU frame data is forcibly extended, and the DMA transfer from the primary buffer memory 14 to the tertiary buffer memory 18 is preferentially performed.

That is, rather than reading the PDU frame data from the tertiary buffer memory 18 by the second CPU 26, the tertiary buffer memory 1
8 is given higher priority.
This is because the DMA transfer to the tertiary buffer memory 18 is performed at the same timing as the DMA transfer to the secondary buffer memory 16, so that contention control is simplified and online recording and online reference described later are simultaneously performed. In this case, it is to prevent the efficiency of online recording in the secondary buffer memory 16 from decreasing.

The second CPU 26 controls the tertiary buffer memory 18
The PDU frame data read out from is used in real time as a data file for off-line analysis processing such as display and analysis by system software of a protocol analyzer, and translation by an upper layer protocol.

(4) When the DMA transfer instruction code is “0003”
H "In this case, the PDU frame data assembled in the primary buffer memory 14 is transferred to both the secondary buffer memory 16 and the tertiary buffer memory 18.
That is, online recording and online reference are performed. DM from first CPU 24 to DMA transfer control circuit 20
When the A transfer instruction code “0003H” is transmitted, the DM
The data is written to the register 52e of the A transfer control circuit 20.
Since this DMA transfer instruction code is "0003H", "1" is output from the output terminals Q1 and Q2 of the register 52e. Accordingly, "1" is output from both the D flip-flops 66 and 68. D flip-flops 66, 68
Is output to the AND circuit 64a and the OR circuit 65 and
Since the signals are input to the circuit 64b and the OR circuit 65, the counters 54b, 54c, 54d, the timing generation circuits 72, 74, and the comparator 56 are enabled.

Next, the counters 54a, 54b, 54c,
54d reads the data written in the registers 52a, 52b, 52c, 52d. As described in the above (3), the output terminal Q of the D flip-flop 68 is connected to the tertiary buffer access signal line 20d.
When the DMA transfer to the tertiary buffer memory 18 is performed, a tertiary buffer accessing signal is input to the arbiter device 22.

In this case, the above (2) and (3)
As described above, the PD from the primary buffer memory 14 to the secondary buffer memory 16 and the tertiary buffer memory 18
DMA transfer of U frame data is performed by the same operation. In addition, the contention problem when the second CPU 26 reads the tertiary buffer memory 18 during the DMA transfer is also avoided.

FIG. 5 is a timing chart showing the flow of signals and data during DMA transfer. In FIG. 5, the period denoted by reference numeral T2 is a period in which online recording and online reference are performed simultaneously, and the period denoted by reference numeral T3 is a period in which only online recording is performed.
It is assumed that time elapses from the left side to the right side in the figure.
In the figure, (a) is an operation cycle of the second CPU 26, (b) is a wait signal output from the arbiter device 22 to the second CPU 26, and (c) is a tertiary signal output from the DMA transfer control circuit 20 to the arbiter device 22. Buffer access signal,
(D) is a read / write timing for the tertiary buffer memory 18, (e) is a write timing for the secondary buffer memory 16, and (f) is a primary buffer memory 14.
(G) is a transfer interrupt control signal sent from the DMA transfer control circuit to the first CPU 24,
(H) shows the timing of signal transfer between the first CPU 24 and the DMA transfer control circuit 20. still,
Symbols “R” and “W” in the figure indicate reading and writing, respectively.

In the period indicated by T1 in the figure, the DM
No A transfer is performed, and the second CPU 26 accesses the tertiary buffer memory 18 to read PDU frame data. At the end of the period T1, the first CPU
24 to the DMA transfer control circuit 20.
When "003H" is transmitted, a tertiary buffer accessing signal is transmitted from the DMA transfer control circuit 20 to the arbiter device 22. Then, DMA transfer of the PDU frame data is performed from the primary buffer memory 14 to the secondary buffer memory 16 and the tertiary buffer memory 18.

When the arbiter device 22 receives the tertiary buffer memory accessing signal, it sends a wait signal to the second CPU 26. When this wait signal is transmitted, the operation cycle of the second CPU 26 (cycle 3 in FIG. 5) is extended. During the DMA transfer, the DMA transfer of the PDU frame data is sequentially performed from the primary buffer memory 14 to the secondary buffer memory 16 and the tertiary buffer memory 18.

From the DMA transfer control circuit 20 to the first CPU 2
4 is sent to the first CPU 24.
Accesses the input port of the DMA transfer control circuit 20,
Clear the DMA transfer instruction code. When the DMA transfer control code is cleared in the DMA transfer control circuit 20, the DMA transfer control circuit 20 stops sending the tertiary buffer access signal. When the tertiary buffer access signal is no longer input, the arbiter device 22 outputs the second C signal.
The transmission of the wait signal to the PU 26 is stopped. When the wait signal is no longer transmitted, the second CPU 26 restarts the extended operation cycle, and again operates the tertiary buffer memory 1.
The reading of the PDU frame data from step 8 is restarted.

From the first CPU 24 to the DMA transfer control circuit 2
When the transfer instruction code “0001H” is transmitted to “0”, the wait signal is not transmitted to the second CPU 26 as illustrated. The DMA transfer is performed only from the primary buffer memory 14 to the secondary buffer memory 16. Even during the DMA transfer, the second CPU 26 can read PDU frame data from the tertiary buffer memory 18. When this DMA transfer is completed, the DMA transfer control circuit 20 sends the first CPU 24
A transfer end interrupt signal is sent to the
A input port of the A transfer control circuit 20 is accessed and DMA
The transfer instruction code is cleared.

As described above, according to the type of the transfer instruction code from the first CPU 24, the DMA transfer destination is set to the normal secondary buffer memory 16 and simultaneously performed to the tertiary buffer memory 18. Can be specified for each transfer. Further, the secondary buffer memory 16 can be used only for online recording even when online recording and online reference are performed at the same time, so that online monitoring in a high-speed line such as B-ISDN is not hindered and online reference is performed in real time. Became possible.

The present invention is not limited to the above embodiment, but can be freely modified within the scope of the present invention. For example, in the above embodiment, an example in which the physical layer, the ATM layer, the AAL layer, and the upper layer are divided into layers has been described.
ontrol Protocol / Internet Protocol) or more abstractly OSI (Open Systems Interconnection)
It can be applied to protocol architectures generally stratified by reference models.

[0070]

As described above, according to the present invention,
Since the second storage means for storing units used for online reference is provided in addition to the first storage means for performing online recording, online reference and online recording can be performed simultaneously without complicating the configuration of the apparatus. A problem that occurs when the operation is performed, for example, a problem that a part of the unit is missed can be avoided. More specifically, since online reference can be performed during online recording without disturbing the online recording operation, it is possible to simultaneously perform online recording of a high-speed line, display and analysis of the line status, translate upper layer protocol, and the like in real time. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a communication line monitoring device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a DMA transfer control circuit 20 shown in FIG.

FIG. 3 is a diagram showing the contents of a register 52e.

FIG. 4 is a table showing a DMA transfer instruction code and execution contents in a table format.

FIG. 5 is a timing chart showing the flow of signals and data during DMA transfer.

[Explanation of symbols]

 Reference Signs List 10 Cell extraction circuit (extraction means) 12 PDU frame assembling circuit (assembly means) 14 Primary buffer memory (storage device) 16 Secondary buffer memory (first storage means) 18 Tertiary buffer memory (second storage means) Reference Signs List 20 DMA transfer control circuit (transfer means) 22 Arbiter device (conflict avoidance means) 24 First CPU (first control means) 26 Second CPU (second control means)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 12/28 H04L 12/24 H04L 12/26 H04L 29/14

Claims (7)

(57) [Claims] 1. An apparatus for monitoring a communication line for performing communication using a protocol architecture having at least a physical layer and at least one upper layer located above the physical layer, wherein the communication line Extracting means for extracting the cell of the physical layer from the unit; assembling means for assembling the cell extracted by the extracting means into a unit adapted to the data format of the at least one upper layer; and unit assembled by the assembling means. First to record
And a second unit for recording the unit assembled by the assembling unit.
A communication line monitoring device comprising: 2. The communication line monitoring apparatus according to claim 1, further comprising a storage device for temporarily storing the unit assembled by said assembling means and temporarily storing the unit being assembled. . 3. The communication line according to claim 2, further comprising a transfer unit that transfers the assembled unit stored in the storage device to the first storage unit and the second storage unit. Monitoring device. 4. A first control means for controlling whether or not the transfer means transfers the unit to the first storage means and whether or not to transfer the unit to the second storage means. The communication line monitoring device according to claim 3, wherein 5. The communication line monitoring apparatus according to claim 3, further comprising second control means for controlling said second storage means and reading said unit. 6. A conflict avoiding means for temporarily interrupting reading of said unit by said second control means when said unit is transferred from said storage device to said second storage means. The communication line monitoring device according to claim 5, wherein 7. The system according to claim 4, wherein the first control means temporarily suspends the operation of the transfer means when the assembly means stores the assembled unit in the storage device. Communication line monitoring device as described in the above.