JPH056350B2 - - Google Patents
Info
- Publication number
- JPH056350B2 JPH056350B2 JP57178412A JP17841282A JPH056350B2 JP H056350 B2 JPH056350 B2 JP H056350B2 JP 57178412 A JP57178412 A JP 57178412A JP 17841282 A JP17841282 A JP 17841282A JP H056350 B2 JPH056350 B2 JP H056350B2
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- Japan
- Prior art keywords
- region
- field effect
- type
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- conductivity type
- Prior art date
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- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 10
- 239000002131 composite material Substances 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims 7
- 239000010408 film Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000013329 compounding Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置の構造に係り、特に、従来
の構造に比較して素子の駆動能力を増大させて高
速動作を行うのにより適合した半導体装置の構造
に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to the structure of a semiconductor device, and in particular to a semiconductor device that is more suitable for high-speed operation by increasing the drive capability of elements compared to conventional structures. Regarding the structure of
一般に半導体回路はより高速な性能を得るため
に、より微細化を進めることによりその目的を達
成している。併し集積度が非常に高くなると、１
つのチツプ当りに消費される電力が増大するため
に、熱的な限界が生じ、或程度以上は素子を集積
することは不可能となる。
Generally, in order to obtain higher-speed performance of semiconductor circuits, this goal is achieved by further miniaturization. However, when the degree of integration becomes very high, 1
The increased power consumed per chip creates a thermal limit, making it impossible to integrate devices beyond a certain point.
CMOS（Complementary symmetry MOS
transister）（相補型MOSトランジスタ）回路は、
過渡現象の状態の時にのみ電流が流れることか
ら、現時点では消費電力が最小の回路構成である
とされている。併し乍らCMOS回路は電流駆動
能力が小さく、負荷容量の大きな素子を駆動した
場合には、立ち上り時間が大きくなり、高速動作
を望むことは困難となる。このことは集積度の高
い回路では、素子間の配線長が長くなることに伴
う配線相互間の静電容量の増大による速度の減少
効果として、現実にあらわれてくる。その結果、
従来のCMOS回路をそのまま微細化したLSIでは
高速特性を期待することは困難であつた。 Complementary symmetry MOS (CMOS)
transister) (complementary MOS transistor) circuit is
Because current flows only during transient conditions, it is currently considered to be the circuit configuration with the lowest power consumption. However, the CMOS circuit has a small current driving capability, and when driving an element with a large load capacity, the rise time becomes long, making it difficult to expect high-speed operation. This actually appears in highly integrated circuits as a reduction in speed due to an increase in capacitance between interconnects as the length of interconnects between elements increases. the result,
It has been difficult to expect high-speed characteristics from LSIs that are miniaturized from conventional CMOS circuits.
本発明の目的は超高集積回路において、消費電
力が少くて高速で動作する半導体素子を提供する
ことにある。この目的を達成するために本発明の
素子構造では、CMOS回路を含んだ集積回路に
おいて、電流駆動能力を著しく増大させて、高速
化を図ろうとするものである。
An object of the present invention is to provide a semiconductor element that consumes less power and operates at high speed in an ultra-highly integrated circuit. In order to achieve this object, the device structure of the present invention is intended to significantly increase the current driving capability of an integrated circuit including a CMOS circuit, thereby increasing the speed of the integrated circuit.
本発明を応用する主な回路を第１図と第２図に
示す。第１図に示す回路はCMOS回路の出力端
ＯにNPNトランジスタのベース端子を接続させ、
入力端子VINが低レベルの時にNPNトランジスタ
をON状態にして、大電流エミツタ端子OEから
取り出そうとするものである。この回路では、
CMOS単独で構成されたインバータ回路の駆動
電流よりも大きな電流をエミツタ端子OEから取
り出すことができるため、高速な動作が期待でき
る。第２図に示す回路は第１図に示したNPNト
ランジスタ端子OEをMOSトランジスタQ2のソー
ス端子に接続したインバータ回路である。いま
Q1をPMOS、Q2をNMOSとする。VINが低レベ
ルの時、Q1はON状態となり、電流はQ3のベース
に流れ、Q3はON状態となる。例えば端子Ｏに抵
抗Ｒを接続するとVINが低レベルの時、端子Ｏは
高レベルとなり、インバータ回路が構成される。
Main circuits to which the present invention is applied are shown in FIGS. 1 and 2. The circuit shown in Figure 1 connects the base terminal of an NPN transistor to the output terminal O of the CMOS circuit,
When the input terminal V IN is at a low level, the NPN transistor is turned on to draw a large current from the emitter terminal OE. In this circuit,
Since it is possible to extract a larger current from the emitter terminal OE than the drive current of an inverter circuit configured solely with CMOS, high-speed operation can be expected. The circuit shown in FIG. 2 is an inverter circuit in which the NPN transistor terminal OE shown in FIG. 1 is connected to the source terminal of the MOS transistor Q2 . now
Let Q 1 be PMOS and Q 2 be NMOS. When V IN is at a low level, Q 1 is in the ON state, current flows to the base of Q 3 , and Q 3 is in the ON state. For example, if a resistor R is connected to the terminal O, when V IN is at a low level, the terminal O becomes a high level, and an inverter circuit is formed.
以下本発明の一実施例を図面によつて詳しく説
明する。 An embodiment of the present invention will be described in detail below with reference to the drawings.
第３図は第１図に示した回路を構成する半導体
素子の断面構造図である。即ちＰ型基板３１上に
Ｎ型埋込層３２、Ｎ型エピタキシヤル層３３を成
長させ、エピタキシヤル層内にＰ型層３４，３５
を設け、PMOS，Q1を形成する。またＰ型層３
５と接して深いＰ型層３６を形成し、Ｐ型層３６
内にＮ型層３８，３９，３１０を形成し、NPN
トランジスタQ3、NMOSQ2を構成する。NMOS
とPMOSとのゲート電極を接続し、NPNトラン
ジスタQ3のコレクタ端子３１１を接続すれば、
第１図の回路となる。この様にすれば、CMOS
回路のNPNトランジスタを複合化させることが
できるため、面積の小さな高速の論理回路が実現
できる。 FIG. 3 is a cross-sectional structural diagram of a semiconductor element constituting the circuit shown in FIG. 1. That is, an N-type buried layer 32 and an N-type epitaxial layer 33 are grown on a P-type substrate 31, and P-type layers 34 and 35 are grown in the epitaxial layer.
and form PMOS, Q 1 . Also, P-type layer 3
A deep P-type layer 36 is formed in contact with the P-type layer 36.
N-type layers 38, 39, 310 are formed inside the NPN
Configures transistor Q 3 and NMOSQ 2 . NMOS
If we connect the gate electrodes of and PMOS and connect the collector terminal 311 of NPN transistor Q3 , we get
The circuit shown in Figure 1 is obtained. If you do this, CMOS
Since it is possible to combine NPN transistors in a circuit, a high-speed logic circuit with a small area can be realized.
第４図は第２図に示した回路を構成する半導体
素子の断面構造図である。Ｐ型基板４１の上にＮ
型埋込層４２を形成し、Ｎ型エピタキシヤル層４
３を成長させ、その内部にＰ型層４４，４５，４
６を形成し、Ｐ型層４６内にＮ型層４９，４１０
を形成すると複合化されたトランジスタQ1，Q2，
Q3が構成できる。なおNPNトランジスタQ3のエ
ミツタ電極はNMOSのQ2のソース電極と同一と
なつている。 FIG. 4 is a cross-sectional structural diagram of a semiconductor element constituting the circuit shown in FIG. 2. N on the P type substrate 41
A type buried layer 42 is formed, and an N type epitaxial layer 4 is formed.
3, and P-type layers 44, 45, 4 are grown inside it.
6 and N-type layers 49 and 410 within the P-type layer 46.
The composite transistors Q 1 , Q 2 ,
Q 3 can be configured. Note that the emitter electrode of the NPN transistor Q3 is the same as the source electrode of the NMOS transistor Q2 .
第５図は本発明を実現させるための半導体素子
の製造工程を示したものである。以下第５図ａ，
ｂ，ｃ，ｄの各図について説明する。 FIG. 5 shows the manufacturing process of a semiconductor device for realizing the present invention. Below, Figure 5a,
Each figure b, c, and d will be explained.
第５図ａにおいて、まずＰ型基板５１にＮ型埋
込層５２を形成した後、Ｎ型エピタキシヤル層５
３を成長させる。次に素子分離領域としてＰ型拡
散層５２１を形成する。熱酸化膜５２０を形成
し、イオン打込法でＰ型領域５６を５３の１部に
形成する。 In FIG. 5a, first, an N-type buried layer 52 is formed on a P-type substrate 51, and then an N-type epitaxial layer 5 is formed.
Grow 3. Next, a P-type diffusion layer 521 is formed as an element isolation region. A thermal oxide film 520 is formed, and a P-type region 56 is formed in a portion of 53 by ion implantation.
次に第５図ｂにおいては窒化膜（Si3N4）を全
面に堆積し、NPNトランジスタNMOS，PMOS
を形成する個所のみに窒化膜５２２を残して酸化
し、厚い酸化膜５７を形成する。次にNPNトラ
ンジスタのコレクタ領域５２３をＮ型高濃度に拡
散する。 Next, in Fig. 5b, a nitride film (Si 3 N 4 ) is deposited on the entire surface, and NPN transistors NMOS and PMOS are formed.
A thick oxide film 57 is formed by oxidizing, leaving the nitride film 522 only at the location where it is to be formed. Next, the collector region 523 of the NPN transistor is diffused to a high concentration of N type.
第５図ｃにおいては窒化膜５２２を除去し、酸
化膜５２０を除去した後、再度酸化し、ゲート酸
化膜５２４を形成し、多結晶シリコン層を堆積
し、PMOSゲート５２５、NMOSゲート５２６
をパターニングする。次にＰ型不純物を拡散し、
Ｐ型領域５４，５５を形成する。なお薄膜の５２
６は不純物拡散用のマスクである。 In FIG. 5c, after the nitride film 522 is removed and the oxide film 520 is removed, it is oxidized again, a gate oxide film 524 is formed, a polycrystalline silicon layer is deposited, and a PMOS gate 525 and an NMOS gate 526 are deposited.
pattern. Next, diffuse P-type impurities,
P-type regions 54 and 55 are formed. In addition, 52 of the thin film
6 is a mask for impurity diffusion.
第５図ｄにおいては、PMOS領域のQ1の部分
をおおい、Ｎ型領域５８，５９，５１０を形成
し、ゲート電極５２５，５２６を酸化膜５１２，
５１３で保護して金属電極を形成すれば、第３図
に示した断面構造が実現できる。 In FIG. 5d, the Q 1 portion of the PMOS region is covered, N-type regions 58, 59, and 510 are formed, and gate electrodes 525 and 526 are covered with an oxide film 512,
If a metal electrode is formed while being protected by 513, the cross-sectional structure shown in FIG. 3 can be realized.
第６図は第１図の回路を実現させるための第２
の実施例である。本実施例ではNPNトランジス
タQ3の電流増幅率を増加させるためにＰ型領域
６６′の拡散深さをNMOSを形成するＰ型領域の
６６の拡散深さよりも浅くしている。 Figure 6 shows the second circuit for realizing the circuit in Figure 1.
This is an example. In this embodiment, in order to increase the current amplification factor of the NPN transistor Q3 , the diffusion depth of the P-type region 66' is made shallower than the diffusion depth of the P-type region 66 forming the NMOS.
第７図は第６図の実施例の目的と同様に、
NPNトランジスタQ3の電流増加率を増加させた
構造であるが、Ｎ型エミツタ領域６８の深さを
NMOSのソース・ドレイン領域６９，６１０の
深さよりも深く形成したものである。第６図、第
７図の実施例は何れもCMOS回路のラツチアツ
プ対策として、非常に有効な素子構造となる。 FIG. 7 has the same purpose as the embodiment shown in FIG.
This structure increases the current increase rate of the NPN transistor Q3 , but the depth of the N-type emitter region 68 is
It is formed deeper than the depth of the source/drain regions 69 and 610 of the NMOS. Both the embodiments shown in FIGS. 6 and 7 have device structures that are very effective as a countermeasure against latch-up in CMOS circuits.
第８図は第６図に示した断面構造の実施例を、
インバータ回路に応用した例を示す。Q1−１，
Q2−１，Q3−１およびQ1−２，Q2−２，Q3−２
は、それぞれ第６図のQ1，Q2，Q3に対応するト
ランジスタである。 FIG. 8 shows an example of the cross-sectional structure shown in FIG.
An example of application to an inverter circuit is shown. Q 1 -1,
Q 2 -1, Q 3 -1 and Q 1 -2, Q 2 -2, Q 3 -2
are transistors corresponding to Q 1 , Q 2 , and Q 3 in FIG. 6, respectively.
第９図は１ゲートのインバータ断面構造を示し
たものである。本インバータ構造では、順方向動
作で用いるNPNトランジスタQ3−２と、逆方向
動作で用いるnpnトランジスタQ3−１とを、使用
しているため、N+埋込層９２を１つだけ形成す
ればよい。第９図で、Q1−１，Q1−２はPMOS
であり、Q2−１，Q2−２はNMOSであり、Q3−
１，Q3−２はNPNトランジスタである。また９
１はＰ型基板、９２はＮ型埋込層、９４はＰ型多
結晶層、９７は酸化膜を示している。 FIG. 9 shows a cross-sectional structure of a one-gate inverter. In this inverter structure, since the NPN transistor Q 3 -2 used in forward direction operation and the NPN transistor Q 3 -1 used in reverse direction operation are used, only one N + buried layer 92 needs to be formed. Bye. In Figure 9, Q 1 -1 and Q 1 -2 are PMOS
, Q 2 −1, Q 2 −2 are NMOS, and Q 3 −
1, Q 3 -2 is an NPN transistor. Also 9
1 is a P-type substrate, 92 is an N-type buried layer, 94 is a P-type polycrystalline layer, and 97 is an oxide film.
以上述べた様に、本発明によれば、MOSトラ
ンジスタとバイポーラトランジスタとを有効に組
み合わせ、複合化することにより、回路素子を高
速に動作させることができ、かつ消費電力を低減
できるという大きな効果がある。
As described above, according to the present invention, by effectively combining and compounding MOS transistors and bipolar transistors, circuit elements can be operated at high speed and power consumption can be reduced. be.
特に、相補型MOS回路の出力端にバイポーラ
トランジスタのベースを接続した、BiCMOSゲ
ート回路を構成する際、一方のMOSトランジス
タの基板領域を、他方のMOSトランジスタのド
レインを介して、配線をせずに、自らのソースに
接続できる効果が有る。 In particular, when configuring a BiCMOS gate circuit in which the base of a bipolar transistor is connected to the output end of a complementary MOS circuit, the substrate area of one MOS transistor is connected through the drain of the other MOS transistor without wiring. , which has the effect of connecting to its own source.
さらに、バイポーラトランジスタのベースを、
配線をせずに、相補型MOS回路の出力端に接続
できる効果が有る。 Furthermore, the base of the bipolar transistor is
This has the effect of being able to connect to the output end of a complementary MOS circuit without wiring.
従つて、簡略な素子構造を有し、素子面積が大
幅に低減されたBiCMOSゲート回路が構成でき
る効果が有る。 Therefore, there is an effect that a BiCMOS gate circuit having a simple element structure and a significantly reduced element area can be constructed.
第１図および第２図は本発明に応用した基本回
路図、第３図は第１図の回路を実現した本発明に
よる素子の断面構造図、第４図は第２図の回路を
実現した本発明による素子の断面構造図、第５図
は本発明を実現する素子製作工程の各段階におけ
る断面構造図、第６図と第７図は第１図の回路を
実現した他の実施例、第８図と第９図は本発明を
インバータ回路に応用した場合の断面構造図を示
す。
VIN……電圧入力端子、OE……エミツタ出力端
子、Q1……PMOS、Q2……NMOS、Q3……
NPNトランジスタ、３１……Ｐ型基板、３２…
…Ｎ型埋込層、３３……Ｎ型エピタキシヤル層、
３４，３５……Ｐ型層、３６……Ｐ型層、３７…
…酸化シリコン、３８，３９，３１０……Ｎ型
層、３１１……コレクタ端子。
Figures 1 and 2 are basic circuit diagrams applied to the present invention, Figure 3 is a cross-sectional structural diagram of an element according to the present invention that realizes the circuit of Figure 1, and Figure 4 shows that the circuit of Figure 2 is realized. FIG. 5 is a cross-sectional structure diagram of the device according to the present invention at each stage of the device manufacturing process to realize the present invention, FIGS. 6 and 7 are other embodiments realizing the circuit of FIG. 1, FIGS. 8 and 9 show cross-sectional structural views when the present invention is applied to an inverter circuit. V IN ... Voltage input terminal, OE... Emitter output terminal, Q 1 ... PMOS, Q 2 ... NMOS, Q 3 ...
NPN transistor, 31...P-type substrate, 32...
...N-type buried layer, 33...N-type epitaxial layer,
34, 35...P type layer, 36...P type layer, 37...
...Silicon oxide, 38, 39, 310...N type layer, 311...Collector terminal.
Claims (1)
形成された第１導電型と反対の第２導電型の第１
領域と、上記第１領域中に設けられた第１導電型
の第２領域および第３領域と、 上記第３領域中に設けられた第２導電型の第４
領域、第５領域および第６領域とを有し、 上記第２領域と上記第３領域の間の、上記第１
領域の表面上に、絶縁膜を介して第１のゲート電
極を有し、上記第２領域と上記第３領域と上記第
１のゲート電極とによつて、第１の電界効果トラ
ンジスタが形成されてなり、 上記第４領域と上記第５領域の間の、上記第３
領域の表面上に、絶縁膜を介して第２のゲート電
極を有し、上記第４領域と上記第５領域と上記第
２のゲート電極とによつて、上記第１の電界効果
トランジスタと反対極性の、第２の電界効果トラ
ンジスタが形成されてなり、 上記第６領域をエミツタ（もしくはコレクタ）
とし、上記第６領域直下の上記第３領域をベース
とし、上記第６領域の下方の上記第１領域をコレ
クタ（もしくはエミツタ）とするバイポーラトラ
ンジスタが形成されてなり、 上記第１の電界効果トランジスタのソース（も
しくはドレイン）と、上記第２の電界効果トラン
ジスタの基板領域と、上記バイポーラトランジス
タのベースとが、上記第３領域によつて互いに接
続されてなり、 上記第１および第２の電界効果トランジスタ
と、上記バイポーラトランジスタとによつて、
BiCMOS複合回路が形成されてなることを特徴
とする半導体装置。 ２ 上記第６領域と上記第５領域とが、同一の第
２導電型領域として、一体形成されていることを
特徴とする特許請求の範囲第１項記載の半導体装
置。 ３ 上記第６領域直下の第３領域の厚さが、上記
第５領域および第４領域直下の第３領域の厚さよ
りも、小さく形成されてなることを特徴とする特
許請求の範囲第１項記載の半導体装置。 ４ 上記第６領域の深さが、上記第５領域または
第４領域の深さよりも、大きく形成されてなるこ
とを特徴とする特許請求の範囲第３項記載の半導
体装置。[Scope of Claims] 1. A semiconductor substrate of a first conductivity type, and a first semiconductor substrate of a second conductivity type opposite to the first conductivity type formed on the surface of the substrate.
a second region and a third region of the first conductivity type provided in the first region; and a fourth region of the second conductivity type provided in the third region.
region, a fifth region, and a sixth region, the first region between the second region and the third region.
A first gate electrode is provided on the surface of the region via an insulating film, and a first field effect transistor is formed by the second region, the third region, and the first gate electrode. and the third area between the fourth area and the fifth area.
A second gate electrode is provided on the surface of the region via an insulating film, and the fourth region, the fifth region, and the second gate electrode are arranged opposite to the first field effect transistor. A polar second field effect transistor is formed, and the sixth region serves as an emitter (or collector).
A bipolar transistor is formed having the third region immediately below the sixth region as a base and the first region below the sixth region serving as a collector (or emitter), and the first field effect transistor The source (or drain) of the second field effect transistor, the substrate region of the second field effect transistor, and the base of the bipolar transistor are connected to each other by the third region, and the first and second field effect transistors are connected to each other by the third region. By the transistor and the bipolar transistor,
A semiconductor device characterized by forming a BiCMOS composite circuit. 2. The semiconductor device according to claim 1, wherein the sixth region and the fifth region are integrally formed as regions of the same second conductivity type. 3. Claim 1, characterized in that the thickness of the third region immediately below the sixth region is smaller than the thickness of the third region immediately below the fifth region and the fourth region. The semiconductor device described. 4. The semiconductor device according to claim 3, wherein the depth of the sixth region is greater than the depth of the fifth region or the fourth region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17841282A JPS5968962A (en) | 1982-10-13 | 1982-10-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17841282A JPS5968962A (en) | 1982-10-13 | 1982-10-13 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5968962A JPS5968962A (en) | 1984-04-19 |
| JPH056350B2 true JPH056350B2 (en) | 1993-01-26 |
Family
ID=16048036
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17841282A Granted JPS5968962A (en) | 1982-10-13 | 1982-10-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5968962A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5226181A (en) * | 1975-08-22 | 1977-02-26 | Nippon Telegr & Teleph Corp <Ntt> | Semi-conductor integrated circuit unit |
| JPS5246785A (en) * | 1975-10-13 | 1977-04-13 | Seiko Epson Corp | Semiconductor integrated circuit |
| JPS53126252A (en) * | 1977-04-11 | 1978-11-04 | Hitachi Ltd | Output circuit |
| JPS54131887A (en) * | 1978-04-04 | 1979-10-13 | Oki Electric Ind Co Ltd | Manufacture of bipolar cmos-type integrated circuit |
-
1982
- 1982-10-13 JP JP17841282A patent/JPS5968962A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5226181A (en) * | 1975-08-22 | 1977-02-26 | Nippon Telegr & Teleph Corp <Ntt> | Semi-conductor integrated circuit unit |
| JPS5246785A (en) * | 1975-10-13 | 1977-04-13 | Seiko Epson Corp | Semiconductor integrated circuit |
| JPS53126252A (en) * | 1977-04-11 | 1978-11-04 | Hitachi Ltd | Output circuit |
| JPS54131887A (en) * | 1978-04-04 | 1979-10-13 | Oki Electric Ind Co Ltd | Manufacture of bipolar cmos-type integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5968962A (en) | 1984-04-19 |
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